From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8423D21CF3B8D for ; Tue, 4 Jul 2017 09:55:01 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7D98061D12; Tue, 4 Jul 2017 16:56:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7D98061D12 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 7D98061D12 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id B64825D968; Tue, 4 Jul 2017 16:56:38 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen Date: Tue, 4 Jul 2017 18:56:26 +0200 Message-Id: <20170704165629.13610-6-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 04 Jul 2017 16:56:39 +0000 (UTC) Subject: [PATCH v2 5/8] OvmfPkg/IndustryStandard/Q35MchIch9.h: add extended TSEG size macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 16:55:01 -0000 Add the macros for interfacing with the QEMU feature added in QEMU commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08). Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index f480455ae432..68485bec71f7 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -29,14 +29,17 @@ #define INTEL_Q35_MCH_DEVICE_ID 0x29C0 // // B/D/F/Type: 0/0/0/PCI // #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) +#define MCH_EXT_TSEG_MB 0x50 +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF + #define MCH_GGC 0x52 #define MCH_GGC_IVD BIT1 #define MCH_PCIEXBAR_LOW 0x60 #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF #define MCH_PCIEXBAR_BUS_FF 0 #define MCH_PCIEXBAR_EN BIT0 @@ -50,14 +53,15 @@ #define MCH_ESMRAMC 0x9E #define MCH_ESMRAMC_H_SMRAME BIT7 #define MCH_ESMRAMC_E_SMERR BIT6 #define MCH_ESMRAMC_SM_CACHE BIT5 #define MCH_ESMRAMC_SM_L1 BIT4 #define MCH_ESMRAMC_SM_L2 BIT3 +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) #define MCH_ESMRAMC_TSEG_8MB BIT2 #define MCH_ESMRAMC_TSEG_2MB BIT1 #define MCH_ESMRAMC_TSEG_1MB 0 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) #define MCH_ESMRAMC_T_EN BIT0 #define MCH_GBSM 0xA4 -- 2.13.1.3.g8be5a757fa67