From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A4F5921CF3B97 for ; Tue, 4 Jul 2017 09:55:02 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A040D285B1; Tue, 4 Jul 2017 16:56:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A040D285B1 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com A040D285B1 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id D3E3C4FA21; Tue, 4 Jul 2017 16:56:39 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen Date: Tue, 4 Jul 2017 18:56:27 +0200 Message-Id: <20170704165629.13610-7-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 04 Jul 2017 16:56:40 +0000 (UTC) Subject: [PATCH v2 6/8] OvmfPkg/SmmAccess: support extended TSEG size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 16:55:02 -0000 In SmmAccessPeiEntryPoint(), map TSEG megabyte counts different from 1, 2 and 8 to the MCH_ESMRAMC_TSEG_EXT bit pattern (introduced in the previous patch), for the ESMRAMC.TSEG_SZ bit-field register. (Suggested by Jordan.) In SmramAccessGetCapabilities() -- backing both PEI_SMM_ACCESS_PPI.GetCapabilities() and EFI_SMM_ACCESS2_PROTOCOL.GetCapabilities() --, map the MCH_ESMRAMC_TSEG_EXT bit pattern found in the ESMRAMC.TSEG_SZ bit-field register to a byte count of (mQ35TsegMbytes * SIZE_1MB). (MCH_ESMRAMC_TSEG_EXT is the only possible pattern if none of MCH_ESMRAMC_TSEG_1MB, MCH_ESMRAMC_TSEG_2MB, and MCH_ESMRAMC_TSEG_8MB match.) The new code paths are not exercised just yet; for that, PlatformPei is going to have to set PcdQ35TsegMbytes (and consequently, SmramInternal's "mQ35TsegMbytes") to a value different from 1, 2, and 8. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccessPei.c | 3 ++- OvmfPkg/SmmAccess/SmramInternal.c | 8 +++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c index aba3aeb9f4bd..0d00140dc92f 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -326,15 +326,16 @@ SmmAccessPeiEntryPoint ( // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is // *restricted* to SMM. // EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK; EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB : mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB : - MCH_ESMRAMC_TSEG_1MB; + mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB : + MCH_ESMRAMC_TSEG_EXT; EsmramcVal |= MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); // // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. // diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c index ae1e9069aca6..fa0efeda72b0 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -192,14 +192,16 @@ SmramAccessGetCapabilities ( // The second region is the main one, following the first. // SmramMap[DescIdxMain].PhysicalStart = SmramMap[DescIdxSmmS3ResumeState].PhysicalStart + SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart; SmramMap[DescIdxMain].PhysicalSize = - (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB : - TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB : - SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; + (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB : + TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB : + TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB : + mQ35TsegMbytes * SIZE_1MB) - + SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; SmramMap[DescIdxMain].RegionState = CommonRegionState; return EFI_SUCCESS; } -- 2.13.1.3.g8be5a757fa67