From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C49E2095D2C9 for ; Mon, 10 Jul 2017 00:47:27 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2017 00:49:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,339,1496127600"; d="scan'208";a="109448016" Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.198.17]) by orsmga002.jf.intel.com with ESMTP; 10 Jul 2017 00:46:08 -0700 From: zwei4 To: edk2-devel@lists.01.org Date: Mon, 10 Jul 2017 15:46:04 +0800 Message-Id: <20170710074604.16320-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] LPDDR4 Configuration. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Jul 2017 07:47:27 -0000 Change LPDDR4 configuration for Benson Glacier. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- .../BensonGlacier/BoardInitPreMem/BoardInitMiscs.c | 34 +++++++++++++++++----- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c index bb1c9bfae..5424df06f 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/BoardInitMiscs.c @@ -83,13 +83,6 @@ BgUpdateFspmUpd ( } } - // - // override RankEnable settings for Benson - // - FspUpdRgn->FspmConfig.Ch0_RankEnable = 1; - FspUpdRgn->FspmConfig.Ch1_RankEnable = 1; - FspUpdRgn->FspmConfig.Ch2_RankEnable = 1; - FspUpdRgn->FspmConfig.Ch3_RankEnable = 1; DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n")); Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid); @@ -104,10 +97,37 @@ BgUpdateFspmUpd ( ASSERT (FALSE); } + FspUpdRgn->FspmConfig.Package = 1; + FspUpdRgn->FspmConfig.Profile = 11; + FspUpdRgn->FspmConfig.MemoryDown = 1; + FspUpdRgn->FspmConfig.DDR3LPageSize = 0; + FspUpdRgn->FspmConfig.DDR3LASR = 0; + FspUpdRgn->FspmConfig.MemorySizeLimit = 0x1800; + FspUpdRgn->FspmConfig.DIMM0SPDAddress = 0; + FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0; + FspUpdRgn->FspmConfig.DDR3LPageSize = 0; + FspUpdRgn->FspmConfig.DDR3LASR = 0; + + FspUpdRgn->FspmConfig.Ch0_RankEnable = 1; + FspUpdRgn->FspmConfig.Ch0_DeviceWidth = 2; FspUpdRgn->FspmConfig.Ch0_DramDensity = 2; + FspUpdRgn->FspmConfig.Ch0_Option = 3; + + FspUpdRgn->FspmConfig.Ch1_RankEnable = 1; + FspUpdRgn->FspmConfig.Ch1_DeviceWidth = 2; FspUpdRgn->FspmConfig.Ch1_DramDensity = 2; + FspUpdRgn->FspmConfig.Ch1_Option = 3; + + FspUpdRgn->FspmConfig.Ch2_RankEnable = 1; + FspUpdRgn->FspmConfig.Ch2_DeviceWidth = 2; FspUpdRgn->FspmConfig.Ch2_DramDensity = 2; + FspUpdRgn->FspmConfig.Ch2_Option = 3; + + FspUpdRgn->FspmConfig.Ch3_RankEnable = 1; + FspUpdRgn->FspmConfig.Ch3_DeviceWidth = 2; FspUpdRgn->FspmConfig.Ch3_DramDensity = 2; + FspUpdRgn->FspmConfig.Ch3_Option = 3; + return EFI_SUCCESS; } -- 2.11.0.windows.1