From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3709E2095D8E5 for ; Thu, 13 Jul 2017 10:29:35 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id f67so33393088wmh.1 for ; Thu, 13 Jul 2017 10:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=46jscOoIoj1tt+B6R8JksFgPiJR7inm4P6r57oFot/k=; b=UqdLS0qJdnbJgMPmtySsM21q0clI3/m1zfILDr2cNz2kQA1y7fs2wp7jy+sMJrt84r gCwSFP/VPZzoIEYut4s0Q3uWT1Km9SKi3MMhMcwr0Mux1QvX/MjEUHgKALNnq1cssdAu QuxF1A4UxG0T6i9WUmu06h9pEHCKufqHo1ViY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=46jscOoIoj1tt+B6R8JksFgPiJR7inm4P6r57oFot/k=; b=Au0QxCWE9zqfpJ1SSU6mBl4vGdR77Gx2sm7Rz4NcstNSZ3yI4YKnrA2UfbHqKPBA2f EVBER0hQYTqqdSF5izpMQdfj4ToIZ2HQxnOmJ5aAlFaNAzoBwueehwMJKQm+yvZeQF00 h6huuwrz43O95TRH3dvZ5TI1Kx7X8gl+pe/m6t+MBPMUFgN7AtDBcY7FVWJ0EUMzqTnu ejMzD0QtHv1TWgy1/0AEjwZwl6I63H2fDwOvXxuMBNHGFU93t+MdkZX8BqI1GTSPT2kd cspW2VwY3bSVc8xl2cJbPsJ1CdpH/y3SCNGGTGTWztVjYfBklQwXpQf2P+gOCmk/NKHn Shrw== X-Gm-Message-State: AIVw112Ya7UQSgdefFL/xoFp97nH4nW23LsYI7Jzamw63Dkx5GJkMQxQ WaggWriBfhlxtap+ X-Received: by 10.28.107.69 with SMTP id g66mr3108852wmc.110.1499967081884; Thu, 13 Jul 2017 10:31:21 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n71sm5300958wrb.62.2017.07.13.10.31.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 10:31:20 -0700 (PDT) Date: Thu, 13 Jul 2017 18:31:19 +0100 From: Leif Lindholm To: Alexei Fedorov Cc: Ard Biesheuvel , "edk2-devel@lists.01.org" , "liming.gao@intel.com" , "yonghong.zhu@intel.com" , Evan Lloyd Message-ID: <20170713173119.GG26676@bivouac.eciton.net> References: <20170713124844.23556-1-ard.biesheuvel@linaro.org> <20170713124844.23556-2-ard.biesheuvel@linaro.org> <20170713141147.GD26676@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 2/2] BaseTools/tools_def AARCH64: avoid SIMD register in XIP code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Jul 2017 17:29:35 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline How are you ending up with all of those -O3? Are they hardwired in the toolchain? Are you adding that manually? Can you see if the issue is reproducible with aarch64-linux-gnu, which will have a configuration matching more closely what we tend to use? (Not as a solution, just looking for a workaround better than "don't build with GCC7.) / Leif On Thu, Jul 13, 2017 at 05:06:43PM +0000, Alexei Fedorov wrote: > -mgeneral-regs-only is already there: > > See the top of generated .S file: > > > .arch armv8-a > .file "" > // GNU GIMPLE (Linaro GCC 7.1-2017.05) version 7.1.1 20170510 (aarch64-elf) > // compiled by GNU C version 4.8.2, GMP version 6.1.2, MPFR version 3.1.5, MPC version 1.0.3, isl version none > // GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072 > // options passed: -mlittle-endian -mcmodel=tiny -march=armv8-a -mabi=lp64 > // -mstrict-align -mgeneral-regs-only -mlittle-endian -mcmodel=tiny > // -march=armv8-a -mabi=lp64 > // -auxbase-strip ArmVeNorFlashDxe.dll.ltrans0.ltrans.o -g -g -O3 -O3 -Os > // -Os -O3 -Wno-lto-type-mismatch -Wno-array-bounds > > > ________________________________ > From: Ard Biesheuvel > Sent: 13 July 2017 18:00:43 > To: Alexei Fedorov > Cc: Leif Lindholm; edk2-devel@lists.01.org; liming.gao@intel.com; yonghong.zhu@intel.com; Evan Lloyd > Subject: Re: [PATCH 2/2] BaseTools/tools_def AARCH64: avoid SIMD register in XIP code > > On 13 July 2017 at 17:56, Alexei Fedorov wrote: > > I'm getting > > > > > > UEFI firmware (version built at 16:34:57 on Jul 13 2017) > > Synchronous Exception at 0x00000000F5451338 > > : > > > > EL2:0x00000000F5451338 : LDR q0,[x9,x0] > > EL2:0x00000000F545133C : ADD x1,x1,#1 > > EL2:0x00000000F5451340 : CMP x7,x1 > > EL2:0x00000000F5451344 : STR q0,[x2,x0] > > EL2:0x00000000F5451348 : ADD x0,x0,#0x10 > > EL2:0x00000000F545134C : B.HI {pc}-0x14 ; 0xf5451338 > > ... > > > > with X0=0 & X9 = 0x000000000BFD0008 (Flash memory) in AlignedCopyMem() > > function > > > > (edk2\ArmPlatformPkg\Drivers\NorFlashDxe\NorFlashDxe.c): > > > > > > // r:\edk2\ArmPlatformPkg\Drivers\NorFlashDxe\NorFlashDxe.c:784: > > *Destination64++ = *Source64++; > > .loc 10 784 0 > > ldr q0, [x9, x0] // MEM[base: vectp.229_593, index: > > ivtmp.349_1117, offset: 0B], MEM[base: vectp.229_593, index: ivtmp.349_1117, > > offset: 0B] > > add x1, x1, 1 // ivtmp_603, ivtmp_603, > > cmp x7, x1 // bnd.223, ivtmp_603 > > str q0, [x2, x0] // MEM[base: vectp.229_593, index: > > ivtmp.349_1117, offset: 0B], MEM[base: vectp_Buffer.232_598, index: > > ivtmp.349_1117, offset: 0B] > > add x0, x0, 16 // ivtmp.349, ivtmp.349, > > bhi .L200 //, > > > > > > Despite compiler option -mgeneral-regs-only: > > > > // -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -mgeneral-regs-only > > // -mlittle-endian -mpc-relative-literal-loads -mstrict-align > > (see attached assembly generated file) > > > > That is the same compiler bug at work, I think. So we need to add > -mgeneral-regs-only for this module as well. > > Perhaps we should simply set it globally? Leif? > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.