[Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] WIFI Pin Setting

[Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] WIFI Pin Setting

[zwei4]

Configure GPIO pins of on-board WIFI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
---
 .../Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h              | 4 ++--
 .../Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl   | 8 +++-----
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
index 1bf848995..77d409026 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/BoardGpios.h
@@ -73,7 +73,7 @@ BXT_GPIO_PAD_INIT  mMinnow3_GpioInitData_N[] =
   BXT_GPIO_PAD_CONF(L"GPIO_7",                   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_L,   NA    ,    NA,   HizRx0I,   SAME, GPIO_PADBAR+0x0038,  NORTH),//Mux with DISP1_TOUCH_INT_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_8",                   M1   ,    NA    ,  NA   ,  NA    ,   NA       , Wake_Disabled, P_20K_L,   NA    ,    NA,   HizRx0I,   SAME, GPIO_PADBAR+0x0040,  NORTH),//Mux with DISP1_TOUCH_RST_N based on the SW3 switch
   BXT_GPIO_PAD_CONF(L"GPIO_9",                   M1   ,    NA    ,  NA    ,  NA    ,   NA      , Wake_Disabled, P_20K_L,    NA    ,   NA     ,NA   ,     NA, GPIO_PADBAR+0x0048,  NORTH),//Feature: LB
-  BXT_GPIO_PAD_CONF(L"GPIO_10",                  M0   ,    GPO   , GPIO_D ,  HI   ,   Level    , Wake_Enabled , P_20K_L,    NA,     NA,   TxDRxE ,     NA, GPIO_PADBAR+0x0050,  NORTH),//Feature: LB     
+  BXT_GPIO_PAD_CONF(L"GPIO_10",                  M0   ,    GPO   , GPIO_D ,  LO   ,   Level    , Wake_Enabled , P_20K_L,    NA,     NA,       NA   ,     NA, GPIO_PADBAR+0x0050,  NORTH),//Feature: LB     
   BXT_GPIO_PAD_CONF(L"GPIO_11",                  M1   ,    NA    , NA    ,  NA    ,   NA       , Wake_Disabled, P_20K_L,    NA   ,    NA     ,NA   ,     NA, GPIO_PADBAR+0x0058,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_12",                  M1   ,    NA    , NA    ,  NA    ,   NA       , Wake_Enabled , P_20K_L,    NA   ,    NA     ,NA   ,     NA, GPIO_PADBAR+0x0060,  NORTH),//Feature: LB
   BXT_GPIO_PAD_CONF(L"GPIO_13",                  M1   ,    NA    , NA    ,  NA    ,   NA       , Wake_Disabled, P_20K_L,    NA   ,    NA     ,NA   ,     NA, GPIO_PADBAR+0x0068,  NORTH),//Feature: LB
@@ -259,7 +259,7 @@ BXT_GPIO_PAD_INIT  mMinnow3_GpioInitData_W [] =
   BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5",      M0   ,    GPO   ,GPIO_D,   HI    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,NA        ,  NA  ,  GPIO_PADBAR+0x00A8,  WEST),//Feature: RF_KILL_WWAN           Net in Sch: NGFF_WWAN_RF_KILL_1P8_N
   BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6",      M2   ,    NA  ,   NA    ,  NA    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,NA        ,  NA  ,  GPIO_PADBAR+0x00B0,  WEST),//Feature: AVS_I2S5_SDI
   BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7",      M1   ,    NA    , NA   ,   NA    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,IOS_Masked,  SAME,  GPIO_PADBAR+0x00B8,  WEST),
-  BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8",      M0   ,    GPO   ,GPIO_D,   HI    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,NA        ,  NA  ,  GPIO_PADBAR+0x00C0,  WEST),//Feature: BT_Disable             Net in Sch: BT_DISABLE2_1P8_N
+  BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8",      M0   ,    GPO   ,GPIO_D,   LO    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,NA        ,  NA  ,  GPIO_PADBAR+0x00C0,  WEST),//Feature: BT_Disable             Net in Sch: BT_DISABLE2_1P8_N
   BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9",      M2   ,    NA    , NA   ,   NA    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA,IOS_Masked,  SAME,  GPIO_PADBAR+0x00C8,  WEST),//CG2000 PDB: If PDB = 0: power-down; If PDB = 1: power-up, it is the same in ISH/LPSS mode
   BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B",  M1   ,    NA    , NA   ,   NA    ,   NA      ,  Wake_Disabled, P_NONE,    NA    ,    NA, HizRx0I,  EnPd,     GPIO_PADBAR+0x00D0,  WEST),
   BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B",  M1   ,    NA    , NA   ,   NA    ,   NA      ,  Wake_Disabled, P_20K_L,   NA    ,    NA, HizRx0I,  EnPd,     GPIO_PADBAR+0x00D8,  WEST),
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
index ed4b285ac..7d0fa4ba8 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/LBEE5KL1DX.asl
@@ -12,9 +12,7 @@
 **/
 
 /*
- GPIO_10 for Wi-Fi direct IRQ 0x6D.
- GPIO_15 for Wi-Fi reset
- PMIC_STDBY for Wi-Fi disable, NW index 30
+ GPIO_10 for Wi-Fi Kill.
 */
 
 
@@ -45,13 +43,13 @@ Scope(\_SB.PCI0.SDIO)
 
     Method (_PS3, 0, NotSerialized)
     {
-      Store( 0x00, \_SB.GPO0.CWLE )        // Put WiFi chip in Reset
+      Store( 0x01, \_SB.GPO0.CWLE )        // Disable
       Sleep(150)
     }
 
     Method (_PS0, 0, NotSerialized)
     {
-      Store( 0x01, \_SB.GPO0.CWLE )      // Take WiFi chip out in Reset
+      Store( 0x00, \_SB.GPO0.CWLE )        // Enable
       Sleep(150)
     }
   }
-- 
2.11.0.windows.1