From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22d.google.com (mail-wm0-x22d.google.com [IPv6:2a00:1450:400c:c09::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D2F121C9E7D9 for ; Mon, 17 Jul 2017 09:27:25 -0700 (PDT) Received: by mail-wm0-x22d.google.com with SMTP id w126so81187802wme.0 for ; Mon, 17 Jul 2017 09:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=eSejlbN4gs6dIUyhQiIsoFuD650GACNeZowYSsCFFZg=; b=Y9LVb4MkhiKuVLlYAD7/Fr8DyV50ZgwW1Slxw8SZxVj5GIkdVyxsBbiKqJOQ6hsbYw BzdMmfLn8PlokTooKmXt4x9ej8hQ90+L0tsqqDJaFv++QaHteYHt7Ui/V61/55tsBCcT JIgnZCIDivoQu2rpUv+LZXeG/1Dn12UqEbb0k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=eSejlbN4gs6dIUyhQiIsoFuD650GACNeZowYSsCFFZg=; b=tSou1EKGUCgbCSr8JUomL5jwSw5FZ//zKMde4VG1NmCu5tmxQ1a42DxbiLwbwSDUqn mUY3EKrwaaGSSBcHIcN9EV/ydzeDki5NOwXytXvaLVn9fT3r1CvpYsVnGfR7MEO7xV/a rXmpTcNchkjJeoEJJbI8sIXX4q7G84we77smPhkFPiiJZSc+2sUbmGRAZ51DcHrhvwB6 yFGP0WikZzJtnIH+suJ2QLkfR1BlwAstEN9fAvIBmRD3lF+YwnpxExrYooyoaDNhQXNo lxiQY5AkjWy3P3frcVWcnk3viZJ8D+nmLwVK1jgtuPmA3QXxG3sfdV8au3BpVQwKW+Tr wi8w== X-Gm-Message-State: AIVw110iQhQ8SYJx0q7bO9AGrFnLTdZ47qEScHi9zqWP9RrW8meRmvYN ltXPfEDkOuhVMmGq X-Received: by 10.28.170.194 with SMTP id t185mr5545047wme.114.1500308956561; Mon, 17 Jul 2017 09:29:16 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 76sm7929224wmm.14.2017.07.17.09.29.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jul 2017 09:29:15 -0700 (PDT) Date: Mon, 17 Jul 2017 17:29:14 +0100 From: Leif Lindholm To: Jun Nie Cc: edk2-devel@lists.01.org, evan.lloyd@arm.com, Alexei.Fedorov@arm.com, ard.biesheuvel@linaro.org, shawn.guo@linaro.org, jason.liu@linaro.org Message-ID: <20170717162914.GN26676@bivouac.eciton.net> References: <1499419125-18297-1-git-send-email-jun.nie@linaro.org> MIME-Version: 1.0 In-Reply-To: <1499419125-18297-1-git-send-email-jun.nie@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v3] ArmPlatformPkg: Support different PL011 reg offset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Jul 2017 16:27:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jul 07, 2017 at 05:18:45PM +0800, Jun Nie wrote: > ZTE/SanChip version pl011 has different reg offset and bit offset > for some registers. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jun Nie Reviewed-by: Leif Lindholm Pushed as d4f6c35c84. > --- > ArmPlatformPkg/ArmPlatformPkg.dec | 1 + > ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf | 1 + > ArmPlatformPkg/Include/Drivers/PL011Uart.h | 31 ++++++++++++++++++++++++++ > 3 files changed, 33 insertions(+) > > diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec > index d756fd2..b8a6b13 100644 > --- a/ArmPlatformPkg/ArmPlatformPkg.dec > +++ b/ArmPlatformPkg/ArmPlatformPkg.dec > @@ -97,6 +97,7 @@ > gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 > gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D > gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F > + gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E > > ## PL011 Serial Debug UART > gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 > diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf > index 0154f3b..3fd4602 100644 > --- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf > +++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf > @@ -39,3 +39,4 @@ > > gArmPlatformTokenSpaceGuid.PL011UartInteger > gArmPlatformTokenSpaceGuid.PL011UartFractional > + gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant > diff --git a/ArmPlatformPkg/Include/Drivers/PL011Uart.h b/ArmPlatformPkg/Include/Drivers/PL011Uart.h > index d5e88e8..4957dbf 100644 > --- a/ArmPlatformPkg/Include/Drivers/PL011Uart.h > +++ b/ArmPlatformPkg/Include/Drivers/PL011Uart.h > @@ -18,7 +18,25 @@ > #include > #include > > +#define PL011_VARIANT_ZTE 1 > + > // PL011 Registers > +#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE > +#define UARTDR 0x004 > +#define UARTRSR 0x010 > +#define UARTECR 0x010 > +#define UARTFR 0x014 > +#define UARTIBRD 0x024 > +#define UARTFBRD 0x028 > +#define UARTLCR_H 0x030 > +#define UARTCR 0x034 > +#define UARTIFLS 0x038 > +#define UARTIMSC 0x040 > +#define UARTRIS 0x044 > +#define UARTMIS 0x048 > +#define UARTICR 0x04c > +#define UARTDMACR 0x050 > +#else > #define UARTDR 0x000 > #define UARTRSR 0x004 > #define UARTECR 0x004 > @@ -34,6 +52,7 @@ > #define UARTMIS 0x040 > #define UARTICR 0x044 > #define UARTDMACR 0x048 > +#endif > > #define UARTPID0 0xFE0 > #define UARTPID1 0xFE4 > @@ -47,6 +66,17 @@ > #define UART_STATUS_ERROR_MASK 0x0F > > // Flag reg bits > +#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE > +#define PL011_UARTFR_RI (1 << 0) // Ring indicator > +#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty > +#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full > +#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full > +#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty > +#define PL011_UARTFR_BUSY (1 << 8) // UART busy > +#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect > +#define PL011_UARTFR_DSR (1 << 3) // Data set ready > +#define PL011_UARTFR_CTS (1 << 1) // Clear to send > +#else > #define PL011_UARTFR_RI (1 << 8) // Ring indicator > #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty > #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full > @@ -56,6 +86,7 @@ > #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect > #define PL011_UARTFR_DSR (1 << 1) // Data set ready > #define PL011_UARTFR_CTS (1 << 0) // Clear to send > +#endif > > // Flag reg bits - alternative names > #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE > -- > 1.9.1 >