* [PATCH 0/2] IntelSiliconPkg/IntelVTdDxe: Code refinements
@ 2017-08-01 4:32 Hao Wu
2017-08-01 4:32 ` [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID Hao Wu
2017-08-01 4:32 ` [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks Hao Wu
0 siblings, 2 replies; 5+ messages in thread
From: Hao Wu @ 2017-08-01 4:32 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao
Cc: Jiewen Yao <jiewen.yao@intel.com>
Hao Wu (2):
IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID
IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks
IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 6 ++++--
IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
--
2.12.0.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID
2017-08-01 4:32 [PATCH 0/2] IntelSiliconPkg/IntelVTdDxe: Code refinements Hao Wu
@ 2017-08-01 4:32 ` Hao Wu
2017-08-01 4:56 ` Yao, Jiewen
2017-08-01 4:32 ` [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks Hao Wu
1 sibling, 1 reply; 5+ messages in thread
From: Hao Wu @ 2017-08-01 4:32 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
index 456a039bcd..d19aea2cc1 100644
--- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
+++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
@@ -158,7 +158,7 @@ InvalidateVtdIOTLBDomain (
Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));
Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_DOMAIN);
- Reg64 |= DomainIdentifier;
+ Reg64 |= LShiftU64 (DomainIdentifier, 32);
MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64);
do {
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks
2017-08-01 4:32 [PATCH 0/2] IntelSiliconPkg/IntelVTdDxe: Code refinements Hao Wu
2017-08-01 4:32 ` [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID Hao Wu
@ 2017-08-01 4:32 ` Hao Wu
2017-08-01 4:56 ` Yao, Jiewen
1 sibling, 1 reply; 5+ messages in thread
From: Hao Wu @ 2017-08-01 4:32 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Jiewen Yao
Add explicit NULL pointer check to make the codes more straight-forward.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
index 0cff2cc939..5af4a4627b 100644
--- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
@@ -862,6 +862,8 @@ SetAccessAttribute (
VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;
UINT64 Pt;
+ SecondLevelPagingEntry = NULL;
+
DEBUG ((DEBUG_INFO,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess));
VtdIndex = FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntry, &ContextEntry);
@@ -884,7 +886,7 @@ SetAccessAttribute (
SecondLevelPagingEntry = (VOID *)(UINTN)LShiftU64 (ExtContextEntry->Bits.SecondLevelPageTranslationPointer, 12);
DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
}
- } else {
+ } else if (ContextEntry != NULL) {
if (ContextEntry->Bits.Present == 0) {
SecondLevelPagingEntry = CreateSecondLevelPagingEntry (VtdIndex, 0);
DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
@@ -959,7 +961,7 @@ AlwaysEnablePageAttribute (
ExtContextEntry->Bits.SecondLevelPageTranslationPointer = Pt;
ExtContextEntry->Bits.DomainIdentifier = ((1 << (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
ExtContextEntry->Bits.Present = 1;
- } else {
+ } else if (ContextEntry != NULL) {
ContextEntry->Bits.SecondLevelPageTranslationPointer = Pt;
ContextEntry->Bits.DomainIdentifier = ((1 << (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
ContextEntry->Bits.Present = 1;
--
2.12.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID
2017-08-01 4:32 ` [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID Hao Wu
@ 2017-08-01 4:56 ` Yao, Jiewen
0 siblings, 0 replies; 5+ messages in thread
From: Yao, Jiewen @ 2017-08-01 4:56 UTC (permalink / raw)
To: Wu, Hao A, edk2-devel@lists.01.org
Reviewed-by: jiewen.yao@intel.com
> -----Original Message-----
> From: Wu, Hao A
> Sent: Tuesday, August 1, 2017 12:32 PM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain
> ID
>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> ---
> IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
> b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
> index 456a039bcd..d19aea2cc1 100644
> --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
> +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
> @@ -158,7 +158,7 @@ InvalidateVtdIOTLBDomain (
>
> Reg64 &= ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK));
> Reg64 |= (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_DOMAIN);
> - Reg64 |= DomainIdentifier;
> + Reg64 |= LShiftU64 (DomainIdentifier, 32);
> MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress +
> (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG,
> Reg64);
>
> do {
> --
> 2.12.0.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks
2017-08-01 4:32 ` [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL pointer checks Hao Wu
@ 2017-08-01 4:56 ` Yao, Jiewen
0 siblings, 0 replies; 5+ messages in thread
From: Yao, Jiewen @ 2017-08-01 4:56 UTC (permalink / raw)
To: Wu, Hao A, edk2-devel@lists.01.org; +Cc: Wu, Hao A
Reviewed-by: jiewen.yao@intel.com
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Hao
> Wu
> Sent: Tuesday, August 1, 2017 12:32 PM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: [edk2] [PATCH 2/2] IntelSiliconPkg/IntelVTdDxe: Add explicit NULL
> pointer checks
>
> Add explicit NULL pointer check to make the codes more straight-forward.
>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> ---
> IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
> b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
> index 0cff2cc939..5af4a4627b 100644
> --- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
> +++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c
> @@ -862,6 +862,8 @@ SetAccessAttribute (
> VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry;
> UINT64 Pt;
>
> + SecondLevelPagingEntry = NULL;
> +
> DEBUG ((DEBUG_INFO,"SetAccessAttribute (S%04x B%02x D%02x F%02x)
> (0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device,
> SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess));
>
> VtdIndex = FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntry,
> &ContextEntry);
> @@ -884,7 +886,7 @@ SetAccessAttribute (
> SecondLevelPagingEntry = (VOID *)(UINTN)LShiftU64
> (ExtContextEntry->Bits.SecondLevelPageTranslationPointer, 12);
> DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x
> B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus,
> SourceId.Bits.Device, SourceId.Bits.Function));
> }
> - } else {
> + } else if (ContextEntry != NULL) {
> if (ContextEntry->Bits.Present == 0) {
> SecondLevelPagingEntry = CreateSecondLevelPagingEntry (VtdIndex, 0);
> DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x
> B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment,
> SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
> @@ -959,7 +961,7 @@ AlwaysEnablePageAttribute (
> ExtContextEntry->Bits.SecondLevelPageTranslationPointer = Pt;
> ExtContextEntry->Bits.DomainIdentifier = ((1 <<
> (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
> ExtContextEntry->Bits.Present = 1;
> - } else {
> + } else if (ContextEntry != NULL) {
> ContextEntry->Bits.SecondLevelPageTranslationPointer = Pt;
> ContextEntry->Bits.DomainIdentifier = ((1 <<
> (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1);
> ContextEntry->Bits.Present = 1;
> --
> 2.12.0.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
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Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2017-08-01 4:32 [PATCH 0/2] IntelSiliconPkg/IntelVTdDxe: Code refinements Hao Wu
2017-08-01 4:32 ` [PATCH 1/2] IntelSiliconPkg/IntelVTdDxe: Fix typo for VTd IOTLB domain ID Hao Wu
2017-08-01 4:56 ` Yao, Jiewen
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