From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0E4D021D18243 for ; Wed, 16 Aug 2017 19:33:08 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2017 19:35:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,385,1498546800"; d="scan'208";a="1004628248" Received: from mdkinney-mobl1.amr.corp.intel.com ([10.241.98.166]) by orsmga003.jf.intel.com with ESMTP; 16 Aug 2017 19:35:33 -0700 From: Michael D Kinney To: edk2-devel@lists.01.org Cc: Eric Dong , Michael Kinney Date: Wed, 16 Aug 2017 19:35:32 -0700 Message-Id: <20170817023532.5380-1-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.13.1.windows.2 Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Aug 2017 02:33:08 -0000 https://bugzilla.tianocore.org/show_bug.cgi?id=674 Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs. Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 6b66c49085..f086b97c30 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES mSmmCpuSemaphores; UINTN mSemaphoreSize; SPIN_LOCK *mPFLock = NULL; SMM_CPU_SYNC_MODE mCpuSmmSyncMode; +BOOLEAN mMachineCheckSupported = FALSE; /** Performs an atomic compare exchange operation to get semaphore. @@ -264,8 +265,12 @@ SmmWaitForApArrival ( ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus); - LmceEn = IsLmceOsEnabled (); - LmceSignal = IsLmceSignaled(); + LmceEn = FALSE; + LmceSignal = FALSE; + if (mMachineCheckSupported) { + LmceEn = IsLmceOsEnabled (); + LmceSignal = IsLmceSignaled(); + } // // Platform implementor should choose a timeout value appropriately: @@ -1366,6 +1371,13 @@ InitializeMpServiceData ( UINTN Index; UINT8 *GdtTssTables; UINTN GdtTableStepSize; + CPUID_VERSION_INFO_EDX RegEdx; + + // + // Determine if this CPU supports machine check + // + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32); + mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1); // // Allocate memory for all locks and semaphores -- 2.13.1.windows.2