[Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check

[Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check

[Michael D Kinney]

https://bugzilla.tianocore.org/show_bug.cgi?id=674

Add CPUID check to see if the CPU supports the Machine
Check Architecture before accessing the Machine Check
Architecture related MSRs.

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 6b66c49085..f086b97c30 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES                          mSmmCpuSemaphores;
 UINTN                                       mSemaphoreSize;
 SPIN_LOCK                                   *mPFLock = NULL;
 SMM_CPU_SYNC_MODE                           mCpuSmmSyncMode;
+BOOLEAN                                     mMachineCheckSupported = FALSE;
 
 /**
   Performs an atomic compare exchange operation to get semaphore.
@@ -264,8 +265,12 @@ SmmWaitForApArrival (
 
   ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
 
-  LmceEn = IsLmceOsEnabled ();
-  LmceSignal = IsLmceSignaled();
+  LmceEn     = FALSE;
+  LmceSignal = FALSE;
+  if (mMachineCheckSupported) {
+    LmceEn     = IsLmceOsEnabled ();
+    LmceSignal = IsLmceSignaled();
+  }
 
   //
   // Platform implementor should choose a timeout value appropriately:
@@ -1366,6 +1371,13 @@ InitializeMpServiceData (
   UINTN                     Index;
   UINT8                     *GdtTssTables;
   UINTN                     GdtTableStepSize;
+  CPUID_VERSION_INFO_EDX    RegEdx;
+
+  //
+  // Determine if this CPU supports machine check
+  //
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
+  mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1);
 
   //
   // Allocate memory for all locks and semaphores
-- 
2.13.1.windows.2

Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check

[Dong, Eric]

Reviewed-by: Eric Dong <eric.dong@intel.com>

-----Original Message-----
From: Kinney, Michael D 
Sent: Thursday, August 17, 2017 10:36 AM
To: edk2-devel@lists.01.org
Cc: Dong, Eric <eric.dong@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check

https://bugzilla.tianocore.org/show_bug.cgi?id=674

Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs.

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 6b66c49085..f086b97c30 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES                          mSmmCpuSemaphores;
 UINTN                                       mSemaphoreSize;
 SPIN_LOCK                                   *mPFLock = NULL;
 SMM_CPU_SYNC_MODE                           mCpuSmmSyncMode;
+BOOLEAN                                     mMachineCheckSupported = FALSE;
 
 /**
   Performs an atomic compare exchange operation to get semaphore.
@@ -264,8 +265,12 @@ SmmWaitForApArrival (
 
   ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
 
-  LmceEn = IsLmceOsEnabled ();
-  LmceSignal = IsLmceSignaled();
+  LmceEn     = FALSE;
+  LmceSignal = FALSE;
+  if (mMachineCheckSupported) {
+    LmceEn     = IsLmceOsEnabled ();
+    LmceSignal = IsLmceSignaled();
+  }
 
   //
   // Platform implementor should choose a timeout value appropriately:
@@ -1366,6 +1371,13 @@ InitializeMpServiceData (
   UINTN                     Index;
   UINT8                     *GdtTssTables;
   UINTN                     GdtTableStepSize;
+  CPUID_VERSION_INFO_EDX    RegEdx;
+
+  //
+  // Determine if this CPU supports machine check  //  AsmCpuid 
+ (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);  
+ mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1);
 
   //
   // Allocate memory for all locks and semaphores
--
2.13.1.windows.2