From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DB0A321D2E649 for ; Sun, 20 Aug 2017 12:31:16 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 3F6FB20A80; Sun, 20 Aug 2017 15:33:47 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute1.internal (MEProxy); Sun, 20 Aug 2017 15:33:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=6UAKEk04NQ4PplQH61k9S/UofZ/nV44m/3uxRfGmL Ko=; b=mqaZwXqbElLNIyDLJf5mSfmNy0eiDUv6tDi/KFVdkwJw+d88eQuFKEcF0 OukuuTlMToUVVBFSS1nsGGn9tDy5QsJWefNsfbuNwuO5lp4ALFQXnQIPbvnudFpI X9NkxTpMuyV1DOds2BtSagju1a0oMhuJCDTKMPvynuWToGDbxzQagZFfYNimeTm9 HCEKGYch4EXRhcRhmBsmuUJqZrkH+TUMssgoC5IFmeYBvoQWCfnrTqukMMq/cfmu Fll+i/itT+p2l9hFY8ryNnlQUCAIvdWzvwf0Op6Eh99S0JyWDUk7C5GOMHbrOO9s fNJUZV3t405mdDomZuQqpvvW/UWYw== X-ME-Sender: X-Sasl-enc: LqwcojAlY0KOKBMrhgqXlsG1rXtScy6rUu/HY+I7b01p 1503257626 Received: from localhost.localdomain (c-71-226-23-158.hsd1.fl.comcast.net [71.226.23.158]) by mail.messagingengine.com (Postfix) with ESMTPA id AA38C24775; Sun, 20 Aug 2017 15:33:46 -0400 (EDT) From: Alan Ott To: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org Cc: edk2-devel@lists.01.org, linaro-uefi@lists.linaro.org, Alan Ott Date: Sun, 20 Aug 2017 15:33:34 -0400 Message-Id: <20170820193335.21471-3-alan@softiron.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170820193335.21471-1-alan@softiron.com> References: <20170820193335.21471-1-alan@softiron.com> Subject: [PATCH v2 edk2-platforms 2/3] Silicon/AMD/Styx: Use PcdSataPortMode properly for two controllers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 Aug 2017 19:31:17 -0000 The previous implementation used only the lower bits for both the first and second SATA controller, when the upper bits should have been used for the second SATA controller. Also ASSERT that SataChPerSerdes is 2, because the even/odd logic doesn't work if it's not. Signed-off-by: Alan Ott Contributed-under: TianoCore Contribution Agreement 1.0 --- Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c index 78c6819..ea49cae 100644 --- a/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c +++ b/Silicon/AMD/Styx/Drivers/StyxSataPlatformDxe/InitController.c @@ -109,10 +109,15 @@ InitializeSataController ( SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes); - for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) { + // + // SataChPerSerdes must be 2 for the Even/Odd logic in the loop below + // + ASSERT(SataChPerSerdes == 2); + + for (PortNum = StartPort; PortNum < SataPortCount + StartPort; PortNum += SataChPerSerdes) { EvenPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> (PortNum * 2)) & 3; OddPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3; - SataPhyInit ((StartPort + PortNum) / SataChPerSerdes, EvenPort, OddPort); + SataPhyInit (PortNum / SataChPerSerdes, EvenPort, OddPort); } // -- 2.9.3