* [PATCH v2 0/5] Add multiple PCI segments configuration access support
@ 2017-08-25 8:57 Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 1/5] MdePkg/PciSegmentLib: Fix typo in function header comments Ruiyu Ni
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel
v2: Add missing function header and file header. Correct all incorrect file headers.
Ruiyu Ni (5):
MdePkg/PciSegmentLib: Fix typo in function header comments
MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS
MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance.
MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance.
MdePkg/Include/IndustryStandard/PciExpress21.h | 19 +-
MdePkg/Include/Library/PciExpressLib.h | 5 +-
MdePkg/Include/Library/PciSegmentInfoLib.h | 41 ++
MdePkg/Include/Library/PciSegmentLib.h | 102 ++--
.../Library/{PciSegmentLib.h => S3PciSegmentLib.h} | 364 ++++++-----
.../BasePciSegmentInfoLibNull.inf | 41 ++
.../BasePciSegmentInfoLibNull.uni | 20 +
.../BasePciSegmentInfoLibNull/PciSegmentInfoLib.c | 38 ++
.../Library/BasePciSegmentLibPci/PciSegmentLib.c | 136 +++--
.../BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf | 45 ++
.../BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni | 23 +
.../BaseS3PciSegmentLib/S3PciSegmentLib.c} | 674 ++++++++++++++-------
.../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +++
.../BasePciSegmentLibSegmentInfo.inf | 46 ++
.../BasePciSegmentLibSegmentInfo.uni | 21 +
.../DxeRuntimePciSegmentLib.c | 321 ++++++++++
.../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 ++
.../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
.../PciSegmentLibCommon.c} | 656 +++++++++++++++-----
.../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 ++
.../PeiPciSegmentLibPciCfg2/PciSegmentLib.c | 187 +++---
.../PciSegmentLib.c | 180 +++---
MdePkg/MdePkg.dec | 8 +
MdePkg/MdePkg.dsc | 4 +
24 files changed, 2250 insertions(+), 885 deletions(-)
create mode 100644 MdePkg/Include/Library/PciSegmentInfoLib.h
copy MdePkg/Include/Library/{PciSegmentLib.h => S3PciSegmentLib.h} (80%)
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c
create mode 100644 MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
create mode 100644 MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni
copy MdePkg/{Include/Library/PciSegmentLib.h => Library/BaseS3PciSegmentLib/S3PciSegmentLib.c} (66%)
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
copy MdePkg/{Include/Library/PciSegmentLib.h => Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c} (69%)
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
--
2.12.2.windows.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/5] MdePkg/PciSegmentLib: Fix typo in function header comments
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
@ 2017-08-25 8:57 ` Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 2/5] MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS Ruiyu Ni
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel; +Cc: Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/Library/PciSegmentLib.h | 102 +++++------
.../Library/BasePciSegmentLibPci/PciSegmentLib.c | 136 +++++++--------
.../PeiPciSegmentLibPciCfg2/PciSegmentLib.c | 187 ++++++++++-----------
.../PciSegmentLib.c | 180 ++++++++++----------
4 files changed, 308 insertions(+), 297 deletions(-)
diff --git a/MdePkg/Include/Library/PciSegmentLib.h b/MdePkg/Include/Library/PciSegmentLib.h
index 5175e07606..6e4fecb0b1 100644
--- a/MdePkg/Include/Library/PciSegmentLib.h
+++ b/MdePkg/Include/Library/PciSegmentLib.h
@@ -23,7 +23,7 @@
access method. Modules will typically use the PCI Segment Library for its PCI configuration
accesses when PCI Segments other than Segment #0 must be accessed.
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -99,9 +99,9 @@ PciSegmentRegisterForRuntimeAccess (
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
-
+
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 8-bit PCI configuration register specified by Address.
@@ -118,7 +118,7 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@@ -142,7 +142,7 @@ PciSegmentWrite8 (
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@@ -184,18 +184,18 @@ PciSegmentAnd8 (
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
followed a bitwise OR with another 8-bit value.
-
+
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -345,8 +345,7 @@ PciSegmentBitFieldAnd8 (
/**
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
@@ -389,10 +388,10 @@ PciSegmentBitFieldAndThenOr8 (
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
+
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 16-bit PCI configuration register specified by Address.
@@ -409,7 +408,7 @@ PciSegmentRead16 (
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -431,11 +430,10 @@ PciSegmentWrite16 (
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -462,10 +460,10 @@ PciSegmentOr16 (
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
+
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@@ -482,19 +480,19 @@ PciSegmentAnd16 (
/**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
followed a bitwise OR with another 16-bit value.
-
+
Reads the 16-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -573,9 +571,15 @@ PciSegmentBitFieldWrite16 (
);
/**
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -604,31 +608,31 @@ PciSegmentBitFieldOr16 (
);
/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
- and writes the result back to the bit field in the 16-bit port.
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
- The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are serialized.
- Extra left bits in OrData are stripped.
-
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
- The ordinal of the least significant bit in a byte is bit 0.
+ Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
- The ordinal of the most significant bit in a byte is bit 7.
- @param AndData The value to AND with the read value from the PCI configuration register.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
- @return The value written to the PCI configuration register.
+ @return The value written back to the PCI configuration register.
**/
UINT16
@@ -686,7 +690,7 @@ PciSegmentBitFieldAndThenOr16 (
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@@ -706,7 +710,7 @@ PciSegmentRead32 (
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@@ -731,7 +735,7 @@ PciSegmentWrite32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@@ -756,7 +760,7 @@ PciSegmentOr32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@@ -776,14 +780,14 @@ PciSegmentAnd32 (
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
followed a bitwise OR with another 32-bit value.
-
+
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@@ -906,7 +910,7 @@ PciSegmentBitFieldOr32 (
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 32-bit register.
-
+
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
AND between the read result and the value specified by AndData, and writes the result
to the 32-bit PCI configuration register specified by Address. The value written to
@@ -919,7 +923,7 @@ PciSegmentBitFieldOr32 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address PCI configuration register to write.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
diff --git a/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c b/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
index dc2745bf3a..8396c44ed7 100644
--- a/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
+++ b/MdePkg/Library/BasePciSegmentLibPci/PciSegmentLib.c
@@ -2,7 +2,7 @@
PCI Segment Library that layers on top of the PCI Library which only
supports segment 0 PCI configuration access.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -75,7 +75,7 @@ PciSegmentRegisterForRuntimeAccess (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 8-bit PCI configuration register specified by Address.
@@ -99,7 +99,7 @@ PciSegmentRead8 (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
@@ -128,7 +128,7 @@ PciSegmentWrite8 (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -154,7 +154,7 @@ PciSegmentOr8 (
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -183,8 +183,8 @@ PciSegmentAnd8 (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -213,7 +213,7 @@ PciSegmentAndThenOr8 (
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -247,12 +247,12 @@ PciSegmentBitFieldRead8 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -289,7 +289,7 @@ PciSegmentBitFieldWrite8 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -331,7 +331,7 @@ PciSegmentBitFieldOr8 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -358,8 +358,7 @@ PciSegmentBitFieldAnd8 (
/**
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
@@ -376,7 +375,7 @@ PciSegmentBitFieldAnd8 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -412,7 +411,7 @@ PciSegmentBitFieldAndThenOr8 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 16-bit PCI configuration register specified by Address.
@@ -437,7 +436,7 @@ PciSegmentRead16 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -460,16 +459,15 @@ PciSegmentWrite16 (
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function and
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@@ -498,7 +496,7 @@ PciSegmentOr16 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -528,8 +526,8 @@ PciSegmentAnd16 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -559,7 +557,7 @@ PciSegmentAndThenOr16 (
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -594,12 +592,12 @@ PciSegmentBitFieldRead16 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -620,9 +618,15 @@ PciSegmentBitFieldWrite16 (
}
/**
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -631,7 +635,7 @@ PciSegmentBitFieldWrite16 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -657,31 +661,31 @@ PciSegmentBitFieldOr16 (
}
/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
- and writes the result back to the bit field in the 16-bit port.
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
- The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are serialized.
- Extra left bits in OrData are stripped.
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
- The ordinal of the least significant bit in a byte is bit 0.
+ Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
- The ordinal of the most significant bit in a byte is bit 7.
- @param AndData The value to AND with the read value from the PCI configuration register.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
- @return The value written to the PCI configuration register.
+ @return The value written back to the PCI configuration register.
**/
UINT16
@@ -719,7 +723,7 @@ PciSegmentBitFieldAnd16 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -755,7 +759,7 @@ PciSegmentBitFieldAndThenOr16 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 32-bit PCI configuration register specified by Address.
@@ -780,7 +784,7 @@ PciSegmentRead32 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -810,7 +814,7 @@ PciSegmentWrite32 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -838,7 +842,7 @@ PciSegmentOr32 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -868,7 +872,7 @@ PciSegmentAnd32 (
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@@ -899,7 +903,7 @@ PciSegmentAndThenOr32 (
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -934,12 +938,12 @@ PciSegmentBitFieldRead32 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -976,7 +980,7 @@ PciSegmentBitFieldWrite32 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1018,7 +1022,7 @@ PciSegmentBitFieldOr32 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1063,7 +1067,7 @@ PciSegmentBitFieldAnd32 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1105,10 +1109,10 @@ PciSegmentBitFieldAndThenOr32 (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer receiving the data read.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
@return Size
@@ -1203,10 +1207,10 @@ PciSegmentReadBuffer (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer containing the data to write.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
@return The parameter of Size.
diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
index 93f63df389..8af168d7f9 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PciSegmentLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Segment Library implementation using PCI CFG2 PPI.
- Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -168,7 +168,7 @@ PeiPciSegmentLibPciCfg2WriteWorker (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Bus, Device, Function and
+ @param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@@ -195,11 +195,10 @@ PciSegmentRegisterForRuntimeAccess (
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function,
- and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 8-bit PCI configuration register specified by Address.
@@ -220,10 +219,10 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
@@ -249,10 +248,10 @@ PciSegmentWrite8 (
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -278,7 +277,7 @@ PciSegmentOr8 (
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -297,18 +296,18 @@ PciSegmentAnd8 (
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
followed a bitwise OR with another 8-bit value.
-
+
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -337,7 +336,7 @@ PciSegmentAndThenOr8 (
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -371,12 +370,12 @@ PciSegmentBitFieldRead8 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -413,7 +412,7 @@ PciSegmentBitFieldWrite8 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -455,7 +454,7 @@ PciSegmentBitFieldOr8 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -482,8 +481,7 @@ PciSegmentBitFieldAnd8 (
/**
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
@@ -500,7 +498,7 @@ PciSegmentBitFieldAnd8 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -532,11 +530,11 @@ PciSegmentBitFieldAndThenOr8 (
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 16-bit PCI configuration register specified by Address.
@@ -557,11 +555,11 @@ PciSegmentRead16 (
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -584,16 +582,15 @@ PciSegmentWrite16 (
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function and
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@@ -618,11 +615,11 @@ PciSegmentOr16 (
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -641,18 +638,18 @@ PciSegmentAnd16 (
/**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
followed a bitwise OR with another 16-bit value.
-
+
Reads the 16-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@@ -683,7 +680,7 @@ PciSegmentAndThenOr16 (
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -718,12 +715,12 @@ PciSegmentBitFieldRead16 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -744,9 +741,15 @@ PciSegmentBitFieldWrite16 (
}
/**
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -755,7 +758,7 @@ PciSegmentBitFieldWrite16 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -781,31 +784,31 @@ PciSegmentBitFieldOr16 (
}
/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
- and writes the result back to the bit field in the 16-bit port.
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
- The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are serialized.
- Extra left bits in OrData are stripped.
-
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
- The ordinal of the least significant bit in a byte is bit 0.
+ Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
- The ordinal of the most significant bit in a byte is bit 7.
- @param AndData The value to AND with the read value from the PCI configuration register.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
- @return The value written to the PCI configuration register.
+ @return The value written back to the PCI configuration register.
**/
UINT16
@@ -843,7 +846,7 @@ PciSegmentBitFieldAnd16 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -875,12 +878,11 @@ PciSegmentBitFieldAndThenOr16 (
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function,
- and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 32-bit PCI configuration register specified by Address.
@@ -901,12 +903,11 @@ PciSegmentRead32 (
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device,
- Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -932,11 +933,11 @@ PciSegmentWrite32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -960,12 +961,11 @@ PciSegmentOr32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function,
- and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -984,19 +984,18 @@ PciSegmentAnd32 (
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
followed a bitwise OR with another 32-bit value.
-
+
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function,
- and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@@ -1027,7 +1026,7 @@ PciSegmentAndThenOr32 (
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1062,12 +1061,12 @@ PciSegmentBitFieldRead32 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -1104,7 +1103,7 @@ PciSegmentBitFieldWrite32 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1133,7 +1132,7 @@ PciSegmentBitFieldOr32 (
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 32-bit register.
-
+
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
AND between the read result and the value specified by AndData, and writes the result
to the 32-bit PCI configuration register specified by Address. The value written to
@@ -1146,7 +1145,7 @@ PciSegmentBitFieldOr32 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1191,7 +1190,7 @@ PciSegmentBitFieldAnd32 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1233,10 +1232,10 @@ PciSegmentBitFieldAndThenOr32 (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus,
- Device, Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer receiving the data read.
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
@return Size
@@ -1332,10 +1331,10 @@ PciSegmentReadBuffer (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus,
- Device, Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer containing the data to write.
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
@return The parameter of Size.
diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index 5b286b057f..7e57ec21f9 100644
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Segment Library implementation using PCI Root Bridge I/O Protocol.
- Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -246,7 +246,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker (
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Bus, Device, Function and
+ @param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@@ -273,10 +273,10 @@ PciSegmentRegisterForRuntimeAccess (
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 8-bit PCI configuration register specified by Address.
@@ -297,10 +297,10 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
@@ -326,10 +326,10 @@ PciSegmentWrite8 (
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -355,7 +355,7 @@ PciSegmentOr8 (
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -374,18 +374,18 @@ PciSegmentAnd8 (
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
followed a bitwise OR with another 8-bit value.
-
+
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -414,7 +414,7 @@ PciSegmentAndThenOr8 (
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -448,12 +448,12 @@ PciSegmentBitFieldRead8 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -490,7 +490,7 @@ PciSegmentBitFieldWrite8 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -532,7 +532,7 @@ PciSegmentBitFieldOr8 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -559,8 +559,7 @@ PciSegmentBitFieldAnd8 (
/**
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
@@ -577,7 +576,7 @@ PciSegmentBitFieldAnd8 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -609,11 +608,11 @@ PciSegmentBitFieldAndThenOr8 (
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 16-bit PCI configuration register specified by Address.
@@ -634,11 +633,11 @@ PciSegmentRead16 (
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -661,16 +660,15 @@ PciSegmentWrite16 (
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function and
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@@ -695,11 +693,11 @@ PciSegmentOr16 (
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -718,19 +716,19 @@ PciSegmentAnd16 (
/**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
followed a bitwise OR with another 16-bit value.
-
+
Reads the 16-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
- @param AndData The value to AND with the PCI configuration register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -760,7 +758,7 @@ PciSegmentAndThenOr16 (
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -795,12 +793,12 @@ PciSegmentBitFieldRead16 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -821,9 +819,15 @@ PciSegmentBitFieldWrite16 (
}
/**
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -832,7 +836,7 @@ PciSegmentBitFieldWrite16 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -858,31 +862,31 @@ PciSegmentBitFieldOr16 (
}
/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
- and writes the result back to the bit field in the 16-bit port.
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
- Reads the 16-bit PCI configuration register specified by Address,
- performs a bitwise OR between the read result and the value specified by OrData,
- and writes the result to the 16-bit PCI configuration register specified by Address.
- The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are serialized.
- Extra left bits in OrData are stripped.
-
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
- The ordinal of the least significant bit in a byte is bit 0.
+ Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
- The ordinal of the most significant bit in a byte is bit 7.
- @param AndData The value to AND with the read value from the PCI configuration register.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
- @return The value written to the PCI configuration register.
+ @return The value written back to the PCI configuration register.
**/
UINT16
@@ -920,7 +924,7 @@ PciSegmentBitFieldAnd16 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -952,11 +956,11 @@ PciSegmentBitFieldAndThenOr16 (
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 32-bit PCI configuration register specified by Address.
@@ -977,11 +981,11 @@ PciSegmentRead32 (
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
@@ -1007,11 +1011,11 @@ PciSegmentWrite32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -1035,11 +1039,11 @@ PciSegmentOr32 (
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
@@ -1058,18 +1062,18 @@ PciSegmentAnd32 (
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
followed a bitwise OR with another 32-bit value.
-
+
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
-
+
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
- @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@@ -1100,7 +1104,7 @@ PciSegmentAndThenOr32 (
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
- @param Address The PCI configuration register to read.
+ @param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1135,12 +1139,12 @@ PciSegmentBitFieldRead32 (
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
- @param Value The new value of the bit field.
+ @param Value New value of the bit field.
@return The value written back to the PCI configuration register.
@@ -1177,7 +1181,7 @@ PciSegmentBitFieldWrite32 (
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1206,7 +1210,7 @@ PciSegmentBitFieldOr32 (
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 32-bit register.
-
+
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
AND between the read result and the value specified by AndData, and writes the result
to the 32-bit PCI configuration register specified by Address. The value written to
@@ -1219,7 +1223,7 @@ PciSegmentBitFieldOr32 (
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1264,7 +1268,7 @@ PciSegmentBitFieldAnd32 (
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- @param Address The PCI configuration register to write.
+ @param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
@@ -1306,10 +1310,10 @@ PciSegmentBitFieldAndThenOr32 (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer receiving the data read.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
@return Size
@@ -1404,10 +1408,10 @@ PciSegmentReadBuffer (
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
- @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer containing the data to write.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
@return The parameter of Size.
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/5] MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 1/5] MdePkg/PciSegmentLib: Fix typo in function header comments Ruiyu Ni
@ 2017-08-25 8:57 ` Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 3/5] MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance Ruiyu Ni
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel; +Cc: Liming Gao
The patch adds new macro PCI_ECAM_ADDRESS into PciExpress21.h,
to align to the PCIE spec, and also update PciExpressLib.h to
redirect PCI_EXPRESS_LIB_ADDRESS to the new macro.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 19 ++++++++++++++++++-
MdePkg/Include/Library/PciExpressLib.h | 5 ++---
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index 175c82c88e..ce9c06a7c6 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -18,6 +18,23 @@
#include <IndustryStandard/Pci30.h>
+/**
+ Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+ ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+ of Bus, Device, Function and Register are stripped prior to the generation of
+ the address.
+
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..4095.
+
+ @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+ (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
#pragma pack(1)
///
/// PCI Express Capability Structure
diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h
index e312d57528..f65b44384f 100644
--- a/MdePkg/Include/Library/PciExpressLib.h
+++ b/MdePkg/Include/Library/PciExpressLib.h
@@ -5,7 +5,7 @@
configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
is defined by PcdPciExpressBaseAddress.
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -35,8 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@return The encode PCI address.
**/
-#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
- (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
/**
Registers a PCI device so PCI configuration registers may be accessed after
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/5] MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance.
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 1/5] MdePkg/PciSegmentLib: Fix typo in function header comments Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 2/5] MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS Ruiyu Ni
@ 2017-08-25 8:57 ` Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib Ruiyu Ni
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel; +Cc: Liming Gao
The patch adds PciSegmentInfoLib library class which is used
by PciSegmentLib (commit in next patch) to support multiple
segment PCI configuration access.
BasePciSegmentInfoLibNull instance is added but it shouldn't be
used by any real platform.
Any single segment platform that wants to use PciSegmentLib could
use BasePciSegmentLibPci instance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/Library/PciSegmentInfoLib.h | 41 ++++++++++++++++++++++
.../BasePciSegmentInfoLibNull.inf | 41 ++++++++++++++++++++++
.../BasePciSegmentInfoLibNull.uni | 20 +++++++++++
.../BasePciSegmentInfoLibNull/PciSegmentInfoLib.c | 38 ++++++++++++++++++++
MdePkg/MdePkg.dec | 3 ++
MdePkg/MdePkg.dsc | 1 +
6 files changed, 144 insertions(+)
create mode 100644 MdePkg/Include/Library/PciSegmentInfoLib.h
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni
create mode 100644 MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c
diff --git a/MdePkg/Include/Library/PciSegmentInfoLib.h b/MdePkg/Include/Library/PciSegmentInfoLib.h
new file mode 100644
index 0000000000..588269a9ae
--- /dev/null
+++ b/MdePkg/Include/Library/PciSegmentInfoLib.h
@@ -0,0 +1,41 @@
+/** @file
+ Provides services to return segment information on a platform with multiple PCI segments.
+
+ This library is consumed by PciSegmentLib to support multiple segment PCI configuration access.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PCI_SEGMENT_INFO_LIB__
+#define __PCI_SEGMENT_INFO_LIB__
+
+typedef struct {
+ UINT16 SegmentNumber; ///< Segment number.
+ UINT64 BaseAddress; ///< ECAM Base address.
+ UINT8 StartBusNumber; ///< Start BUS number, for verifying the PCI Segment address.
+ UINT8 EndBusNumber; ///< End BUS number, for verifying the PCI Segment address.
+} PCI_SEGMENT_INFO;
+
+/**
+ Return an array of PCI_SEGMENT_INFO holding the segment information.
+
+ Note: The returned array/buffer is owned by callee.
+
+ @param Count Return the count of segments.
+
+ @retval A callee owned array holding the segment information.
+**/
+PCI_SEGMENT_INFO *
+GetPciSegmentInfo (
+ UINTN *Count
+ );
+
+#endif
diff --git a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
new file mode 100644
index 0000000000..5ae59fb2be
--- /dev/null
+++ b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
@@ -0,0 +1,41 @@
+## @file
+# Instance of PCI SegmentInfo Library.
+#
+# Default PCI Segment Information Library that shouldn't be used by real platform.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BasePciSegmentInfoLibNull
+ MODULE_UNI_FILE = BasePciSegmentInfoLibNull.uni
+ FILE_GUID = 36B28584-C6AE-4B1B-A473-A51618EE525A
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PciSegmentInfoLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
diff --git a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni
new file mode 100644
index 0000000000..a956787637
--- /dev/null
+++ b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni
@@ -0,0 +1,20 @@
+// /** @file
+// Instance of PCI SegmentInfo Library.
+//
+// Default PCI Segment Information Library that shouldn't be used by real platform.
+//
+// Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Default instance of PCI SegmentInfo Library."
+
+#string STR_MODULE_DESCRIPTION #language en-US "Default PCI Segment Information Library that shouldn't be used by real platform."
diff --git a/MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c b/MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c
new file mode 100644
index 0000000000..011a41450c
--- /dev/null
+++ b/MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Default PCI Segment Information Library that returns one segment whose
+ segment base address equals to PcdPciExpressBaseAddress.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentInfoLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Return an array of PCI_SEGMENT_INFO holding the segment information.
+
+ Note: The returned array/buffer is owned by callee.
+
+ @param Count Return the count of segments.
+
+ @retval A callee owned array holding the segment information.
+**/
+PCI_SEGMENT_INFO *
+GetPciSegmentInfo (
+ UINTN *Count
+ )
+{
+ ASSERT (FALSE);
+ *Count = 0;
+ return NULL;
+}
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 425004f9d8..ad13185ed6 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -131,6 +131,9 @@ [LibraryClasses]
## @libraryclass Provides a service to retrieve the PE/COFF entry point from a PE/COFF image.
PeCoffGetEntryPointLib|Include/Library/PeCoffGetEntryPointLib.h
+ ## @libraryclass Provides services to return the PCI segment information.
+ PciSegmentInfoLib|Include/Library/PciSegmentInfoLib.h
+
## @libraryclass Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
PciSegmentLib|Include/Library/PciSegmentLib.h
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 010ce533d7..e553a702a3 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -69,6 +69,7 @@ [Components]
MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
` (2 preceding siblings ...)
2017-08-25 8:57 ` [PATCH v2 3/5] MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance Ruiyu Ni
@ 2017-08-25 8:57 ` Ruiyu Ni
2017-08-29 18:51 ` Ard Biesheuvel
2017-08-25 8:57 ` [PATCH v2 5/5] MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance Ruiyu Ni
2017-08-28 7:39 ` [PATCH v2 0/5] Add multiple PCI segments configuration access support Gao, Liming
5 siblings, 1 reply; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel; +Cc: Liming Gao
The patch adds two PciSegmentLib instances that consumes
PciSegmentInfoLib to provide multiple segments PCI configuration
access.
BasePciSegmentLibSegmentInfo instance is a BASE library.
DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with
runtime drivers to provide not only boot time but also runtime
PCI configuration access.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
.../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +
.../BasePciSegmentLibSegmentInfo.inf | 46 +
.../BasePciSegmentLibSegmentInfo.uni | 21 +
.../DxeRuntimePciSegmentLib.c | 321 +++++
.../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 +
.../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
.../PciSegmentLibSegmentInfo/PciSegmentLibCommon.c | 1375 ++++++++++++++++++++
.../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 +
MdePkg/MdePkg.dsc | 2 +
9 files changed, 1969 insertions(+)
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
new file mode 100644
index 0000000000..e71624d4ba
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
@@ -0,0 +1,71 @@
+/** @file
+ Instance of Base PCI Segment Library that support multi-segment PCI configuration access.
+
+ PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+ support multi-segment PCI configuration access through enhanced configuration access mechanism.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciSegmentLibCommon.h"
+
+/**
+ Return the virtual address for the physical address.
+
+ @param Address The physical address.
+
+ @retval The virtual address.
+**/
+UINTN
+PciSegmentLibVirtualAddress (
+ IN UINTN Address
+ )
+{
+ return Address;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ //
+ // Use PciSegmentLibGetEcamAddress() to validate the Address.
+ //
+ DEBUG_CODE (
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count);
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
new file mode 100644
index 0000000000..9cd60764dc
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
@@ -0,0 +1,46 @@
+## @file
+# Instance of Base PCI Segment Library that support multi-segment PCI configuration access.
+#
+# PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+# support multi-segment PCI configuration access through enhanced configuration access mechanism.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BasePciSegmentLibSegmentInfo
+ MODULE_UNI_FILE = BasePciSegmentLibSegmentInfo.uni
+ FILE_GUID = 3427D883-E093-4CC9-BE85-6BD4058E96E2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PciSegmentLibCommon.h
+ PciSegmentLibCommon.c
+ BasePciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentInfoLib
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
new file mode 100644
index 0000000000..ad33a5fdad
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
@@ -0,0 +1,21 @@
+// /** @file
+// Instance of Base PCI Segment Library that support multi-segment PCI configuration access.
+
+// PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+// support multi-segment PCI configuration access through enhanced configuration access mechanism.
+//
+// Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of Base PCI Segment Library that support multi-segment PCI configuration access."
+
+#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to support multi-segment PCI configuration access through enhanced configuration access mechanism."
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
new file mode 100644
index 0000000000..9c86608677
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
@@ -0,0 +1,321 @@
+/** @file
+ Instance of Runtime PCI Segment Library that support multi-segment PCI configuration access.
+
+ PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+ support multi-segment PCI configuration access through enhanced configuration access mechanism.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciSegmentLibCommon.h"
+#include <PiDxe.h>
+#include <Guid/EventGroup.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciSegmentInfoLib.h>
+
+///
+/// Define table for mapping PCI Segment MMIO physical addresses to virtual addresses at OS runtime
+///
+typedef struct {
+ UINTN PhysicalAddress;
+ UINTN VirtualAddress;
+} PCI_SEGMENT_RUNTIME_REGISTRATION_TABLE;
+
+///
+/// Set Virtual Address Map Event
+///
+EFI_EVENT mDxeRuntimePciSegmentLibVirtualNotifyEvent = NULL;
+
+///
+/// The number of PCI devices that have been registered for runtime access.
+///
+UINTN mDxeRuntimePciSegmentLibNumberOfRuntimeRanges = 0;
+
+///
+/// The table of PCI devices that have been registered for runtime access.
+///
+PCI_SEGMENT_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciSegmentLibRegistrationTable = NULL;
+
+///
+/// The table index of the most recent virtual address lookup.
+///
+UINTN mDxeRuntimePciSegmentLibLastRuntimeRange = 0;
+
+/**
+ Convert the physical PCI Express MMIO addresses for all registered PCI devices
+ to virtual addresses.
+
+ @param[in] Event The event that is being processed.
+ @param[in] Context The Event Context.
+**/
+VOID
+EFIAPI
+DxeRuntimePciSegmentLibVirtualNotify (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+ EFI_STATUS Status;
+
+ //
+ // If there have been no runtime registrations, then just return
+ //
+ if (mDxeRuntimePciSegmentLibRegistrationTable == NULL) {
+ return;
+ }
+
+ //
+ // Convert physical addresses associated with the set of registered PCI devices to
+ // virtual addresses.
+ //
+ for (Index = 0; Index < mDxeRuntimePciSegmentLibNumberOfRuntimeRanges; Index++) {
+ Status = EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciSegmentLibRegistrationTable[Index].VirtualAddress));
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ //
+ // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.
+ //
+ Status = EfiConvertPointer (0, (VOID **) &mDxeRuntimePciSegmentLibRegistrationTable);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ The constructor function caches the PCI Express Base Address and creates a
+ Set Virtual Address Map event to convert physical address to virtual addresses.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor completed successfully.
+ @retval Other value The constructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+DxeRuntimePciSegmentLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Register SetVirtualAddressMap () notify function
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ DxeRuntimePciSegmentLibVirtualNotify,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mDxeRuntimePciSegmentLibVirtualNotifyEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ The destructor function frees any allocated buffers and closes the Set Virtual
+ Address Map event.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The destructor completed successfully.
+ @retval Other value The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+DxeRuntimePciSegmentLibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // If one or more PCI devices have been registered for runtime access, then
+ // free the registration table.
+ //
+ if (mDxeRuntimePciSegmentLibRegistrationTable != NULL) {
+ FreePool (mDxeRuntimePciSegmentLibRegistrationTable);
+ }
+
+ //
+ // Close the Set Virtual Address Map event
+ //
+ Status = gBS->CloseEvent (mDxeRuntimePciSegmentLibVirtualNotifyEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ RETURN_STATUS Status;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+ UINTN Index;
+ VOID *NewTable;
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+ UINT64 EcamAddress;
+
+ //
+ // Convert Address to a ECAM address at the beginning of the PCI Configuration
+ // header for the specified PCI Bus/Dev/Func
+ //
+ Address &= ~(UINTN)EFI_PAGE_MASK;
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ EcamAddress = PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count);
+
+ //
+ // Return an error if this function is called after ExitBootServices().
+ //
+ if (EfiAtRuntime ()) {
+ return RETURN_UNSUPPORTED;
+ }
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+ ASSERT (EcamAddress < BASE_4GB);
+ }
+ Address = (UINTN)EcamAddress;
+
+ //
+ // See if Address has already been registerd for runtime access
+ //
+ for (Index = 0; Index < mDxeRuntimePciSegmentLibNumberOfRuntimeRanges; Index++) {
+ if (mDxeRuntimePciSegmentLibRegistrationTable[Index].PhysicalAddress == Address) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ //
+ // Get the GCD Memory Descriptor for the ECAM Address
+ //
+ Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);
+ if (EFI_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS
+ // will allocate a virtual address range for the 4KB PCI Configuration Header.
+ //
+ Status = gDS->SetMemorySpaceAttributes (Address, EFI_PAGE_SIZE, Descriptor.Attributes | EFI_MEMORY_RUNTIME);
+ if (EFI_ERROR (Status)) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Grow the size of the registration table
+ //
+ NewTable = ReallocateRuntimePool (
+ (mDxeRuntimePciSegmentLibNumberOfRuntimeRanges + 0) * sizeof (PCI_SEGMENT_RUNTIME_REGISTRATION_TABLE),
+ (mDxeRuntimePciSegmentLibNumberOfRuntimeRanges + 1) * sizeof (PCI_SEGMENT_RUNTIME_REGISTRATION_TABLE),
+ mDxeRuntimePciSegmentLibRegistrationTable
+ );
+ if (NewTable == NULL) {
+ return RETURN_OUT_OF_RESOURCES;
+ }
+ mDxeRuntimePciSegmentLibRegistrationTable = NewTable;
+ mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibNumberOfRuntimeRanges].PhysicalAddress = Address;
+ mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibNumberOfRuntimeRanges].VirtualAddress = Address;
+ mDxeRuntimePciSegmentLibNumberOfRuntimeRanges++;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Return the linear address for the physical address.
+
+ @param Address The physical address.
+
+ @retval The linear address.
+**/
+UINTN
+PciSegmentLibVirtualAddress (
+ IN UINTN Address
+ )
+{
+ UINTN Index;
+ //
+ // If SetVirtualAddressMap() has not been called, then just return the physical address
+ //
+ if (!EfiGoneVirtual ()) {
+ return Address;
+ }
+
+ //
+ // See if there is a physical address match at the exact same index as the last address match
+ //
+ if (mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibLastRuntimeRange].PhysicalAddress == (Address & (~(UINTN)EFI_PAGE_MASK))) {
+ //
+ // Convert the physical address to a virtual address and return the virtual address
+ //
+ return (Address & EFI_PAGE_MASK) + mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibLastRuntimeRange].VirtualAddress;
+ }
+
+ //
+ // Search the entire table for a physical address match
+ //
+ for (Index = 0; Index < mDxeRuntimePciSegmentLibNumberOfRuntimeRanges; Index++) {
+ if (mDxeRuntimePciSegmentLibRegistrationTable[Index].PhysicalAddress == (Address & (~(UINTN)EFI_PAGE_MASK))) {
+ //
+ // Cache the matching index value
+ //
+ mDxeRuntimePciSegmentLibLastRuntimeRange = Index;
+ //
+ // Convert the physical address to a virtual address and return the virtual address
+ //
+ return (Address & EFI_PAGE_MASK) + mDxeRuntimePciSegmentLibRegistrationTable[Index].VirtualAddress;
+ }
+ }
+
+ //
+ // No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
+ //
+ ASSERT (FALSE);
+ CpuBreakpoint ();
+
+ //
+ // Return the physical address
+ //
+ return Address;
+}
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
new file mode 100644
index 0000000000..e484af5b06
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
@@ -0,0 +1,55 @@
+## @file
+# Instance of Runtime PCI Segment Library that support multi-segment PCI configuration access.
+#
+# PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+# support multi-segment PCI configuration access through enhanced configuration access mechanism.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeRuntimePciSegmentLibSegmentInfo
+ MODULE_UNI_FILE = DxeRuntimePciSegmentLibSegmentInfo.uni
+ FILE_GUID = F73EB3DE-F4E3-47CB-9F18-97796AE06314
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib|DXE_RUNTIME_DRIVER
+ CONSTRUCTOR = DxeRuntimePciSegmentLibConstructor
+ DESTRUCTOR = DxeRuntimePciSegmentLibDestructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ PciSegmentLibCommon.h
+ PciSegmentLibCommon.c
+ DxeRuntimePciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentInfoLib
+ UefiRuntimeLib
+ MemoryAllocationLib
+ DxeServicesTableLib
+ UefiBootServicesTableLib
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
new file mode 100644
index 0000000000..171fc7d16c
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
@@ -0,0 +1,21 @@
+// /** @file
+// Instance of Runtime PCI Segment Library that support multi-segment PCI configuration access.
+
+// PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to
+// support multi-segment PCI configuration access through enhanced configuration access mechanism.
+//
+// Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of Runtime PCI Segment Library that support multi-segment PCI configuration access."
+
+#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Library that consumes segment information provided by PciSegmentInfoLib to support multi-segment PCI configuration access through enhanced configuration access mechanism."
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
new file mode 100644
index 0000000000..7b7324d673
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
@@ -0,0 +1,1375 @@
+/** @file
+ Provide common routines used by BasePciSegmentLibSegmentInfo and
+ DxeRuntimePciSegmentLibSegmentInfo libraries.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciSegmentLibCommon.h"
+
+typedef struct {
+ UINT64 Register : 12;
+ UINT64 Function : 3;
+ UINT64 Device : 5;
+ UINT64 Bus : 8;
+ UINT64 Reserved1 : 4;
+ UINT64 Segment : 16;
+ UINT64 Reserved2 : 16;
+} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;
+
+/**
+ Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,
+ Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.
+ @param Count Number of segments.
+
+ @retval ECAM address.
+**/
+UINTN
+PciSegmentLibGetEcamAddress (
+ IN UINT64 Address,
+ IN CONST PCI_SEGMENT_INFO *SegmentInfo,
+ IN UINTN Count
+ )
+{
+ while (Count != 0) {
+ if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {
+ break;
+ }
+ SegmentInfo++;
+ Count--;
+ }
+ ASSERT (Count != 0);
+ ASSERT (
+ (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&
+ (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)
+ );
+ ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);
+ ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);
+
+ Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register);
+
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+ ASSERT (Address < BASE_4GB);
+ }
+
+ return PciSegmentLibVirtualAddress ((UINTN)Address);
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ return MmioBitFieldAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+ UINTN Address;
+
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((Address & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(volatile UINT8 *)Buffer = MmioRead8 (Address);
+ Address += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, MmioRead16 (Address));
+ Address += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, MmioRead32 (Address));
+ Address += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, MmioRead16 (Address));
+ Address += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(volatile UINT8 *)Buffer = MmioRead8 (Address);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+ UINTN Count;
+ PCI_SEGMENT_INFO *SegmentInfo;
+ UINTN Address;
+
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ SegmentInfo = GetPciSegmentInfo (&Count);
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((Address & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ MmioWrite8 (Address, *(UINT8*)Buffer);
+ Address += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ MmioWrite16 (Address, ReadUnaligned16 (Buffer));
+ Address += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ MmioWrite32 (Address, ReadUnaligned32 (Buffer));
+ Address += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ MmioWrite16 (Address, ReadUnaligned16 (Buffer));
+ Address += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ MmioWrite8 (Address, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
new file mode 100644
index 0000000000..4e1f523098
--- /dev/null
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
@@ -0,0 +1,57 @@
+/** @file
+ Provide common routines used by BasePciSegmentLibSegmentInfo and
+ DxeRuntimePciSegmentLibSegmentInfo libraries.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_SEGMENT_LIB_COMMON_H_
+#define _PCI_SEGMENT_LIB_COMMON_H_
+
+#include <Base.h>
+#include <IndustryStandard/PciExpress21.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PciSegmentInfoLib.h>
+
+/**
+ Return the linear address for the physical address.
+
+ @param Address The physical address.
+
+ @retval The linear address.
+**/
+UINTN
+PciSegmentLibVirtualAddress (
+ IN UINTN Address
+ );
+
+/**
+ Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,
+ Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.
+ @param Count Number of segments.
+
+ @retval ECAM address.
+**/
+UINTN
+PciSegmentLibGetEcamAddress (
+ IN UINT64 Address,
+ IN CONST PCI_SEGMENT_INFO *SegmentInfo,
+ IN UINTN Count
+ );
+
+#endif
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index e553a702a3..19545aa398 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -70,6 +70,8 @@ [Components]
MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
+ MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
+ MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/5] MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance.
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
` (3 preceding siblings ...)
2017-08-25 8:57 ` [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib Ruiyu Ni
@ 2017-08-25 8:57 ` Ruiyu Ni
2017-08-28 7:39 ` [PATCH v2 0/5] Add multiple PCI segments configuration access support Gao, Liming
5 siblings, 0 replies; 10+ messages in thread
From: Ruiyu Ni @ 2017-08-25 8:57 UTC (permalink / raw)
To: edk2-devel; +Cc: Liming Gao
The patch adds the new library class S3PciSegmentLib to carry out
PCI configuration and enable the PCI operations to be replayed during
an S3 resume. This library class maps directly on top of the
PciSegmentLib class.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/Library/S3PciSegmentLib.h | 1037 ++++++++++++++++
.../BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf | 45 +
.../BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni | 23 +
.../Library/BaseS3PciSegmentLib/S3PciSegmentLib.c | 1249 ++++++++++++++++++++
MdePkg/MdePkg.dec | 5 +
MdePkg/MdePkg.dsc | 1 +
6 files changed, 2360 insertions(+)
create mode 100644 MdePkg/Include/Library/S3PciSegmentLib.h
create mode 100644 MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
create mode 100644 MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni
create mode 100644 MdePkg/Library/BaseS3PciSegmentLib/S3PciSegmentLib.c
diff --git a/MdePkg/Include/Library/S3PciSegmentLib.h b/MdePkg/Include/Library/S3PciSegmentLib.h
new file mode 100644
index 0000000000..dbd77cf03a
--- /dev/null
+++ b/MdePkg/Include/Library/S3PciSegmentLib.h
@@ -0,0 +1,1037 @@
+/** @file
+ The multiple segments PCI configuration Library Services that carry out
+ PCI configuration and enable the PCI operations to be replayed during an
+ S3 resume. This library class maps directly on top of the PciSegmentLib class.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __S3_PCI_SEGMENT_LIB__
+#define __S3_PCI_SEGMENT_LIB__
+
+
+/**
+ Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
+ and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.
+
+ Computes an address that is compatible with the PCI Segment Library functions.
+ The unused upper bits of Segment, Bus, Device, Function,
+ and Register are stripped prior to the generation of the address.
+
+ @param Segment PCI Segment number. Range 0..65535.
+ @param Bus PCI Bus number. Range 0..255.
+ @param Device PCI Device number. Range 0..31.
+ @param Function PCI Function number. Range 0..7.
+ @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
+
+ @return The address that is compatible with the PCI Segment Library functions.
+
+**/
+#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
+ ((Segment != 0) ? \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) | \
+ (LShiftU64 ((Segment) & 0xffff, 32)) \
+ ) : \
+ ( ((Register) & 0xfff) | \
+ (((Function) & 0x07) << 12) | \
+ (((Device) & 0x1f) << 15) | \
+ (((Bus) & 0xff) << 20) \
+ ) \
+ )
+
+/**
+ Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentRead8 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ );
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 8-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 8-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ );
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 8-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentRead16 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ );
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 16-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentRead32 (
+ IN UINT64 Address
+ );
+
+/**
+ Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ );
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 32-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ );
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 32-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ );
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ );
+
+#endif
diff --git a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
new file mode 100644
index 0000000000..18df4a0be3
--- /dev/null
+++ b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Instance of S3 PCI Segment Library based on PCI Segment and S3 BootScript Library.
+#
+# S3 PCI Segment Services that perform PCI Configuration cycles and
+# also enable the PCI operation to be replayed during an S3 resume.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are
+# licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseS3SegmentPciLib
+ MODULE_UNI_FILE = BaseS3SegmentPciLib.uni
+ FILE_GUID = 17E2C90E-AD1F-443A-8C94-6E50C0E98607
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = S3PciSegmentLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ S3PciSegmentLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PciSegmentLib
+ S3BootScriptLib
+ DebugLib
diff --git a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni
new file mode 100644
index 0000000000..f614e7d7be
--- /dev/null
+++ b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni
@@ -0,0 +1,23 @@
+// /** @file
+// Instance of S3 PCI Segment Library based on PCI Segment and S3 BootScript Library.
+//
+// S3 PCI Segment Services that perform PCI Configuration cycles and
+// also enable the PCI operation to be replayed during an S3 resume.
+//
+// Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials are
+// licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of S3 PCI Segment Library based on PCI Segment and S3 BootScript Library."
+
+#string STR_MODULE_DESCRIPTION #language en-US "S3 PCI Segment Services that perform PCI Configuration cycles and also enable the PCI operation to be replayed during an S3 resume."
+
diff --git a/MdePkg/Library/BaseS3PciSegmentLib/S3PciSegmentLib.c b/MdePkg/Library/BaseS3PciSegmentLib/S3PciSegmentLib.c
new file mode 100644
index 0000000000..0cae84bd58
--- /dev/null
+++ b/MdePkg/Library/BaseS3PciSegmentLib/S3PciSegmentLib.c
@@ -0,0 +1,1249 @@
+/** @file
+ The multiple segments PCI configuration Library Services that carry out
+ PCI configuration and enable the PCI operations to be replayed during an
+ S3 resume. This library class maps directly on top of the PciSegmentLib class.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include <Base.h>
+
+#include <Library/DebugLib.h>
+#include <Library/S3BootScriptLib.h>
+#include <Library/PciSegmentLib.h>
+
+/**
+ Macro that converts address in PciSegmentLib format to the new address that can be pass
+ to the S3 Boot Script Library functions. The Segment is dropped.
+
+ @param Address Address in PciSegmentLib format.
+
+ @retval New address that can be pass to the S3 Boot Script Library functions.
+**/
+#define PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS(Address) \
+ ((((UINT32)(Address) >> 20) & 0xff) << 24) | \
+ ((((UINT32)(Address) >> 15) & 0x1f) << 16) | \
+ ((((UINT32)(Address) >> 12) & 0x07) << 8) | \
+ LShiftU64 ((Address) & 0xfff, 32) // Always put Register in high four bytes.
+
+/**
+ Saves a PCI configuration value to the boot script.
+
+ This internal worker function saves a PCI configuration value in
+ the S3 script to be replayed on S3 resume.
+
+ If the saving process fails, then ASSERT().
+
+ @param Width The width of PCI configuration.
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Buffer The buffer containing value.
+
+**/
+VOID
+InternalSavePciSegmentWriteValueToBootScript (
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
+ IN UINT64 Address,
+ IN VOID *Buffer
+ )
+{
+ RETURN_STATUS Status;
+
+ Status = S3BootScriptSavePciCfg2Write (
+ Width,
+ RShiftU64 ((Address), 32) & 0xffff,
+ PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (Address),
+ 1,
+ Buffer
+ );
+ ASSERT_RETURN_ERROR (Status);
+}
+
+/**
+ Saves an 8-bit PCI configuration value to the boot script.
+
+ This internal worker function saves an 8-bit PCI configuration value in
+ the S3 script to be replayed on S3 resume.
+
+ If the saving process fails, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value saved to boot script.
+
+ @return Value.
+
+**/
+UINT8
+InternalSavePciSegmentWrite8ValueToBootScript (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));
+}
+
+/**
+ Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
+ the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));
+}
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 8-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 8-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 8-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));
+}
+
+/**
+ Saves a 16-bit PCI configuration value to the boot script.
+
+ This internal worker function saves a 16-bit PCI configuration value in
+ the S3 script to be replayed on S3 resume.
+
+ If the saving process fails, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value saved to boot script.
+
+ @return Value.
+
+**/
+UINT16
+InternalSavePciSegmentWrite16ValueToBootScript (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads a 16-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));
+}
+
+/**
+ Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));
+}
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 16-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));
+}
+
+
+
+/**
+ Saves a 32-bit PCI configuration value to the boot script.
+
+ This internal worker function saves a 32-bit PCI configuration value in the S3 script
+ to be replayed on S3 resume.
+
+ If the saving process fails, then ASSERT().
+
+ @param Address Address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Value The value saved to boot script.
+
+ @return Value.
+
+**/
+UINT32
+InternalSavePciSegmentWrite32ValueToBootScript (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);
+
+ return Value;
+}
+
+/**
+ Reads a 32-bit PCI configuration register, and saves the value in the S3 script
+ to be replayed on S3 resume.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));
+}
+
+/**
+ Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
+ value, and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
+ be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));
+}
+
+/**
+ Writes a bit field to a PCI configuration register, and saves the value in
+ the S3 script to be replayed on S3 resume.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 32-bit port, and saves the value in the
+ S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register, and
+ saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, writes the result back to the bit field in the 32-bit port,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer,
+ and saves the value in the S3 script to be replayed on S3 resume.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ RETURN_STATUS Status;
+
+ Status = S3BootScriptSavePciCfg2Write (
+ S3BootScriptWidthUint8,
+ RShiftU64 (StartAddress, 32) & 0xffff,
+ PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),
+ PciSegmentReadBuffer (StartAddress, Size, Buffer),
+ Buffer
+ );
+ ASSERT_RETURN_ERROR (Status);
+ return Size;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space, and saves the value in the S3 script to be replayed on S3
+ resume.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ RETURN_STATUS Status;
+
+ Status = S3BootScriptSavePciCfg2Write (
+ S3BootScriptWidthUint8,
+ RShiftU64 (StartAddress, 32) & 0xffff,
+ PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),
+ PciSegmentWriteBuffer (StartAddress, Size, Buffer),
+ Buffer
+ );
+ ASSERT_RETURN_ERROR (Status);
+ return Size;
+}
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ad13185ed6..b65e1e591a 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -137,6 +137,11 @@ [LibraryClasses]
## @libraryclass Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
PciSegmentLib|Include/Library/PciSegmentLib.h
+ ## @libraryclass The multiple segments PCI configuration Library Services that carry out
+ ## PCI configuration and enable the PCI operations to be replayed during an
+ ## S3 resume. This library class maps directly on top of the PciSegmentLib class.
+ S3PciSegmentLib|Include/Library/PciSegmentLib.h
+
## @libraryclass Provides services to access PCI Configuration Space.
PciLib|Include/Library/PciLib.h
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 19545aa398..8f5726350e 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -72,6 +72,7 @@ [Components]
MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
+ MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
--
2.12.2.windows.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/5] Add multiple PCI segments configuration access support
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
` (4 preceding siblings ...)
2017-08-25 8:57 ` [PATCH v2 5/5] MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance Ruiyu Ni
@ 2017-08-28 7:39 ` Gao, Liming
5 siblings, 0 replies; 10+ messages in thread
From: Gao, Liming @ 2017-08-28 7:39 UTC (permalink / raw)
To: Ni, Ruiyu, edk2-devel@lists.01.org
Reviewed-by: Liming Gao <liming.gao@intel.com>
>-----Original Message-----
>From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>Ruiyu Ni
>Sent: Friday, August 25, 2017 4:57 PM
>To: edk2-devel@lists.01.org
>Subject: [edk2] [PATCH v2 0/5] Add multiple PCI segments configuration
>access support
>
>v2: Add missing function header and file header. Correct all incorrect file
>headers.
>
>Ruiyu Ni (5):
> MdePkg/PciSegmentLib: Fix typo in function header comments
> MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS
> MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance.
> MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
> MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance.
>
> MdePkg/Include/IndustryStandard/PciExpress21.h | 19 +-
> MdePkg/Include/Library/PciExpressLib.h | 5 +-
> MdePkg/Include/Library/PciSegmentInfoLib.h | 41 ++
> MdePkg/Include/Library/PciSegmentLib.h | 102 ++--
> .../Library/{PciSegmentLib.h => S3PciSegmentLib.h} | 364 ++++++-----
> .../BasePciSegmentInfoLibNull.inf | 41 ++
> .../BasePciSegmentInfoLibNull.uni | 20 +
> .../BasePciSegmentInfoLibNull/PciSegmentInfoLib.c | 38 ++
> .../Library/BasePciSegmentLibPci/PciSegmentLib.c | 136 +++--
> .../BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf | 45 ++
> .../BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni | 23 +
> .../BaseS3PciSegmentLib/S3PciSegmentLib.c} | 674 ++++++++++++++-----
>--
> .../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +++
> .../BasePciSegmentLibSegmentInfo.inf | 46 ++
> .../BasePciSegmentLibSegmentInfo.uni | 21 +
> .../DxeRuntimePciSegmentLib.c | 321 ++++++++++
> .../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 ++
> .../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
> .../PciSegmentLibCommon.c} | 656 +++++++++++++++-----
> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 ++
> .../PeiPciSegmentLibPciCfg2/PciSegmentLib.c | 187 +++---
> .../PciSegmentLib.c | 180 +++---
> MdePkg/MdePkg.dec | 8 +
> MdePkg/MdePkg.dsc | 4 +
> 24 files changed, 2250 insertions(+), 885 deletions(-)
> create mode 100644 MdePkg/Include/Library/PciSegmentInfoLib.h
> copy MdePkg/Include/Library/{PciSegmentLib.h => S3PciSegmentLib.h} (80%)
> create mode 100644
>MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
> create mode 100644
>MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.uni
> create mode 100644
>MdePkg/Library/BasePciSegmentInfoLibNull/PciSegmentInfoLib.c
> create mode 100644
>MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
> create mode 100644
>MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.uni
> copy MdePkg/{Include/Library/PciSegmentLib.h =>
>Library/BaseS3PciSegmentLib/S3PciSegmentLib.c} (66%)
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInf
>o.inf
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInf
>o.uni
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSeg
>mentInfo.inf
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSeg
>mentInfo.uni
> copy MdePkg/{Include/Library/PciSegmentLib.h =>
>Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c} (69%)
> create mode 100644
>MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
>
>--
>2.12.2.windows.2
>
>_______________________________________________
>edk2-devel mailing list
>edk2-devel@lists.01.org
>https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
2017-08-25 8:57 ` [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib Ruiyu Ni
@ 2017-08-29 18:51 ` Ard Biesheuvel
2017-08-29 20:39 ` Laszlo Ersek
0 siblings, 1 reply; 10+ messages in thread
From: Ard Biesheuvel @ 2017-08-29 18:51 UTC (permalink / raw)
To: Ruiyu Ni, Laszlo Ersek; +Cc: edk2-devel@lists.01.org, Liming Gao
Hi,
Some comments below.
On 25 August 2017 at 09:57, Ruiyu Ni <ruiyu.ni@intel.com> wrote:
> The patch adds two PciSegmentLib instances that consumes
> PciSegmentInfoLib to provide multiple segments PCI configuration
> access.
>
> BasePciSegmentLibSegmentInfo instance is a BASE library.
> DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with
> runtime drivers to provide not only boot time but also runtime
> PCI configuration access.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> ---
> .../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +
> .../BasePciSegmentLibSegmentInfo.inf | 46 +
> .../BasePciSegmentLibSegmentInfo.uni | 21 +
> .../DxeRuntimePciSegmentLib.c | 321 +++++
> .../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 +
> .../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.c | 1375 ++++++++++++++++++++
> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 +
> MdePkg/MdePkg.dsc | 2 +
> 9 files changed, 1969 insertions(+)
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
>
[...]
> diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
> new file mode 100644
> index 0000000000..7b7324d673
> --- /dev/null
> +++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
> @@ -0,0 +1,1375 @@
> +/** @file
> + Provide common routines used by BasePciSegmentLibSegmentInfo and
> + DxeRuntimePciSegmentLibSegmentInfo libraries.
> +
> + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> + This program and the accompanying materials are
> + licensed and made available under the terms and conditions of
> + the BSD License which accompanies this distribution. The full
> + text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "PciSegmentLibCommon.h"
> +
> +typedef struct {
> + UINT64 Register : 12;
> + UINT64 Function : 3;
> + UINT64 Device : 5;
> + UINT64 Bus : 8;
> + UINT64 Reserved1 : 4;
> + UINT64 Segment : 16;
> + UINT64 Reserved2 : 16;
> +} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;
> +
Is this guaranteed to work as expected by the C spec?
> +/**
> + Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,
> + Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.
> + @param Count Number of segments.
> +
> + @retval ECAM address.
> +**/
> +UINTN
> +PciSegmentLibGetEcamAddress (
> + IN UINT64 Address,
> + IN CONST PCI_SEGMENT_INFO *SegmentInfo,
> + IN UINTN Count
> + )
> +{
> + while (Count != 0) {
> + if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {
> + break;
> + }
> + SegmentInfo++;
> + Count--;
> + }
> + ASSERT (Count != 0);
> + ASSERT (
> + (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&
> + (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)
> + );
> + ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);
> + ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);
> +
> + Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (
> + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,
> + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,
> + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,
> + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register);
> +
> + if (sizeof (UINTN) == sizeof (UINT32)) {
> + ASSERT (Address < BASE_4GB);
> + }
> +
> + return PciSegmentLibVirtualAddress ((UINTN)Address);
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
> +}
> +
> +/**
> + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentOr8 (
> + IN UINT64 Address,
> + IN UINT8 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAnd8 (
> + IN UINT64 Address,
> + IN UINT8 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
> + followed a bitwise OR with another 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAndThenOr8 (
> + IN UINT64 Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldRead8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 8-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldWrite8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 8-bit register.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAnd8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
> +}
MmioBitFieldAnd8
> +
> +/**
> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAndThenOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by OrData, and
> + writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned. This function
> + must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function and
> + Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentOr16 (
> + IN UINT64 Address,
> + IN UINT16 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAnd16 (
> + IN UINT64 Address,
> + IN UINT16 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
> + followed a bitwise OR with another 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAndThenOr16 (
> + IN UINT64 Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldRead16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 16-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldWrite16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
> + the result back to the bit field in the 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
> + AND, writes the result back to the bit field in the 16-bit register.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 16-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAnd16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
> +}
MmioBitFieldAnd16
> +
> +/**
> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAndThenOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentOr32 (
> + IN UINT64 Address,
> + IN UINT32 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAnd32 (
> + IN UINT64 Address,
> + IN UINT32 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
> + followed a bitwise OR with another 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAndThenOr32 (
> + IN UINT64 Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldRead32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 32-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldWrite32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 Value
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 OrData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 32-bit register.
> +
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
> + AND between the read result and the value specified by AndData, and writes the result
> + to the 32-bit PCI configuration register specified by Address. The value written to
> + the PCI configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in AndData are stripped.
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAnd32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData
> + )
> +{
> + UINTN Count;
> + PCI_SEGMENT_INFO *SegmentInfo;
> +
> + SegmentInfo = GetPciSegmentInfo (&Count);
> + return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);
> +}
MmioBitFieldAnd32
--
Ard.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
2017-08-29 18:51 ` Ard Biesheuvel
@ 2017-08-29 20:39 ` Laszlo Ersek
2017-08-29 20:47 ` Andrew Fish
0 siblings, 1 reply; 10+ messages in thread
From: Laszlo Ersek @ 2017-08-29 20:39 UTC (permalink / raw)
To: Ard Biesheuvel, Ruiyu Ni; +Cc: edk2-devel@lists.01.org, Liming Gao
On 08/29/17 20:51, Ard Biesheuvel wrote:
> Hi,
>
> Some comments below.
>
> On 25 August 2017 at 09:57, Ruiyu Ni <ruiyu.ni@intel.com> wrote:
>> The patch adds two PciSegmentLib instances that consumes
>> PciSegmentInfoLib to provide multiple segments PCI configuration
>> access.
>>
>> BasePciSegmentLibSegmentInfo instance is a BASE library.
>> DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with
>> runtime drivers to provide not only boot time but also runtime
>> PCI configuration access.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
>> Cc: Liming Gao <liming.gao@intel.com>
>> ---
>> .../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +
>> .../BasePciSegmentLibSegmentInfo.inf | 46 +
>> .../BasePciSegmentLibSegmentInfo.uni | 21 +
>> .../DxeRuntimePciSegmentLib.c | 321 +++++
>> .../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 +
>> .../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
>> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.c | 1375 ++++++++++++++++++++
>> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 +
>> MdePkg/MdePkg.dsc | 2 +
>> 9 files changed, 1969 insertions(+)
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
>>
> [...]
>> diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>> new file mode 100644
>> index 0000000000..7b7324d673
>> --- /dev/null
>> +++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>> @@ -0,0 +1,1375 @@
>> +/** @file
>> + Provide common routines used by BasePciSegmentLibSegmentInfo and
>> + DxeRuntimePciSegmentLibSegmentInfo libraries.
>> +
>> + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
>> + This program and the accompanying materials are
>> + licensed and made available under the terms and conditions of
>> + the BSD License which accompanies this distribution. The full
>> + text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include "PciSegmentLibCommon.h"
>> +
>> +typedef struct {
>> + UINT64 Register : 12;
>> + UINT64 Function : 3;
>> + UINT64 Device : 5;
>> + UINT64 Bus : 8;
>> + UINT64 Reserved1 : 4;
>> + UINT64 Segment : 16;
>> + UINT64 Reserved2 : 16;
>> +} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;
>> +
>
> Is this guaranteed to work as expected by the C spec?
>From C99, "6.7.2.1 Structure and union specifiers", paragraph 10:
"An implementation may allocate any addressable storage unit large
enough to hold a bit-field. If enough space remains, a bit-field that
immediately follows another bit-field in a structure shall be packed
into adjacent bits of the same unit. If insufficient space remains,
whether a bit-field that does not fit is put into the next unit or
overlaps adjacent units is implementation-defined. The order of
allocation of bit-fields within a unit (high-order to low-order or
low-order to high-order) is implementation-defined. The alignment of the
addressable storage unit is unspecified."
Due to the above, I consider bit-fields totally nonportable, and avoid
introducing bit-fields in any code I write.
However, "implementation-defined" means the compiler docs have to
describe how bit-fields are laid out. If you know your toolchain (...all
of your toolchains...), I guess you can make them work. FWIW, edk2 is
chock-full of bit-fields.
... For example, the clang build options contain "-mms-bitfields":
https://clang.llvm.org/docs/ClangCommandLineReference.html
--> "Set the default structure layout to be compatible with the
Microsoft compiler standard".
The GCC docs are here:
https://gcc.gnu.org/onlinedocs/gcc/Structures-unions-enumerations-and-bit-fields-implementation.html
--> "Determined by ABI."
These structures make me shudder, but if they work, I just close my eyes
and move on. :/
Laszlo
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib
2017-08-29 20:39 ` Laszlo Ersek
@ 2017-08-29 20:47 ` Andrew Fish
0 siblings, 0 replies; 10+ messages in thread
From: Andrew Fish @ 2017-08-29 20:47 UTC (permalink / raw)
To: Laszlo Ersek
Cc: Ard Biesheuvel, Ruiyu Ni, edk2-devel@lists.01.org, Liming Gao
> On Aug 29, 2017, at 1:39 PM, Laszlo Ersek <lersek@redhat.com> wrote:
>
> On 08/29/17 20:51, Ard Biesheuvel wrote:
>> Hi,
>>
>> Some comments below.
>>
>> On 25 August 2017 at 09:57, Ruiyu Ni <ruiyu.ni@intel.com> wrote:
>>> The patch adds two PciSegmentLib instances that consumes
>>> PciSegmentInfoLib to provide multiple segments PCI configuration
>>> access.
>>>
>>> BasePciSegmentLibSegmentInfo instance is a BASE library.
>>> DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with
>>> runtime drivers to provide not only boot time but also runtime
>>> PCI configuration access.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
>>> Cc: Liming Gao <liming.gao@intel.com>
>>> ---
>>> .../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 +
>>> .../BasePciSegmentLibSegmentInfo.inf | 46 +
>>> .../BasePciSegmentLibSegmentInfo.uni | 21 +
>>> .../DxeRuntimePciSegmentLib.c | 321 +++++
>>> .../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 +
>>> .../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 +
>>> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.c | 1375 ++++++++++++++++++++
>>> .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 +
>>> MdePkg/MdePkg.dsc | 2 +
>>> 9 files changed, 1969 insertions(+)
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>>> create mode 100644 MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h
>>>
>> [...]
>>> diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>>> new file mode 100644
>>> index 0000000000..7b7324d673
>>> --- /dev/null
>>> +++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c
>>> @@ -0,0 +1,1375 @@
>>> +/** @file
>>> + Provide common routines used by BasePciSegmentLibSegmentInfo and
>>> + DxeRuntimePciSegmentLibSegmentInfo libraries.
>>> +
>>> + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
>>> + This program and the accompanying materials are
>>> + licensed and made available under the terms and conditions of
>>> + the BSD License which accompanies this distribution. The full
>>> + text of the license may be found at
>>> + http://opensource.org/licenses/bsd-license.php.
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>>> +
>>> +**/
>>> +
>>> +#include "PciSegmentLibCommon.h"
>>> +
>>> +typedef struct {
>>> + UINT64 Register : 12;
>>> + UINT64 Function : 3;
>>> + UINT64 Device : 5;
>>> + UINT64 Bus : 8;
>>> + UINT64 Reserved1 : 4;
>>> + UINT64 Segment : 16;
>>> + UINT64 Reserved2 : 16;
>>> +} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;
>>> +
>>
>> Is this guaranteed to work as expected by the C spec?
>
> From C99, "6.7.2.1 Structure and union specifiers", paragraph 10:
>
> "An implementation may allocate any addressable storage unit large
> enough to hold a bit-field. If enough space remains, a bit-field that
> immediately follows another bit-field in a structure shall be packed
> into adjacent bits of the same unit. If insufficient space remains,
> whether a bit-field that does not fit is put into the next unit or
> overlaps adjacent units is implementation-defined. The order of
> allocation of bit-fields within a unit (high-order to low-order or
> low-order to high-order) is implementation-defined. The alignment of the
> addressable storage unit is unspecified."
>
> Due to the above, I consider bit-fields totally nonportable, and avoid
> introducing bit-fields in any code I write.
>
> However, "implementation-defined" means the compiler docs have to
> describe how bit-fields are laid out. If you know your toolchain (...all
> of your toolchains...), I guess you can make them work. FWIW, edk2 is
> chock-full of bit-fields.
>
> ... For example, the clang build options contain "-mms-bitfields":
>
Laszlo,
FYI -mms-bitfields was to force EFI ABI compatibility, not to enabled bit fields per say. I can't remember why we used ms-bitfields vs. ms-struct?
Thanks,
Andrew Fish
> https://clang.llvm.org/docs/ClangCommandLineReference.html <https://clang.llvm.org/docs/ClangCommandLineReference.html>
>
> --> "Set the default structure layout to be compatible with the
> Microsoft compiler standard".
>
> The GCC docs are here:
>
> https://gcc.gnu.org/onlinedocs/gcc/Structures-unions-enumerations-and-bit-fields-implementation.html <https://gcc.gnu.org/onlinedocs/gcc/Structures-unions-enumerations-and-bit-fields-implementation.html>
>
> --> "Determined by ABI."
>
> These structures make me shudder, but if they work, I just close my eyes
> and move on. :/
>
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org <mailto:edk2-devel@lists.01.org>
> https://lists.01.org/mailman/listinfo/edk2-devel <https://lists.01.org/mailman/listinfo/edk2-devel>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-08-29 20:44 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-25 8:57 [PATCH v2 0/5] Add multiple PCI segments configuration access support Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 1/5] MdePkg/PciSegmentLib: Fix typo in function header comments Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 2/5] MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 3/5] MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance Ruiyu Ni
2017-08-25 8:57 ` [PATCH v2 4/5] MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib Ruiyu Ni
2017-08-29 18:51 ` Ard Biesheuvel
2017-08-29 20:39 ` Laszlo Ersek
2017-08-29 20:47 ` Andrew Fish
2017-08-25 8:57 ` [PATCH v2 5/5] MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance Ruiyu Ni
2017-08-28 7:39 ` [PATCH v2 0/5] Add multiple PCI segments configuration access support Gao, Liming
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