From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x231.google.com (mail-wr0-x231.google.com [IPv6:2a00:1450:400c:c0c::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6D5D721E2BE5C for ; Tue, 29 Aug 2017 08:43:27 -0700 (PDT) Received: by mail-wr0-x231.google.com with SMTP id 40so10915570wrv.5 for ; Tue, 29 Aug 2017 08:46:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=LqFOb9/nZlZaK0SnZ/ZfnLQhRJ1yXhWIHNWer8uZOuo=; b=GC5rSeiGjk8MqXDTUi7NsWNtCtx1SjPjl1GWVbWfeZSBvhYoZMfyxv2zE3RKHQZAZY 357vAgjDrtm7u4ydPZ456pkVqMHacPPMd6vKR1cD4e6/rtV8sottZSOiNpOs+4vehhg2 dEx02IzRsWdZ+EWTjPUk5AkDftv8iPk9lRYmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=LqFOb9/nZlZaK0SnZ/ZfnLQhRJ1yXhWIHNWer8uZOuo=; b=XGF8dKtDp1f3pu8pd2XEYTTAcPmov6ZFMu51fzvETFkjfCTxgVC0Nsxb+9wfj5PyDN 101bxrvT0M+j1jJuI8Ye31I3Vn+/mEN+RrPTGSzcQWllWjt4syAoUNG2pK9IbCP2TieD cbza0OjGmMAEiBLfNpK/183bgc33rCjLkdfofI6XdbInrfn5AVYiS7q9rGVFQkydxXTv +QVY2uTjNT4FmltGnjyCS9Bgj0AcV7O93WPM/CZsDoKlm9oAs9d9qZ0b4mFYgllMyUIq mxA0wnnaaq0DqRO0IjnEmOFxXFVynQiNXmSSYffS4eQ2c4cDRFAmVZsLTmc4xzXBe9cr nr3w== X-Gm-Message-State: AHYfb5g4n1nG4g1AXvbNwjLlY8mb5NBAq2+8p54bhdW8uuUPMm+GdC+6 fz1zkdyIwb3RDCHn0hGsvg== X-Received: by 10.223.177.216 with SMTP id r24mr546644wra.50.1504021566658; Tue, 29 Aug 2017 08:46:06 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f21sm3166840wra.97.2017.08.29.08.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 08:46:06 -0700 (PDT) Date: Tue, 29 Aug 2017 16:46:03 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, mw@semihalf.com Message-ID: <20170829154603.fvhfwp66asipxnoe@bivouac.eciton.net> References: <20170825122554.17819-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20170825122554.17819-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] Platform/Armada/Pp2Dxe: switch to ArmDmaLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Aug 2017 15:43:27 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Aug 25, 2017 at 01:25:54PM +0100, Ard Biesheuvel wrote: > Instead of hardcoding the non-cache coherent nature of this device > by invoking UncachedMemoryAllocationLib directly for allocating > shared buffers, switch to DmaLib, which encapsulates this at a > more abstract level. This allows the driver to be shared with > platforms that are cache coherent (by simply switching to another > DmaLib implementation), and removes the hardcoded dependency on > UncachedMemoryAllocationLib, which will be removed from upstream > EDK2. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Ah, and there is the non-bogus fix :) Reviewed-by: Leif Lindholm > --- > This depends on patches #1 and #2 of > https://lists.01.org/pipermail/edk2-devel/2017-August/013740.html > > Platform/Marvell/Armada/Armada.dsc.inc | 1 - > Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 35 ++++++++++++++------ > Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 2 +- > Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 4 +-- > 4 files changed, 28 insertions(+), 14 deletions(-) > > diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc > index 4e8f289fcbca..04b108619ac7 100644 > --- a/Platform/Marvell/Armada/Armada.dsc.inc > +++ b/Platform/Marvell/Armada/Armada.dsc.inc > @@ -37,7 +37,6 @@ > UtmiPhyLib|Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf > > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf > - UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf > DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf > > # Basic utility libraries > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c > index 8de2473d09f0..1e2ccd0dbe9d 100644 > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c > @@ -175,9 +175,10 @@ Pp2DxeBmPoolInit ( > VOID > ) > { > - INTN Index; > - UINT8 *PoolAddr; > - UINT32 PoolSize = (sizeof(VOID *) * MVPP2_BM_SIZE) * 2 + MVPP2_BM_POOL_PTR_ALIGN; > + INTN Index; > + UINT8 *PoolAddr; > + UINT32 PoolSize; > + EFI_STATUS Status; > > ASSERT(MVPP2_BM_POOL_PTR_ALIGN >= sizeof(UINTN)); > > @@ -194,11 +195,16 @@ Pp2DxeBmPoolInit ( > return EFI_OUT_OF_RESOURCES; > } > > - PoolAddr = UncachedAllocateAlignedZeroPool (PoolSize, MVPP2_BM_POOL_PTR_ALIGN); > - if (PoolAddr == NULL) { > - return EFI_OUT_OF_RESOURCES; > + Status = DmaAllocateAlignedBuffer (EfiBootServicesData, > + EFI_SIZE_TO_PAGES (PoolSize), > + MVPP2_BM_POOL_PTR_ALIGN, > + (VOID **)&PoolAddr); > + if (EFI_ERROR (Status)) { > + goto FreePools; > } > > + ZeroMem (PoolAddr, PoolSize); > + > Mvpp2Shared->BmPools->Id = MVPP2_BM_POOL; > Mvpp2Shared->BmPools->VirtAddr = (UINT32 *)PoolAddr; > Mvpp2Shared->BmPools->PhysAddr = (UINTN)PoolAddr; > @@ -206,6 +212,10 @@ Pp2DxeBmPoolInit ( > Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE); > > return EFI_SUCCESS; > + > +FreePools: > + FreePool (Mvpp2Shared->BmPools); > + return Status; > } > > /* Enable and fill BM pool */ > @@ -1169,12 +1179,17 @@ Pp2DxeInitialise ( > Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency); > > /* Prepare buffers */ > - BufferSpace = UncachedAllocateAlignedZeroPool (BD_SPACE, MVPP2_BUFFER_ALIGN_SIZE); > - if (BufferSpace == NULL) { > - DEBUG((DEBUG_ERROR, "Failed to allocate buffer space\n")); > - return EFI_OUT_OF_RESOURCES; > + Status = DmaAllocateAlignedBuffer (EfiBootServicesData, > + EFI_SIZE_TO_PAGES (BD_SPACE), > + MVPP2_BUFFER_ALIGN_SIZE, > + &BufferSpace); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed to allocate buffer space\n")); > + return Status; > } > > + ZeroMem (BufferSpace, BD_SPACE); > + > BufferLocation.TxDescs = BufferSpace; > BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)((UINTN)BufferSpace + MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); > BufferLocation.RxDescs = (MVPP2_RX_DESC *)((UINTN)BufferSpace + > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h > index 3bb0c4a65376..a179638fd609 100644 > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h > @@ -46,13 +46,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #include > #include > #include > +#include > #include > #include > #include > #include > #include > #include > -#include > > #include "Mvpp2LibHw.h" > > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf > index 87cc5e8ded74..9052fe27b7f3 100644 > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf > @@ -43,13 +43,14 @@ > Mvpp2Lib.c > > [Packages] > + EmbeddedPkg/EmbeddedPkg.dec > MdePkg/MdePkg.dec > MdeModulePkg/MdeModulePkg.dec > - ArmPlatformPkg/ArmPlatformPkg.dec > ArmPkg/ArmPkg.dec > Platform/Marvell/Marvell.dec > > [LibraryClasses] > + DmaLib > IoLib > PcdLib > BaseLib > @@ -60,7 +61,6 @@ > UefiDriverEntryPoint > UefiBootServicesTableLib > MemoryAllocationLib > - UncachedMemoryAllocationLib > CacheMaintenanceLib > > [Protocols] > -- > 2.11.0 >