From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3881C208F7AD6 for ; Thu, 31 Aug 2017 06:06:06 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id f127so4483153wmf.1 for ; Thu, 31 Aug 2017 06:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=LIB4hexRr9EPGsI9J2oQmIvJeLHgQY3t/fyeH5hQsCiaH1Y1PurZ+dMyFkrAaCVLnO 795n4qec8FfzrgjrOW9HajA7XWbFbw8GgiaNOFA0XjI2sH5e+OPeLLxPegDF9LW6OKEQ YfhgP5FOHRbv/sNFcX4Prkq5yAOh9D0Kesr6s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=ld6Zh0jFgRvCv1vaH0VNNAu+FPG1t0WVKIhk1vK3qDDvz18AL1lJ5heBnD1ayq2Dim IoVBPu5AnjMqcOeRppWQLF22y7YH6UTLKKJ4QhIA6KbA1BS7fqoylzBBr10qwPBd8J3h hpkIk5mXEdoASbrz2bnFJ00po2obaGAABkgmZOnSn15ttkfE8gWAr0nc9GSwTnKg0grm WWL+0z4tknCJuC6xHZPWGDI4dFZn5CcocS6/wjv/sFLd3quTb9SNuxtsUvVXXcJbUQXE SIhX0++U5cTJaTk52J/VozUCHu3l7EBo5I9vpt75txMXphC6j3E0SLI+PZoj778cYMJP bdag== X-Gm-Message-State: AHYfb5ibgzm0LVVWF+oyW4+UHAoCudBe7wSy7zkkAxOBodlDh3uXKXnp +6DrLRWaC1qQvBclHQv3rw== X-Received: by 10.28.113.207 with SMTP id d76mr486446wmi.140.1504184927725; Thu, 31 Aug 2017 06:08:47 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, alan@softiron.com, liming.gao@intel.com, yonghong.zhu@intel.com, Ard Biesheuvel Date: Thu, 31 Aug 2017 14:08:30 +0100 Message-Id: <20170831130830.12833-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 13:06:06 -0000 Fix the trigger type of the legacy INTx interrupts. The Seattle SoC manual classifies them as level high, not rising edge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 28 ++++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts index e57e702029ba..2c05fdbb8b71 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts @@ -291,20 +291,20 @@ msi-parent = <&msi>; reg = <0x0 0xf0000000 0x0 0x10000000>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>, - - <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>, - - <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>; + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_LEVEL_HIGH>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_LEVEL_HIGH>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_LEVEL_HIGH>; dma-coherent; dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ -- 2.11.0