From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com [IPv6:2a00:1450:400c:c09::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1CC0C21959CAD for ; Fri, 8 Sep 2017 11:20:40 -0700 (PDT) Received: by mail-wm0-x22e.google.com with SMTP id i189so9390313wmf.1 for ; Fri, 08 Sep 2017 11:23:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C4vzijepps6K7iHklENQCnv/oubSVRrE29/BoPa3P/k=; b=GVCLsfPZjglr0NWGs49MgPHqOnw22U9MzIr4GAB4eMlyPa6SnWKhITVW68iPqXs2U/ m5yT7TrShHe6rH9hDUT80ebwSAn6XLwj3S+AEX9E1wSJQ5J5MyJFs+6MbWl9RuenoT+O Zdmn+bQSurFSP3VtEdHgXglDO9ipSr4p06V60= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C4vzijepps6K7iHklENQCnv/oubSVRrE29/BoPa3P/k=; b=kM5tayM4qPbuTwjAOhqksUqayvxcruVd9dK546hlY7vT011IRCO/hXuqGuyU0V4zYa Bv7Rbek5x/40xE08Ai/juvzi1eIIntVghzOW0EEdyDmd91l6gv7phL21MftTu0oAMk90 i9fDK1D1oxLeF62yuUjoZJhVYXBlnEvyWv0M5XKBCalKVlJfwVYG8pH4mjwt/AlTuN+b tPQxeoTPqnfQdGkFmyBnXKuObQ5y3lwBPJ0NuwRc7OIPYX3hTFBRpGSxUvysle0eKtt6 n9YQVTJKzEReItABO0ZR/1MJojd0Fdtmqzrc+yuYSGtRR6JhxYcVFPQqtCmeeqf5GnSu KKCQ== X-Gm-Message-State: AHPjjUgPJwLrfcisoee8Dvz8m5OI0OWKw4uyqUF7grpTuHIygyh36RV7 qf5PGCywu36eRVrEmgvVgA== X-Google-Smtp-Source: ADKCNb66MO3bxEWOyc7lG1CzJmfIPMmINM/9c7Hd4MQ492UjWzgDIGyKmqVdehQFSJ0pCpWDcZkH4Q== X-Received: by 10.28.234.72 with SMTP id i69mr2194509wmh.80.1504895010919; Fri, 08 Sep 2017 11:23:30 -0700 (PDT) Received: from localhost.localdomain ([154.151.223.220]) by smtp.gmail.com with ESMTPSA id s196sm3254354wmb.6.2017.09.08.11.23.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Sep 2017 11:23:30 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel Date: Fri, 8 Sep 2017 19:23:03 +0100 Message-Id: <20170908182315.9591-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170908182315.9591-1-ard.biesheuvel@linaro.org> References: <20170908182315.9591-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Sep 2017 18:20:40 -0000 Replace the common MemoryInitPeiLib implementation with one that does not remove the primary FV from the memory map. This is a waste of memory and TLB entries, given that the OS can no longer use a 1 GB block mapping to map this memory. Since we have our own implementation now, there is no point in using ArmPlatformLib's GetVirtualMemoryMap() implementation, and we can simply declare and map the regions directly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c | 140 ++++++++++++++++++++ Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf | 50 +++++++ 2 files changed, 190 insertions(+) diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c new file mode 100644 index 000000000000..1d25d63f1b6c --- /dev/null +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c @@ -0,0 +1,140 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include + +#include +#include + +#define ARM_MEMORY_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK } + +#define ARM_DEVICE_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE } + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { + // DDR - 2 GB + ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_1_BASE, + SYNQUACER_SYSTEM_MEMORY_1_SZ), + + // DDR - 30 GB + ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_2_BASE, + SYNQUACER_SYSTEM_MEMORY_2_SZ), + + // DDR - 32 GB +// ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_3_BASE, +// SYNQUACER_SYSTEM_MEMORY_3_SZ), + + // Synquacer OnChip non-secure ROM + ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_ROM_BASE, + SYNQUACER_NON_SECURE_ROM_SZ), + + // Synquacer OnChip peripherals + ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, + SYNQUACER_PERIPHERALS_SZ), + + // Synquacer OnChip non-secure SRAM + ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_SRAM_BASE, + SYNQUACER_NON_SECURE_SRAM_SZ), + + // Synquacer GIC-500 + ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE), + ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE), + + // Synquacer eMMC(SDH30) + ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ), + + // Synquacer EEPROM + ARM_DEVICE_REGION (SYNQUACER_EEPROM_BASE, SYNQUACER_EEPROM_BASE_SZ), + + // Synquacer NETSEC + ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ), + + // PCIe control registers + ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE), + + // PCIe config space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE, + SYNQUACER_PCI_SEG0_CONFIG_SIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE, + SYNQUACER_PCI_SEG1_CONFIG_SIZE), + + // PCIe I/O space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE), + + { } +}; + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + RETURN_STATUS Status; + + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SYNQUACER_SYSTEM_MEMORY_1_BASE, + SYNQUACER_SYSTEM_MEMORY_1_SZ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SYNQUACER_SYSTEM_MEMORY_2_BASE, + SYNQUACER_SYSTEM_MEMORY_2_SZ); + +// BuildResourceDescriptorHob ( +// EFI_RESOURCE_SYSTEM_MEMORY, +// ResourceAttributes, +// SYNQUACER_SYSTEM_MEMORY_3_BASE, +// SYNQUACER_SYSTEM_MEMORY_3_SZ); + + Status = ArmConfigureMmu (mVirtualMemoryTable, NULL, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf new file mode 100644 index 000000000000..5f45c30a5e92 --- /dev/null +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SynquacerMemoryInitPeiLib + FILE_GUID = c69d3ce7-098c-4fcd-afb4-15fb05a39308 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM + +[Sources] + SynquacerMemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Socionext/Synquacer/Synquacer.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + DebugLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -- 2.11.0