* [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 13:31 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation Ard Biesheuvel
` (12 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Add a package .DEC description for Synquacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h | 65 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Include/Platform/Pcie.h | 63 +++++++++++++++++++
Silicon/Socionext/Synquacer/Synquacer.dec | 22 +++++++
3 files changed, 150 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
new file mode 100644
index 000000000000..1b5393c32f1d
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
@@ -0,0 +1,65 @@
+/** @file
+ PCI memory configuration for Synquacer
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
+#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
+
+// Memory mapped SPI NOR
+#define SYNQUACER_SPI_NOR_BASE 0x08000000
+#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB
+
+// On-Chip non-secure ROM
+#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000
+#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB
+
+// On-Chip Peripherals
+#define SYNQUACER_PERIPHERALS_BASE 0x20000000
+#define SYNQUACER_PERIPHERALS_SZ 0x0E000000
+
+// On-Chip non-secure SRAM
+#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000
+#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_32KB
+
+// GIC-500
+#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase)
+#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB
+#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase)
+#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB
+
+// eMMC(SDH30)
+#define SYNQUACER_EMMC_BASE 0x52300000
+#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB
+
+#define SYNQUACER_EEPROM_BASE 0x10000000
+#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB
+
+// NETSEC
+#define SYNQUACER_NETSEC_BASE 0x522D0000
+#define SYNQUACER_NETSEC_BASE_SZ SIZE_64KB
+
+#define SYNQUACER_SYSTEM_MEMORY_1_BASE 0x80000000
+#define SYNQUACER_SYSTEM_MEMORY_1_SZ (SIZE_2GB - SIZE_16MB)
+
+#define SYNQUACER_SYSTEM_MEMORY_2_BASE 0x0880000000ULL
+#define SYNQUACER_SYSTEM_MEMORY_2_SZ (SIZE_32GB - SIZE_2GB)
+
+#define SYNQUACER_SYSTEM_MEMORY_3_BASE 0x8800000000ULL
+#define SYNQUACER_SYSTEM_MEMORY_3_SZ SIZE_32GB
+
+// PCI
+#define SYNQUACER_PCIE_BASE 0x58200000
+#define SYNQUACER_PCIE_SIZE 0x00200000
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
new file mode 100644
index 000000000000..f7bdc13ad915
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
@@ -0,0 +1,63 @@
+/** @file
+ PCI memory configuration for Synquacer
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_PCI_H_
+#define _SYNQUACER_PLATFORM_PCI_H_
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
+#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
+
+#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0
+#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e
+
+#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0
+#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff
+#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000
+#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff
+#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000
+
+#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000
+#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff
+#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
+#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
+
+#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0
+#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e
+
+#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff
+#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000
+#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff
+#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000
+
+#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000
+#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff
+#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Synquacer.dec b/Silicon/Socionext/Synquacer/Synquacer.dec
new file mode 100644
index 000000000000..955a056a8d59
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Synquacer.dec
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = Synquacer
+ PACKAGE_GUID = 9c782fd2-7db1-438d-b51c-2155cee2c5cc
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers
2017-09-08 18:23 ` [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers Ard Biesheuvel
@ 2017-09-11 13:31 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 13:31 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:02PM +0100, Ard Biesheuvel wrote:
> Add a package .DEC description for Synquacer with an [Includes]
> section, and add header files containing descriptions of the
> platform's memory map and PCIe configuration. No code yet.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h | 65 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Include/Platform/Pcie.h | 63 +++++++++++++++++++
> Silicon/Socionext/Synquacer/Synquacer.dec | 22 +++++++
I'll start with the bikeshedding (questions for consideration):
- SynQuacer is written that (<-) way in all public information I can
find.
- Does SynQuacer refer to the SC2A11, or is SC2A11 the first member of
a SynQuacer family of products?
> 3 files changed, 150 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
> new file mode 100644
> index 000000000000..1b5393c32f1d
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
> @@ -0,0 +1,65 @@
> +/** @file
> + PCI memory configuration for Synquacer
Not just PCI?
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
> +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
> +
> +// Memory mapped SPI NOR
> +#define SYNQUACER_SPI_NOR_BASE 0x08000000
> +#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB
> +
> +// On-Chip non-secure ROM
> +#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000
> +#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB
> +
> +// On-Chip Peripherals
> +#define SYNQUACER_PERIPHERALS_BASE 0x20000000
> +#define SYNQUACER_PERIPHERALS_SZ 0x0E000000
> +
> +// On-Chip non-secure SRAM
> +#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000
> +#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_32KB
> +
> +// GIC-500
> +#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase)
> +#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB
> +#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase)
> +#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB
> +
> +// eMMC(SDH30)
> +#define SYNQUACER_EMMC_BASE 0x52300000
> +#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB
> +
> +#define SYNQUACER_EEPROM_BASE 0x10000000
> +#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB
> +
> +// NETSEC
> +#define SYNQUACER_NETSEC_BASE 0x522D0000
> +#define SYNQUACER_NETSEC_BASE_SZ SIZE_64KB
> +
> +#define SYNQUACER_SYSTEM_MEMORY_1_BASE 0x80000000
> +#define SYNQUACER_SYSTEM_MEMORY_1_SZ (SIZE_2GB - SIZE_16MB)
> +
> +#define SYNQUACER_SYSTEM_MEMORY_2_BASE 0x0880000000ULL
> +#define SYNQUACER_SYSTEM_MEMORY_2_SZ (SIZE_32GB - SIZE_2GB)
> +
> +#define SYNQUACER_SYSTEM_MEMORY_3_BASE 0x8800000000ULL
> +#define SYNQUACER_SYSTEM_MEMORY_3_SZ SIZE_32GB
> +
> +// PCI
> +#define SYNQUACER_PCIE_BASE 0x58200000
> +#define SYNQUACER_PCIE_SIZE 0x00200000
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
> new file mode 100644
> index 000000000000..f7bdc13ad915
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
> @@ -0,0 +1,63 @@
> +/** @file
> + PCI memory configuration for Synquacer
Not just memory configuration.
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SYNQUACER_PLATFORM_PCI_H_
> +#define _SYNQUACER_PLATFORM_PCI_H_
> +
> +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
> +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
> +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
> +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
> +
> +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0
> +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e
> +
> +#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0
> +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff
> +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000
> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000
> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE
> +
> +#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000
> +#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff
> +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000
> +
> +#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000
> +#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff
> +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000
> +
> +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
> +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
> +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
> +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
> +
> +#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0
> +#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e
> +
> +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff
> +#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE
> +
> +#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000
> +#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff
> +#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000
> +
> +#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000
> +#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff
> +#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Synquacer.dec b/Silicon/Socionext/Synquacer/Synquacer.dec
> new file mode 100644
> index 000000000000..955a056a8d59
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Synquacer.dec
> @@ -0,0 +1,22 @@
> +#
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
I think we're at 0x0001001a (1.26) now?
> + PACKAGE_NAME = Synquacer
> + PACKAGE_GUID = 9c782fd2-7db1-438d-b51c-2155cee2c5cc
> + PACKAGE_VERSION = 0.1
> +
> +[Includes]
> + Include
> +
> +
Drop trailing blanks?
/
Leif
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
2017-09-08 18:23 ` [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 13:36 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board Ard Biesheuvel
` (11 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Replace the common MemoryInitPeiLib implementation with one that does
not remove the primary FV from the memory map. This is a waste of
memory and TLB entries, given that the OS can no longer use a 1 GB
block mapping to map this memory.
Since we have our own implementation now, there is no point in using
ArmPlatformLib's GetVirtualMemoryMap() implementation, and we can
simply declare and map the regions directly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c | 140 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf | 50 +++++++
2 files changed, 190 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
new file mode 100644
index 000000000000..1d25d63f1b6c
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
@@ -0,0 +1,140 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmLib.h>
+#include <Library/ArmMmuLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+
+#include <Platform/MemoryMap.h>
+#include <Platform/Pcie.h>
+
+#define ARM_MEMORY_REGION(Base, Size) \
+ { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
+
+#define ARM_DEVICE_REGION(Base, Size) \
+ { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
+ // DDR - 2 GB
+ ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_1_BASE,
+ SYNQUACER_SYSTEM_MEMORY_1_SZ),
+
+ // DDR - 30 GB
+ ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_2_BASE,
+ SYNQUACER_SYSTEM_MEMORY_2_SZ),
+
+ // DDR - 32 GB
+// ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_3_BASE,
+// SYNQUACER_SYSTEM_MEMORY_3_SZ),
+
+ // Synquacer OnChip non-secure ROM
+ ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_ROM_BASE,
+ SYNQUACER_NON_SECURE_ROM_SZ),
+
+ // Synquacer OnChip peripherals
+ ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
+ SYNQUACER_PERIPHERALS_SZ),
+
+ // Synquacer OnChip non-secure SRAM
+ ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
+ SYNQUACER_NON_SECURE_SRAM_SZ),
+
+ // Synquacer GIC-500
+ ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
+ ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE),
+
+ // Synquacer eMMC(SDH30)
+ ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
+
+ // Synquacer EEPROM
+ ARM_DEVICE_REGION (SYNQUACER_EEPROM_BASE, SYNQUACER_EEPROM_BASE_SZ),
+
+ // Synquacer NETSEC
+ ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
+
+ // PCIe control registers
+ ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
+
+ // PCIe config space
+ ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
+ SYNQUACER_PCI_SEG0_CONFIG_SIZE),
+ ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
+ SYNQUACER_PCI_SEG1_CONFIG_SIZE),
+
+ // PCIe I/O space
+ ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
+ SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
+ ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
+ SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
+
+ { }
+};
+
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ RETURN_STATUS Status;
+
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ SYNQUACER_SYSTEM_MEMORY_1_BASE,
+ SYNQUACER_SYSTEM_MEMORY_1_SZ);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ SYNQUACER_SYSTEM_MEMORY_2_BASE,
+ SYNQUACER_SYSTEM_MEMORY_2_SZ);
+
+// BuildResourceDescriptorHob (
+// EFI_RESOURCE_SYSTEM_MEMORY,
+// ResourceAttributes,
+// SYNQUACER_SYSTEM_MEMORY_3_BASE,
+// SYNQUACER_SYSTEM_MEMORY_3_SZ);
+
+ Status = ArmConfigureMmu (mVirtualMemoryTable, NULL, NULL);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ BuildMemoryTypeInformationHob ();
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
new file mode 100644
index 000000000000..5f45c30a5e92
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SynquacerMemoryInitPeiLib
+ FILE_GUID = c69d3ce7-098c-4fcd-afb4-15fb05a39308
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+ SynquacerMemoryInitPeiLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmMmuLib
+ DebugLib
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation
2017-09-08 18:23 ` [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation Ard Biesheuvel
@ 2017-09-11 13:36 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 13:36 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:03PM +0100, Ard Biesheuvel wrote:
> Replace the common MemoryInitPeiLib implementation with one that does
> not remove the primary FV from the memory map. This is a waste of
> memory and TLB entries, given that the OS can no longer use a 1 GB
> block mapping to map this memory.
>
> Since we have our own implementation now, there is no point in using
> ArmPlatformLib's GetVirtualMemoryMap() implementation, and we can
> simply declare and map the regions directly.
Is there any reason we could not extend this to a better core
implementation, kept in ArmPkg?
(No, that does not need to happen now.)
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c | 140 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf | 50 +++++++
> 2 files changed, 190 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> new file mode 100644
> index 000000000000..1d25d63f1b6c
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> @@ -0,0 +1,140 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmMmuLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +
> +#include <Platform/MemoryMap.h>
> +#include <Platform/Pcie.h>
> +
> +#define ARM_MEMORY_REGION(Base, Size) \
> + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
> +
> +#define ARM_DEVICE_REGION(Base, Size) \
> + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> + VOID
> + );
> +
> +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
> + // DDR - 2 GB
> + ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_1_BASE,
> + SYNQUACER_SYSTEM_MEMORY_1_SZ),
> +
> + // DDR - 30 GB
> + ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_2_BASE,
> + SYNQUACER_SYSTEM_MEMORY_2_SZ),
> +
> + // DDR - 32 GB
> +// ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_3_BASE,
> +// SYNQUACER_SYSTEM_MEMORY_3_SZ),
Could these be kept behind a #define (or FixedPcd) until no longer
needed?
> +
> + // Synquacer OnChip non-secure ROM
> + ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_ROM_BASE,
> + SYNQUACER_NON_SECURE_ROM_SZ),
> +
> + // Synquacer OnChip peripherals
> + ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
> + SYNQUACER_PERIPHERALS_SZ),
> +
> + // Synquacer OnChip non-secure SRAM
> + ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
> + SYNQUACER_NON_SECURE_SRAM_SZ),
> +
> + // Synquacer GIC-500
> + ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
> + ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE),
> +
> + // Synquacer eMMC(SDH30)
> + ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
> +
> + // Synquacer EEPROM
> + ARM_DEVICE_REGION (SYNQUACER_EEPROM_BASE, SYNQUACER_EEPROM_BASE_SZ),
> +
> + // Synquacer NETSEC
> + ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
> +
> + // PCIe control registers
> + ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
> +
> + // PCIe config space
> + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
> + SYNQUACER_PCI_SEG0_CONFIG_SIZE),
> + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
> + SYNQUACER_PCI_SEG1_CONFIG_SIZE),
> +
> + // PCIe I/O space
> + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
> + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
> + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
> + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
> +
> + { }
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> + IN UINT64 UefiMemorySize
> + )
> +{
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + RETURN_STATUS Status;
> +
> + ResourceAttributes =
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED;
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + SYNQUACER_SYSTEM_MEMORY_1_BASE,
> + SYNQUACER_SYSTEM_MEMORY_1_SZ);
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + SYNQUACER_SYSTEM_MEMORY_2_BASE,
> + SYNQUACER_SYSTEM_MEMORY_2_SZ);
> +
> +// BuildResourceDescriptorHob (
> +// EFI_RESOURCE_SYSTEM_MEMORY,
> +// ResourceAttributes,
> +// SYNQUACER_SYSTEM_MEMORY_3_BASE,
> +// SYNQUACER_SYSTEM_MEMORY_3_SZ);
Same #define / FixedPcd?
/
Leif
> +
> + Status = ArmConfigureMmu (mVirtualMemoryTable, NULL, NULL);
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
> + // Optional feature that helps prevent EFI memory map fragmentation.
> + BuildMemoryTypeInformationHob ();
> + }
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> new file mode 100644
> index 000000000000..5f45c30a5e92
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> @@ -0,0 +1,50 @@
> +#/** @file
> +#
> +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = SynquacerMemoryInitPeiLib
> + FILE_GUID = c69d3ce7-098c-4fcd-afb4-15fb05a39308
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
> +
> +[Sources]
> + SynquacerMemoryInitPeiLib.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> + ArmLib
> + ArmMmuLib
> + DebugLib
> +
> +[FeaturePcd]
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
2017-09-08 18:23 ` [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers Ard Biesheuvel
2017-09-08 18:23 ` [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 13:54 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs Ard Biesheuvel
` (10 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 394 ++++++++++++++++++++
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 276 ++++++++++++++
Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S | 93 +++++
Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S | 93 +++++
Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c | 124 ++++++
Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf | 39 ++
6 files changed, 1019 insertions(+)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
new file mode 100644
index 000000000000..2a9a0037dcda
--- /dev/null
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -0,0 +1,394 @@
+#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = SynquacerEvalBoard
+ PLATFORM_GUID = a8180daa-fb8b-11e5-ab24-9fc3167c073d
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+
+[BuildOptions]
+ RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
+
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+[LibraryClasses.common]
+ ArmPlatformLib|Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
+ ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ # BDS Libraries
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+ # Add support for GCC stack protector
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.SEC]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+ # UiApp dependencies
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
+
+ # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+ # Ashbrook 12-Cluster profile
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|2
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|12
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ ## PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gArmPlatformTokenSpaceGuid.PL011UartInteger|0
+ gArmPlatformTokenSpaceGuid.PL011UartFractional|0
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|62500000
+
+ #
+ # ARM Generic Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30400000
+
+ #
+ # Generic watchdog
+ #
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
+
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x3f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free (pool)
+ # DEBUG_PAGE 0x00000020 // Alloc & Free (page)
+ # DEBUG_INFO 0x00000040 // Informational debug messages
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNP Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // LoadFile
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
+ # // significantly impact boot performance
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|2000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+ # use the TTY terminal type
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ # GUID of the UI app
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ #
+ # Enable strict image permissions for all images. (This applies
+ # only to images that were built with >= 4 KB section alignment.)
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
+
+ #
+ # Enable NX memory protection for all non-code regions, including OEM and OS
+ # reserved ones, with the exception of LoaderData regions, of which OS loaders
+ # (i.e., GRUB) may assume that its contents are executable.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
+
+ #
+ # Enable the non-executable DXE stack. (This gets set up by DxeIpl)
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsDynamicHii]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePi/PeiUniCore.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+ <LibraryClasses>
+ ## TODO
+ RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+ }
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
+ #
+ # Generic BDS
+ #
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
new file mode 100644
index 000000000000..6c00e16b169e
--- /dev/null
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -0,0 +1,276 @@
+#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL33_AP_UEFI]
+BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0xF0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x000F0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 89cc2ab6-b847-475f-93e2-819603c3d15a
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+ #
+ # UEFI applications
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Generic BDS
+ #
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+#
+# These SEC rules are used for ArmPlatformPkg/PrePi module.
+# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
+# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
+#
+[Rule.ARM.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.AARCH64.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+# A shim specific rule is required to ensure the alignment is 4K.
+# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
+[Rule.ARM.SEC.SHIM]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
new file mode 100644
index 000000000000..7edae77067d0
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
@@ -0,0 +1,93 @@
+/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+PrimaryCoreMpid:
+ .word 0x0
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_PFX(ArmPlatformPeiBootAction):
+ // The trusted firmware passes the primary CPU MPID through x0 register.
+ // Save it in a variable.
+ adr x1, PrimaryCoreMpid
+ str w0, [x1]
+ ret
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns the core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #7
+ ret
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr w0, PrimaryCoreMpid
+ ret
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// The primary core is the core responsible to initialize the hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ mov w0, #1
+ ret
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
new file mode 100644
index 000000000000..b37b461b77a5
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
@@ -0,0 +1,93 @@
+/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+PrimaryCoreMpid:
+ .word 0x0
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_PFX(ArmPlatformPeiBootAction):
+ // The trusted firmware passes the primary CPU MPID through r0 register.
+ // Save it in a variable.
+ adr r1, PrimaryCoreMpid
+ str r0, [r1]
+ bx lr
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns the core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and r1, r0, #ARM_CORE_MASK
+ and r0, r0, #ARM_CLUSTER_MASK
+ add r0, r1, r0, LSR #7
+ bx lr
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr r0, PrimaryCoreMpid
+ bx lr
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// The primary core is the core responsible to initialize the hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ mov r0, #1
+ bx lr
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
new file mode 100644
index 000000000000..014db60add8e
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
@@ -0,0 +1,124 @@
+/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+STATIC ARM_CORE_INFO mSynquacerInfoTable[] = {
+ { 0x0, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 0
+ { 0x0, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 1
+ { 0x1, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 0
+ { 0x1, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 1
+ { 0x2, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 0
+ { 0x2, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 1
+ { 0x3, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 0
+ { 0x3, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 1
+ { 0x4, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 0
+ { 0x4, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 1
+ { 0x5, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 0
+ { 0x5, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 1
+ { 0x6, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 0
+ { 0x6, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 1
+ { 0x7, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 0
+ { 0x7, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 1
+ { 0x8, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 0
+ { 0x8, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 1
+ { 0x9, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 0
+ { 0x9, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 1
+ { 0xa, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 0
+ { 0xa, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 1
+ { 0xb, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 0
+ { 0xb, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 1
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+}
+
+STATIC
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = ARRAY_SIZE (mSynquacerInfoTable);
+ *ArmCoreTable = mSynquacerInfoTable;
+
+ return EFI_SUCCESS;
+}
+
+STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = {
+ PrePeiCoreGetMpCoreInfo
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof mPlatformPpiTable;
+ *PpiList = mPlatformPpiTable;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
new file mode 100644
index 000000000000..63c3c8d35e21
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
@@ -0,0 +1,39 @@
+#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SynquacerLib
+ FILE_GUID = 8301a0ab-dd8d-476d-8170-1e34b51490d3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+
+[Sources.common]
+ Synquacer.c
+
+[Sources.AARCH64]
+ AArch64/SynquacerHelper.S | GCC
+
+[Sources.ARM]
+ Arm/SynquacerHelper.S | GCC
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board
2017-09-08 18:23 ` [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board Ard Biesheuvel
@ 2017-09-11 13:54 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 13:54 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:04PM +0100, Ard Biesheuvel wrote:
> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
> code provided by Socionext. It can boot into the UiApp menu screen
> or the UEFI Shell, but lacks support for any peripherals.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 394 ++++++++++++++++++++
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 276 ++++++++++++++
> Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S | 93 +++++
> Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S | 93 +++++
Oh - is the platform usable in AArch32 as well? Neat.
> Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c | 124 ++++++
> Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf | 39 ++
> 6 files changed, 1019 insertions(+)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> new file mode 100644
> index 000000000000..2a9a0037dcda
> --- /dev/null
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -0,0 +1,394 @@
> +#
> +# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Linaro Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + PLATFORM_NAME = SynquacerEvalBoard
> + PLATFORM_GUID = a8180daa-fb8b-11e5-ab24-9fc3167c073d
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
Bump the version a bit.
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> + FLASH_DEFINITION = Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +
> +[BuildOptions]
> + RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
> +
> +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
> + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
> + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> +
> + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> +
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!else
> + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> +!endif
> + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> +
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> +
> + # Networking Requirements
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> +
> + # ARM Architectural Libraries
> + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> +
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> + # BDS Libraries
> + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +
> + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
> + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> + PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
> +
> + #
> + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> + # This library provides the instrinsic functions generate by a given compiler.
> + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
This is actually under [.common], though.
> + #
> + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> + # Add support for GCC stack protector
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> +
> +[LibraryClasses.common.SEC]
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> + MemoryInitPeiLib|Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> + # UiApp dependencies
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag]
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> +
> +[PcdsFixedAtBuild.common]
> + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
> +
> + # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +
> + # Ashbrook 12-Cluster profile
I know what that means, but may make more sense to others as
# 12x 2-core processor clusters.
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|2
> + gArmPlatformTokenSpaceGuid.PcdClusterCount|12
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
For internal use only on ARM?
> +
> + ## PL011 - Serial Terminal
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> + gArmPlatformTokenSpaceGuid.PL011UartInteger|0
> + gArmPlatformTokenSpaceGuid.PL011UartFractional|0
> + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|62500000
> +
> + #
> + # ARM Generic Interrupt Controller
> + #
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30400000
> +
> + #
> + # Generic watchdog
> + #
> + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
> + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
> +
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> + # DEBUG_ASSERT_ENABLED 0x01
> + # DEBUG_PRINT_ENABLED 0x02
> + # DEBUG_CODE_ENABLED 0x04
> + # CLEAR_MEMORY_ENABLED 0x08
> + # ASSERT_BREAKPOINT_ENABLED 0x10
> + # ASSERT_DEADLOOP_ENABLED 0x20
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x3f
> +!endif
> +
> + # DEBUG_INIT 0x00000001 // Initialization
> + # DEBUG_WARN 0x00000002 // Warnings
> + # DEBUG_LOAD 0x00000004 // Load events
> + # DEBUG_FS 0x00000008 // EFI File system
> + # DEBUG_POOL 0x00000010 // Alloc & Free (pool)
> + # DEBUG_PAGE 0x00000020 // Alloc & Free (page)
> + # DEBUG_INFO 0x00000040 // Informational debug messages
> + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
> + # DEBUG_VARIABLE 0x00000100 // Variable
> + # DEBUG_BM 0x00000400 // Boot Manager
> + # DEBUG_BLKIO 0x00001000 // BlkIo Driver
> + # DEBUG_NET 0x00004000 // SNP Driver
> + # DEBUG_UNDI 0x00010000 // UNDI Driver
> + # DEBUG_LOADFILE 0x00020000 // LoadFile
> + # DEBUG_EVENT 0x00080000 // Event messages
> + # DEBUG_GCD 0x00100000 // Global Coherency Database changes
> + # DEBUG_CACHE 0x00200000 // Memory range cachability changes
> + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
> + # // significantly impact boot performance
> + # DEBUG_ERROR 0x80000000 // Error
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
> +
> + #
> + # Optional feature to help prevent EFI memory map fragments
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> + # Values are in EFI Pages (4K). DXE Core will make sure that
> + # at least this much of each type of memory can be allocated
> + # from a single memory range. This way you only end up with
> + # maximum of two fragements for each type in the memory map
> + # (the memory used, and the free memory that was prereserved
> + # but not used).
> + #
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|2000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
Are these actually used by your reimplemented MemoryInitPeiLib?
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> +
> + # use the TTY terminal type
> + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> + # GUID of the UI app
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> +
> + #
> + # Enable strict image permissions for all images. (This applies
> + # only to images that were built with >= 4 KB section alignment.)
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
> +
> + #
> + # Enable NX memory protection for all non-code regions, including OEM and OS
> + # reserved ones, with the exception of LoaderData regions, of which OS loaders
> + # (i.e., GRUB) may assume that its contents are executable.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
> +
> + #
> + # Enable the non-executable DXE stack. (This gets set up by DxeIpl)
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
> +
> +[PcdsDynamicHii]
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # PEI Phase modules
> + #
> + ArmPlatformPkg/PrePi/PeiUniCore.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # DXE
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> + }
> +
> + #
> + # Architectural Protocols
> + #
> + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
> + <LibraryClasses>
> + ## TODO
> + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
> + }
> + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
Actually, could you leave out the TFTP command?
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + }
> +
> + #
> + # Generic BDS
> + #
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + MdeModulePkg/Application/UiApp/UiApp.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> + }
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> new file mode 100644
> index 000000000000..6c00e16b169e
> --- /dev/null
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -0,0 +1,276 @@
> +#
> +# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Linaro Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.BL33_AP_UEFI]
> +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
> +Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +
> +# This one is tricky, it must be: BlockSize * NumBlocks = Size
> +BlockSize = 0x00001000
> +NumBlocks = 0xF0
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +
> +0x00000000|0x000F0000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 89cc2ab6-b847-475f-93e2-819603c3d15a
> +BlockSize = 0x40
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +
> + #
> + # UEFI applications
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Generic BDS
> + #
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> +
> +
> +################################################################################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the default
> +# rules for the different module type. User can add the customized rules to define the
> +# content of the FFS file.
> +#
> +################################################################################
> +
> +
> +############################################################################
> +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
> +############################################################################
> +#
> +#[Rule.Common.DXE_DRIVER]
> +# FILE DRIVER = $(NAMED_GUID) {
> +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +# COMPRESS PI_STD {
> +# GUIDED {
> +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> +# UI STRING="$(MODULE_NAME)" Optional
> +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +# }
> +# }
> +# }
> +#
> +############################################################################
> +
> +#
> +# These SEC rules are used for ArmPlatformPkg/PrePi module.
> +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
> +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
> +#
> +[Rule.ARM.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.AARCH64.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +# A shim specific rule is required to ensure the alignment is 4K.
> +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
> +[Rule.ARM.SEC.SHIM]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING ="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + UI STRING ="$(MODULE_NAME)" Optional
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
> new file mode 100644
> index 000000000000..7edae77067d0
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
> @@ -0,0 +1,93 @@
> +/** @file
> +*
> +* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +
> +PrimaryCoreMpid:
> + .word 0x0
> +
> +//
> +// First platform specific function to be called in the PEI phase
> +//
> +// This function is actually the first function called by the PrePi
> +// or PrePeiCore modules. It allows to retrieve arguments passed to
> +// the UEFI firmware through the CPU registers.
> +//
> +ASM_PFX(ArmPlatformPeiBootAction):
> + // The trusted firmware passes the primary CPU MPID through x0 register.
> + // Save it in a variable.
> + adr x1, PrimaryCoreMpid
> + str w0, [x1]
> + ret
> +
> +//
> +// Return the core position from the value of its MpId register
> +//
> +// This function returns the core position from the position 0 in the processor.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the core position
> +//
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 2) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #7
> + ret
> +
> +//
> +// Return the MpId of the primary core
> +//
> +// This function returns the MpId of the primary core.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the MpId of the primary core
> +//
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> + ldr w0, PrimaryCoreMpid
> + ret
> +
> +//
> +// Return a non-zero value if the callee is the primary core
> +//
> +// This function returns a non-zero value if the callee is the primary core.
> +// The primary core is the core responsible to initialize the hardware and run UEFI.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return a non-zero value if the callee is the primary core.
> +//
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> + mov w0, #1
> + ret
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
> new file mode 100644
> index 000000000000..b37b461b77a5
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
> @@ -0,0 +1,93 @@
> +/** @file
> +*
> +* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +
> +PrimaryCoreMpid:
> + .word 0x0
> +
> +//
> +// First platform specific function to be called in the PEI phase
> +//
> +// This function is actually the first function called by the PrePi
> +// or PrePeiCore modules. It allows to retrieve arguments passed to
> +// the UEFI firmware through the CPU registers.
> +//
> +ASM_PFX(ArmPlatformPeiBootAction):
> + // The trusted firmware passes the primary CPU MPID through r0 register.
> + // Save it in a variable.
> + adr r1, PrimaryCoreMpid
> + str r0, [r1]
> + bx lr
> +
> +//
> +// Return the core position from the value of its MpId register
> +//
> +// This function returns the core position from the position 0 in the processor.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the core position
> +//
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 2) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> + and r1, r0, #ARM_CORE_MASK
> + and r0, r0, #ARM_CLUSTER_MASK
> + add r0, r1, r0, LSR #7
> + bx lr
> +
> +//
> +// Return the MpId of the primary core
> +//
> +// This function returns the MpId of the primary core.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return the MpId of the primary core
> +//
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> + ldr r0, PrimaryCoreMpid
> + bx lr
> +
> +//
> +// Return a non-zero value if the callee is the primary core
> +//
> +// This function returns a non-zero value if the callee is the primary core.
> +// The primary core is the core responsible to initialize the hardware and run UEFI.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return Return a non-zero value if the callee is the primary core.
> +//
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> + mov r0, #1
> + bx lr
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
> new file mode 100644
> index 000000000000..014db60add8e
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
> @@ -0,0 +1,124 @@
> +/** @file
> +*
> +* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +STATIC ARM_CORE_INFO mSynquacerInfoTable[] = {
> + { 0x0, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 0
> + { 0x0, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 1
> + { 0x1, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 0
> + { 0x1, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 1
> + { 0x2, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 0
> + { 0x2, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 1
> + { 0x3, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 0
> + { 0x3, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 1
> + { 0x4, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 0
> + { 0x4, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 1
> + { 0x5, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 0
> + { 0x5, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 1
> + { 0x6, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 0
> + { 0x6, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 1
> + { 0x7, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 0
> + { 0x7, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 1
> + { 0x8, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 0
> + { 0x8, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 1
> + { 0x9, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 0
> + { 0x9, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 1
> + { 0xa, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 0
> + { 0xa, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 1
> + { 0xb, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 0
> + { 0xb, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 1
> +};
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> + @return Return the current Boot Mode of the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Initialize controllers that must setup in the normal world
> +
> + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> + in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Initialize the system (or sometimes called permanent) memory
> +
> + This memory is generally represented by the DRAM.
> +
> +**/
> +VOID
> +ArmPlatformInitializeSystemMemory (
> + VOID
> + )
> +{
> +}
> +
> +STATIC
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = ARRAY_SIZE (mSynquacerInfoTable);
> + *ArmCoreTable = mSynquacerInfoTable;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = {
> + PrePeiCoreGetMpCoreInfo
> +};
> +
> +STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof mPlatformPpiTable;
> + *PpiList = mPlatformPpiTable;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> new file mode 100644
> index 000000000000..63c3c8d35e21
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> @@ -0,0 +1,39 @@
> +#
> +# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
So, there are a bunch of files in a row here all with the same
ARM-only Copyright statement - is this all accurate?
/
Leif
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = SynquacerLib
> + FILE_GUID = 8301a0ab-dd8d-476d-8170-1e34b51490d3
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> +
> +[Sources.common]
> + Synquacer.c
> +
> +[Sources.AARCH64]
> + AArch64/SynquacerHelper.S | GCC
> +
> +[Sources.ARM]
> + Arm/SynquacerHelper.S | GCC
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (2 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 14:03 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support Ard Biesheuvel
` (9 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).
This also allows us to implement the Synopsys Designware PCIe specific
workaround for PCI config space accesses to devices 1 and up on bus 0.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c | 1396 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf | 35 +
2 files changed, 1431 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
new file mode 100644
index 000000000000..a9b57883b6cf
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1396 @@
+/** @file
+ PCI Segment Library for Synquacer SoC with multiple RCs
+
+ Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+#include <Platform/Pcie.h>
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+ switch ((UINT16)(Address >> 32)) {
+ case 0:
+ return SYNQUACER_PCI_SEG0_CONFIG_BASE;
+ case 1:
+ return SYNQUACER_PCI_SEG1_CONFIG_BASE;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+
+ // ignore devices > 0 on bus 0
+ if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
+ return 0xffffffff;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + (UINT32)Address);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + (UINT32)Address);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + (UINT32)Address);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param Width The width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+
+ // ignore devices > 0 on bus 0
+ if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
+ return Data;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + (UINT32)Address, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is bit 0.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param AndData The value to AND with the read value from the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
new file mode 100644
index 000000000000..e5f3ac494b32
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCI Segment Library for Synquacer SoC with multiple RCs
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SynquacerPciSegmentLib
+ FILE_GUID = 1299f005-a30b-47d3-9003-24a91f100840
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs
2017-09-08 18:23 ` [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs Ard Biesheuvel
@ 2017-09-11 14:03 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 14:03 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:05PM +0100, Ard Biesheuvel wrote:
> Having two distinct root complexes is not supported by the standard
> set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
> of the latter specifically for this platform (and forget about the
> others).
>
> This also allows us to implement the Synopsys Designware PCIe specific
> workaround for PCI config space accesses to devices 1 and up on bus 0.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c | 1396 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf | 35 +
> 2 files changed, 1431 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 000000000000..a9b57883b6cf
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,1396 @@
> +/** @file
> + PCI Segment Library for Synquacer SoC with multiple RCs
> +
> + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
This does not look unmodified to me.
(I don't really have any comments on the below.)
/
Leif
> + This program and the accompanying materials are
> + licensed and made available under the terms and conditions of
> + the BSD License which accompanies this distribution. The full
> + text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +
> +#include <Platform/Pcie.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +STATIC
> +UINT64
> +PciSegmentLibGetConfigBase (
> + IN UINT64 Address
> + )
> +{
> + switch ((UINT16)(Address >> 32)) {
> + case 0:
> + return SYNQUACER_PCI_SEG0_CONFIG_BASE;
> + case 1:
> + return SYNQUACER_PCI_SEG1_CONFIG_BASE;
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINT64 Base;
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + // ignore devices > 0 on bus 0
> + if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
> + return 0xffffffff;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (Base + (UINT32)Address);
> + case PciCfgWidthUint16:
> + return MmioRead16 (Base + (UINT32)Address);
> + case PciCfgWidthUint32:
> + return MmioRead32 (Base + (UINT32)Address);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + Internal worker function to writes a PCI configuration register.
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT64 Base;
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + // ignore devices > 0 on bus 0
> + if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
> + return Data;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + MmioWrite8 (Base + (UINT32)Address, Data);
> + break;
> + case PciCfgWidthUint16:
> + MmioWrite16 (Base + (UINT32)Address, Data);
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 (Base + (UINT32)Address, Data);
> + break;
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Register a PCI device so PCI configuration registers may be accessed after
> + SetVirtualAddressMap().
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
> + after ExitBootServices().
> + @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> + at runtime could not be mapped.
> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> + complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciSegmentRegisterForRuntimeAccess (
> + IN UINTN Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> + return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentOr8 (
> + IN UINT64 Address,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAnd8 (
> + IN UINT64 Address,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
> + followed a bitwise OR with another 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 8-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAndThenOr8 (
> + IN UINT64 Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldRead8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 8-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldWrite8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 Value
> + )
> +{
> + return PciSegmentWrite8 (
> + Address,
> + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
> + );
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (
> + Address,
> + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
> + );
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 8-bit register.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAnd8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData
> + )
> +{
> + return PciSegmentWrite8 (
> + Address,
> + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
> + );
> +}
> +
> +/**
> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAndThenOr8 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return PciSegmentWrite8 (
> + Address,
> + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
> + );
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function and
> + Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentOr16 (
> + IN UINT64 Address,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAnd16 (
> + IN UINT64 Address,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
> + followed a bitwise OR with another 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAndThenOr16 (
> + IN UINT64 Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldRead16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 16-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldWrite16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 Value
> + )
> +{
> + return PciSegmentWrite16 (
> + Address,
> + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
> + );
> +}
> +
> +/**
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (
> + Address,
> + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
> + );
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
> + and writes the result back to the bit field in the 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 16-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> + Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + The ordinal of the least significant bit in a byte is bit 0.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + The ordinal of the most significant bit in a byte is bit 7.
> + @param AndData The value to AND with the read value from the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAnd16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData
> + )
> +{
> + return PciSegmentWrite16 (
> + Address,
> + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
> + );
> +}
> +
> +/**
> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAndThenOr16 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + return PciSegmentWrite16 (
> + Address,
> + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
> + );
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise OR between the read result and the value specified by OrData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentOr32 (
> + IN UINT64 Address,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAnd32 (
> + IN UINT64 Address,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
> + followed a bitwise OR with another 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address,
> + performs a bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> + and writes the result to the 32-bit PCI configuration register specified by Address.
> + The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAndThenOr32 (
> + IN UINT64 Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address The PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldRead32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 32-bit register is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param Value The new value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldWrite32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 Value
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
> + );
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
> + );
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 32-bit register.
> +
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
> + AND between the read result and the value specified by AndData, and writes the result
> + to the 32-bit PCI configuration register specified by Address. The value written to
> + the PCI configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in AndData are stripped.
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAnd32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
> + );
> +}
> +
> +/**
> + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 32-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> + @param Address The PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAndThenOr32 (
> + IN UINT64 Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + return PciSegmentWrite32 (
> + Address,
> + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
> + );
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned. When possible 32-bit PCI configuration read cycles are used to read
> + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> + and 16-bit PCI configuration read cycles may be used at the beginning and the
> + end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Read a byte if StartAddress is byte aligned
> + //
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Read a word if StartAddress is word aligned
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Read as many double words as possible
> + //
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Read the last remaining word if exist
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Read the last remaining byte if exist
> + //
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + }
> +
> + return ReturnValue;
> +}
> +
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned. When possible 32-bit PCI configuration write cycles are used to
> + write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> + and the end of the range.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> + if (Size == 0) {
> + return 0;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Write a byte if StartAddress is byte aligned
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Write a word if StartAddress is word aligned
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Write as many double words as possible
> + //
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Write the last remaining word if exist
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + 1;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Write the last remaining byte if exist
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> new file mode 100644
> index 000000000000..e5f3ac494b32
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> @@ -0,0 +1,35 @@
> +## @file
> +# PCI Segment Library for Synquacer SoC with multiple RCs
> +#
> +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = SynquacerPciSegmentLib
> + FILE_GUID = 1299f005-a30b-47d3-9003-24a91f100840
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (3 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 14:22 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL Ard Biesheuvel
` (8 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c | 223 ++++++++++++
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf | 50 +++
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c | 383 ++++++++++++++++++++
3 files changed, 656 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
new file mode 100644
index 000000000000..10ddaac3b924
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
@@ -0,0 +1,223 @@
+/** @file
+ PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Platform/Pcie.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08), // PCI Express
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08), // PCI Express
+ 1
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = {
+ {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes
+ { SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+ SYNQUACER_PCI_SEG0_BUSNUM_MAX }, // Bus
+ { SYNQUACER_PCI_SEG0_PORTIO_MIN,
+ SYNQUACER_PCI_SEG0_PORTIO_MAX }, // Io
+ { SYNQUACER_PCI_SEG0_MMIO32_MIN,
+ SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem
+ { SYNQUACER_PCI_SEG0_MMIO64_MIN,
+ SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+ }, {
+ 1, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes
+ { SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+ SYNQUACER_PCI_SEG1_BUSNUM_MAX }, // Bus
+ { SYNQUACER_PCI_SEG1_PORTIO_MIN,
+ SYNQUACER_PCI_SEG1_PORTIO_MAX }, // Io
+ { SYNQUACER_PCI_SEG1_MMIO32_MIN,
+ SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem
+ { SYNQUACER_PCI_SEG1_MMIO64_MIN,
+ SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+ }
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ *Count = ARRAY_SIZE (mPciRootBridges);
+
+ return mPciRootBridges;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
new file mode 100644
index 000000000000..cfa9b2fc1c07
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
@@ -0,0 +1,50 @@
+## @file
+# PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SynquacerPciHostBridgeLib
+ FILE_GUID = fdc92446-65bc-4f86-b4a0-014a2119a732
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+ CONSTRUCTOR = SynquacerPciHostBridgeLibConstructor
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ SynquacerPciHostBridgeLib.c
+ SynquacerPciHostBridgeLibConstructor.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciIoTranslation
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
new file mode 100644
index 000000000000..b3acca32070f
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
@@ -0,0 +1,383 @@
+/** @file
+ PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Platform/Pcie.h>
+
+#define IATU_VIEWPORT_OFF 0x900
+#define IATU_VIEWPORT_INBOUND BIT31
+#define IATU_VIEWPORT_OUTBOUND 0
+#define IATU_VIEWPORT_REGION_INDEX(Idx) ((Idx) & 7)
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
+
+#define CORE_CONTROL 0x000
+#define APP_LTSSM_ENABLE BIT4
+#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define AXI_CLK_STOP 0x004
+#define DBI_ACLK_STOP BIT8
+#define SLV_ACLK_STOP BIT4
+#define MSTR_ACLK_STOP BIT0
+#define DBI_CSYSREQ_REG BIT9
+#define SLV_CSYSREQ_REG BIT5
+#define MSTR_CSYSREQ_REG BIT1
+
+#define RESET_CONTROL_1 0x00C
+#define PERST_N_O_REG BIT5
+#define PERST_N_I_REG BIT4
+#define BUTTON_RST_N_REG BIT1
+#define PWUP_RST_N_REG BIT0
+
+#define RESET_CONTROL_2 0x010
+
+#define RESET_SELECT_1 0x014
+#define SQU_RST_SEL BIT29
+#define PHY_RST_SEL BIT28
+#define PWR_RST_SEL BIT24
+#define STI_RST_SEL BIT20
+#define N_STI_RST_SEL BIT16
+#define CORE_RST_SEL BIT12
+#define PERST_SEL BIT4
+#define BUTTON_RST_SEL BIT1
+#define PWUP_RST_SEL BIT0
+
+#define RESET_SELECT_2 0x018
+#define DBI_ARST_SEL BIT8
+#define SLV_ARST_SEL BIT4
+#define MSTR_ARST_SEL BIT0
+
+#define EM_CONTROL 0x030
+#define PRE_DET_STT_REG BIT4
+
+#define EM_SELECT 0x034
+#define PRE_DET_STT_SEL BIT4
+
+#define PM_CONTROL_2 0x050
+#define SYS_AUX_PWR_DET BIT8
+
+#define PHY_CONFIG_COM_6 0x114
+#define PIPE_PORT_SEL (BIT1 | BIT0)
+
+#define LINK_MONITOR 0x210
+#define SMLH_LINK_UP BIT0
+
+#define LINK_CAPABILITIES_REG 0x07C
+#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4)
+#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define LINK_CONTROL_LINK_STATUS_REG 0x080
+#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20)
+#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16)
+
+#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
+#define BASE_CLASS_CODE 0xFF000000
+#define BASE_CLASS_CODE_VALUE 0x06
+#define SUBCLASS_CODE 0x00FF0000
+#define SUBCLASS_CODE_VALUE 0x04
+#define PROGRAM_INTERFACE 0x0000FF00
+#define PROGRAM_INTERFACE_VALUE 0x00
+
+#define MISC_CONTROL_1_OFF 0x8BC
+#define DBI_RO_WR_EN BIT0
+
+STATIC
+VOID
+ConfigureWindow (
+ IN EFI_PHYSICAL_ADDRESS DbiBase,
+ IN UINTN Index,
+ IN UINT64 CpuBase,
+ IN UINT64 PciBase,
+ IN UINT64 Size,
+ IN UINTN Type,
+ IN UINTN EnableFlags
+ )
+{
+ ArmDataMemoryBarrier ();
+
+ MmioWrite32 (DbiBase + IATU_VIEWPORT_OFF,
+ IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
+
+ ArmDataMemoryBarrier ();
+
+ MmioWrite32 (DbiBase + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(CpuBase & 0xFFFFFFFF));
+ MmioWrite32 (DbiBase + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(CpuBase >> 32));
+ MmioWrite32 (DbiBase + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(CpuBase + Size - 1));
+ MmioWrite32 (DbiBase + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(PciBase & 0xFFFFFFFF));
+ MmioWrite32 (DbiBase + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(PciBase >> 32));
+ MmioWrite32 (DbiBase + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
+ Type);
+ MmioWrite32 (DbiBase + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);
+}
+
+STATIC
+VOID
+SnPcieSetData (
+ EFI_PHYSICAL_ADDRESS Base,
+ UINT32 Offset,
+ UINT32 Mask,
+ UINT32 In
+ )
+{
+ UINT32 Data;
+ UINT32 Shift;
+
+ Shift = 1;
+ if (In) {
+ while (!(Mask & Shift))
+ Shift <<= 1;
+ Data = (MmioRead32 (Base + Offset) & ~Mask) | (In * Shift);
+ } else {
+ Data = MmioRead32 (Base + Offset) & ~Mask;
+ }
+
+ MmioWrite32 (Base + Offset, Data);
+}
+
+STATIC
+UINT32
+SnPcieReadData (
+ EFI_PHYSICAL_ADDRESS Base,
+ UINT32 Offset,
+ UINT32 Mask
+ )
+{
+ UINT32 Shift;
+
+ Shift = 0;
+ while (!(Mask & 1)) {
+ Mask >>= 1;
+ Shift++;
+ }
+
+ return (MmioRead32 (Base + Offset) >> Shift) & Mask;
+}
+
+STATIC
+VOID
+SnDbiRoWrEn (
+ IN EFI_PHYSICAL_ADDRESS DbiBase,
+ IN INTN MaxLinkWidth,
+ IN INTN MaxLinkSpeed
+ )
+{
+ SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
+
+ SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_WIDTH, MaxLinkWidth);
+ SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_SPEED, MaxLinkSpeed);
+
+ SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
+ SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
+ SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
+
+ SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
+}
+
+STATIC
+VOID
+PciInitController (
+ IN EFI_PHYSICAL_ADDRESS ExsBase,
+ IN EFI_PHYSICAL_ADDRESS DbiBase,
+ IN EFI_PHYSICAL_ADDRESS ConfigBase,
+ IN CONST PCI_ROOT_BRIDGE *RootBridge
+ )
+{
+ SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0);
+ SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 0);
+ SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 1);
+
+ // 1: Assert all PHY / LINK resets
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , PERST_SEL , 0);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG , 0);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG , 0);
+
+ // Device Reset(PERST#) is effective afrer Set device_type (RC)
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , PWUP_RST_SEL , 0);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , BUTTON_RST_SEL , 0);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , PWR_RST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_2 , MSTR_ARST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_2 , SLV_ARST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_2 , DBI_ARST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , CORE_RST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , STI_RST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , N_STI_RST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , SQU_RST_SEL , 1);
+ SnPcieSetData (ExsBase, RESET_SELECT_1 , PHY_RST_SEL , 1);
+
+ // 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup.
+ SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
+
+ // 3: Set device_type (RC)
+ SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4);
+
+ // 4: Set Bifurcation 1=disable 4=able
+ // 5: Supply Reference (It has executed)
+ // 6: Wait for 10usec (Reference Clocks is stable)
+ // 7 De assert PERST# */
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG, 1);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG, 1);
+
+ // 8 Assert SYS_AUX_PWR_DET
+ SnPcieSetData(ExsBase, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
+
+ // 9 Supply following clocks
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
+ SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
+
+ // 10 De assert PHY reset
+ // 11 De assert LINK's PMC reset
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
+ SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
+ // 12 PHY auto
+ // 13 Wrapper auto
+ // 14-17 PHY auto
+ // 18 Wrapper auto
+ // 19 Update registers through DBI AXI Slave interface
+ SnDbiRoWrEn (DbiBase, 4 /* lanes */, /* Gen */ 2);
+
+ //
+ // ECAM shift mode uses bits [27:12] of the untranslated address as
+ // B/D/F identifiers. This only works as expected if the base of the
+ // region is aligned to 256 MB, or the effective bus numbers will be
+ // out of sync with the bus base and limit values we chose.
+ //
+ ASSERT ((ConfigBase % SIZE_256MB) == RootBridge->Bus.Base * SIZE_1MB);
+
+ MmioOr32 (DbiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE |
+ EFI_PCI_COMMAND_MEMORY_SPACE |
+ EFI_PCI_COMMAND_BUS_MASTER);
+
+ // Region 0: MMIO32 range
+ ConfigureWindow (DbiBase, 0,
+ RootBridge->Mem.Base,
+ RootBridge->Mem.Base,
+ RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+ 0);
+
+ // Region 1: Type 0 config space
+ ConfigureWindow (DbiBase, 1,
+ ConfigBase + RootBridge->Bus.Base * SIZE_1MB,
+ 0x0,
+ SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ // Region 2: Type 1 config space
+ ConfigureWindow (DbiBase, 2,
+ ConfigBase + RootBridge->Bus.Base * SIZE_1MB + SIZE_64KB,
+ 0x0,
+ (RootBridge->Bus.Limit - RootBridge->Bus.Base + 1) * SIZE_1MB - SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ // Region 3: port I/O range
+ ConfigureWindow (DbiBase, 3,
+ FixedPcdGet32 (PcdPciIoTranslation) + RootBridge->Io.Base,
+ RootBridge->Io.Base,
+ RootBridge->Io.Limit - RootBridge->Io.Base + 1,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+ 0);
+
+ // Region 4: MMIO64 range
+ ConfigureWindow (DbiBase, 4,
+ RootBridge->MemAbove4G.Base,
+ RootBridge->MemAbove4G.Base,
+ RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+ 0);
+
+ // enable link
+ if (SnPcieReadData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) {
+ SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
+ }
+}
+
+STATIC CONST struct {
+ EFI_PHYSICAL_ADDRESS DbiBase;
+ EFI_PHYSICAL_ADDRESS ExsBase;
+ EFI_PHYSICAL_ADDRESS ConfigBase;
+} mBaseAddresses [] = {
+ {
+ SYNQUACER_PCI_SEG0_DBI_BASE,
+ SYNQUACER_PCI_SEG0_EXS_BASE,
+ SYNQUACER_PCI_SEG0_CONFIG_BASE
+ },
+ {
+ SYNQUACER_PCI_SEG1_DBI_BASE,
+ SYNQUACER_PCI_SEG1_EXS_BASE,
+ SYNQUACER_PCI_SEG1_CONFIG_BASE
+ },
+};
+
+
+EFI_STATUS
+EFIAPI
+SynquacerPciHostBridgeLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ PCI_ROOT_BRIDGE *RootBridges;
+ UINTN Count;
+ UINTN Idx;
+
+ RootBridges = PciHostBridgeGetRootBridges (&Count);
+ ASSERT (Count == ARRAY_SIZE(mBaseAddresses));
+ if (Count != ARRAY_SIZE(mBaseAddresses)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ for (Idx = 0; Idx < Count; Idx++) {
+ PciInitController (mBaseAddresses[Idx].ExsBase,
+ mBaseAddresses[Idx].DbiBase,
+ mBaseAddresses[Idx].ConfigBase,
+ &RootBridges[Idx]);
+ }
+
+ return EFI_SUCCESS;
+}
+
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support
2017-09-08 18:23 ` [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support Ard Biesheuvel
@ 2017-09-11 14:22 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 14:22 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:06PM +0100, Ard Biesheuvel wrote:
> Implement the glue library that exposes the PCIe root complexes to
> the generic PCI host bridge driver. Since that driver is the first
> one to access the PCI config space, put the low level init code for
> the RCs into this library's constructor.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c | 223 ++++++++++++
> Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf | 50 +++
> Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c | 383 ++++++++++++++++++++
> 3 files changed, 656 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
> new file mode 100644
> index 000000000000..10ddaac3b924
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
> @@ -0,0 +1,223 @@
> +/** @file
> + PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Platform/Pcie.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
The above is well enough sorted that I'd let it slip, but it isn't
flawless.
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
Shift the spaces after (UINT8) to after sizeof?
> + }
> + },
> + EISA_PNP_ID(0x0A08), // PCI Express
Space before (?
Why don't we have that 0x0a08 in a central header?
> + 0
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
Shift the spaces after (UINT8) to after sizeof?
> + }
> + },
> + EISA_PNP_ID(0x0A08), // PCI Express
Same as above.
> + 1
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = {
> + {
> + 0, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes
> + { SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> + SYNQUACER_PCI_SEG0_BUSNUM_MAX }, // Bus
> + { SYNQUACER_PCI_SEG0_PORTIO_MIN,
> + SYNQUACER_PCI_SEG0_PORTIO_MAX }, // Io
> + { SYNQUACER_PCI_SEG0_MMIO32_MIN,
> + SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem
> + { SYNQUACER_PCI_SEG0_MMIO64_MIN,
> + SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> + }, {
> + 1, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, // AllocationAttributes
> + { SYNQUACER_PCI_SEG1_BUSNUM_MIN,
> + SYNQUACER_PCI_SEG1_BUSNUM_MAX }, // Bus
> + { SYNQUACER_PCI_SEG1_PORTIO_MIN,
> + SYNQUACER_PCI_SEG1_PORTIO_MAX }, // Io
> + { SYNQUACER_PCI_SEG1_MMIO32_MIN,
> + SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem
> + { SYNQUACER_PCI_SEG1_MMIO64_MIN,
> + SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> + }
> +};
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> + The array should be passed into PciHostBridgeFreeRootBridges()
> + when it's not used.
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + *Count = ARRAY_SIZE (mPciRootBridges);
> +
> + return mPciRootBridges;
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
> + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
> + )
> + );
Replace with ARRAY_SIZE?
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> new file mode 100644
> index 000000000000..cfa9b2fc1c07
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +#
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = SynquacerPciHostBridgeLib
> + FILE_GUID = fdc92446-65bc-4f86-b4a0-014a2119a732
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
> + CONSTRUCTOR = SynquacerPciHostBridgeLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the build
> +# tools.
> +#
> +# VALID_ARCHITECTURES = AARCH64
Do we only have AArch64 support for this specific component?
> +#
> +
> +[Sources]
> + SynquacerPciHostBridgeLib.c
> + SynquacerPciHostBridgeLibConstructor.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> + ArmLib
> + DebugLib
> + DevicePathLib
> + MemoryAllocationLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdPciIoTranslation
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
> new file mode 100644
> index 000000000000..b3acca32070f
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
> @@ -0,0 +1,383 @@
> +/** @file
> + PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/ArmLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Platform/Pcie.h>
> +
> +#define IATU_VIEWPORT_OFF 0x900
> +#define IATU_VIEWPORT_INBOUND BIT31
> +#define IATU_VIEWPORT_OUTBOUND 0
> +#define IATU_VIEWPORT_REGION_INDEX(Idx) ((Idx) & 7)
> +
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
> +
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28
> +
> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
> +
> +#define CORE_CONTROL 0x000
> +#define APP_LTSSM_ENABLE BIT4
> +#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define AXI_CLK_STOP 0x004
> +#define DBI_ACLK_STOP BIT8
> +#define SLV_ACLK_STOP BIT4
> +#define MSTR_ACLK_STOP BIT0
> +#define DBI_CSYSREQ_REG BIT9
> +#define SLV_CSYSREQ_REG BIT5
> +#define MSTR_CSYSREQ_REG BIT1
> +
> +#define RESET_CONTROL_1 0x00C
> +#define PERST_N_O_REG BIT5
> +#define PERST_N_I_REG BIT4
> +#define BUTTON_RST_N_REG BIT1
> +#define PWUP_RST_N_REG BIT0
> +
> +#define RESET_CONTROL_2 0x010
> +
> +#define RESET_SELECT_1 0x014
> +#define SQU_RST_SEL BIT29
> +#define PHY_RST_SEL BIT28
> +#define PWR_RST_SEL BIT24
> +#define STI_RST_SEL BIT20
> +#define N_STI_RST_SEL BIT16
> +#define CORE_RST_SEL BIT12
> +#define PERST_SEL BIT4
> +#define BUTTON_RST_SEL BIT1
> +#define PWUP_RST_SEL BIT0
> +
> +#define RESET_SELECT_2 0x018
> +#define DBI_ARST_SEL BIT8
> +#define SLV_ARST_SEL BIT4
> +#define MSTR_ARST_SEL BIT0
> +
> +#define EM_CONTROL 0x030
> +#define PRE_DET_STT_REG BIT4
> +
> +#define EM_SELECT 0x034
> +#define PRE_DET_STT_SEL BIT4
> +
> +#define PM_CONTROL_2 0x050
> +#define SYS_AUX_PWR_DET BIT8
> +
> +#define PHY_CONFIG_COM_6 0x114
> +#define PIPE_PORT_SEL (BIT1 | BIT0)
> +
> +#define LINK_MONITOR 0x210
> +#define SMLH_LINK_UP BIT0
> +
> +#define LINK_CAPABILITIES_REG 0x07C
> +#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4)
> +#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define LINK_CONTROL_LINK_STATUS_REG 0x080
> +#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20)
> +#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16)
> +
> +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
> +#define BASE_CLASS_CODE 0xFF000000
> +#define BASE_CLASS_CODE_VALUE 0x06
> +#define SUBCLASS_CODE 0x00FF0000
> +#define SUBCLASS_CODE_VALUE 0x04
> +#define PROGRAM_INTERFACE 0x0000FF00
> +#define PROGRAM_INTERFACE_VALUE 0x00
> +
> +#define MISC_CONTROL_1_OFF 0x8BC
> +#define DBI_RO_WR_EN BIT0
> +
> +STATIC
> +VOID
> +ConfigureWindow (
> + IN EFI_PHYSICAL_ADDRESS DbiBase,
> + IN UINTN Index,
> + IN UINT64 CpuBase,
> + IN UINT64 PciBase,
> + IN UINT64 Size,
> + IN UINTN Type,
> + IN UINTN EnableFlags
> + )
> +{
> + ArmDataMemoryBarrier ();
> +
> + MmioWrite32 (DbiBase + IATU_VIEWPORT_OFF,
> + IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
> +
> + ArmDataMemoryBarrier ();
> +
> + MmioWrite32 (DbiBase + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(CpuBase & 0xFFFFFFFF));
> + MmioWrite32 (DbiBase + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(CpuBase >> 32));
> + MmioWrite32 (DbiBase + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(CpuBase + Size - 1));
> + MmioWrite32 (DbiBase + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(PciBase & 0xFFFFFFFF));
> + MmioWrite32 (DbiBase + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(PciBase >> 32));
> + MmioWrite32 (DbiBase + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + Type);
> + MmioWrite32 (DbiBase + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);
No barrier needed here?
> +}
> +
> +STATIC
> +VOID
> +SnPcieSetData (
> + EFI_PHYSICAL_ADDRESS Base,
> + UINT32 Offset,
> + UINT32 Mask,
> + UINT32 In
> + )
> +{
> + UINT32 Data;
> + UINT32 Shift;
> +
> + Shift = 1;
> + if (In) {
> + while (!(Mask & Shift))
{
> + Shift <<= 1;
}
/
Leif
> + Data = (MmioRead32 (Base + Offset) & ~Mask) | (In * Shift);
> + } else {
> + Data = MmioRead32 (Base + Offset) & ~Mask;
> + }
> +
> + MmioWrite32 (Base + Offset, Data);
> +}
> +
> +STATIC
> +UINT32
> +SnPcieReadData (
> + EFI_PHYSICAL_ADDRESS Base,
> + UINT32 Offset,
> + UINT32 Mask
> + )
> +{
> + UINT32 Shift;
> +
> + Shift = 0;
> + while (!(Mask & 1)) {
> + Mask >>= 1;
> + Shift++;
> + }
> +
> + return (MmioRead32 (Base + Offset) >> Shift) & Mask;
> +}
> +
> +STATIC
> +VOID
> +SnDbiRoWrEn (
> + IN EFI_PHYSICAL_ADDRESS DbiBase,
> + IN INTN MaxLinkWidth,
> + IN INTN MaxLinkSpeed
> + )
> +{
> + SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
> +
> + SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_WIDTH, MaxLinkWidth);
> + SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_SPEED, MaxLinkSpeed);
> +
> + SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
> + SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
> + SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
> +
> + SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
> +}
> +
> +STATIC
> +VOID
> +PciInitController (
> + IN EFI_PHYSICAL_ADDRESS ExsBase,
> + IN EFI_PHYSICAL_ADDRESS DbiBase,
> + IN EFI_PHYSICAL_ADDRESS ConfigBase,
> + IN CONST PCI_ROOT_BRIDGE *RootBridge
> + )
> +{
> + SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0);
> + SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 0);
> + SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 1);
> +
> + // 1: Assert all PHY / LINK resets
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , PERST_SEL , 0);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG , 0);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG , 0);
> +
> + // Device Reset(PERST#) is effective afrer Set device_type (RC)
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , PWUP_RST_SEL , 0);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , BUTTON_RST_SEL , 0);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , PWR_RST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_2 , MSTR_ARST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_2 , SLV_ARST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_2 , DBI_ARST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , CORE_RST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , STI_RST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , N_STI_RST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , SQU_RST_SEL , 1);
> + SnPcieSetData (ExsBase, RESET_SELECT_1 , PHY_RST_SEL , 1);
> +
> + // 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup.
> + SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
> +
> + // 3: Set device_type (RC)
> + SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4);
> +
> + // 4: Set Bifurcation 1=disable 4=able
> + // 5: Supply Reference (It has executed)
> + // 6: Wait for 10usec (Reference Clocks is stable)
> + // 7 De assert PERST# */
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG, 1);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG, 1);
> +
> + // 8 Assert SYS_AUX_PWR_DET
> + SnPcieSetData(ExsBase, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
> +
> + // 9 Supply following clocks
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
> + SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
> +
> + // 10 De assert PHY reset
> + // 11 De assert LINK's PMC reset
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
> + SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
> + // 12 PHY auto
> + // 13 Wrapper auto
> + // 14-17 PHY auto
> + // 18 Wrapper auto
> + // 19 Update registers through DBI AXI Slave interface
> + SnDbiRoWrEn (DbiBase, 4 /* lanes */, /* Gen */ 2);
> +
> + //
> + // ECAM shift mode uses bits [27:12] of the untranslated address as
> + // B/D/F identifiers. This only works as expected if the base of the
> + // region is aligned to 256 MB, or the effective bus numbers will be
> + // out of sync with the bus base and limit values we chose.
> + //
> + ASSERT ((ConfigBase % SIZE_256MB) == RootBridge->Bus.Base * SIZE_1MB);
> +
> + MmioOr32 (DbiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE |
> + EFI_PCI_COMMAND_MEMORY_SPACE |
> + EFI_PCI_COMMAND_BUS_MASTER);
> +
> + // Region 0: MMIO32 range
> + ConfigureWindow (DbiBase, 0,
> + RootBridge->Mem.Base,
> + RootBridge->Mem.Base,
> + RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + 0);
> +
> + // Region 1: Type 0 config space
> + ConfigureWindow (DbiBase, 1,
> + ConfigBase + RootBridge->Bus.Base * SIZE_1MB,
> + 0x0,
> + SIZE_64KB,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
> +
> + // Region 2: Type 1 config space
> + ConfigureWindow (DbiBase, 2,
> + ConfigBase + RootBridge->Bus.Base * SIZE_1MB + SIZE_64KB,
> + 0x0,
> + (RootBridge->Bus.Limit - RootBridge->Bus.Base + 1) * SIZE_1MB - SIZE_64KB,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
> +
> + // Region 3: port I/O range
> + ConfigureWindow (DbiBase, 3,
> + FixedPcdGet32 (PcdPciIoTranslation) + RootBridge->Io.Base,
> + RootBridge->Io.Base,
> + RootBridge->Io.Limit - RootBridge->Io.Base + 1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + 0);
> +
> + // Region 4: MMIO64 range
> + ConfigureWindow (DbiBase, 4,
> + RootBridge->MemAbove4G.Base,
> + RootBridge->MemAbove4G.Base,
> + RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + 0);
> +
> + // enable link
> + if (SnPcieReadData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) {
> + SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
> + }
> +}
> +
> +STATIC CONST struct {
> + EFI_PHYSICAL_ADDRESS DbiBase;
> + EFI_PHYSICAL_ADDRESS ExsBase;
> + EFI_PHYSICAL_ADDRESS ConfigBase;
> +} mBaseAddresses [] = {
> + {
> + SYNQUACER_PCI_SEG0_DBI_BASE,
> + SYNQUACER_PCI_SEG0_EXS_BASE,
> + SYNQUACER_PCI_SEG0_CONFIG_BASE
> + },
> + {
> + SYNQUACER_PCI_SEG1_DBI_BASE,
> + SYNQUACER_PCI_SEG1_EXS_BASE,
> + SYNQUACER_PCI_SEG1_CONFIG_BASE
> + },
> +};
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SynquacerPciHostBridgeLibConstructor (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + PCI_ROOT_BRIDGE *RootBridges;
> + UINTN Count;
> + UINTN Idx;
> +
> + RootBridges = PciHostBridgeGetRootBridges (&Count);
> + ASSERT (Count == ARRAY_SIZE(mBaseAddresses));
> + if (Count != ARRAY_SIZE(mBaseAddresses)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + for (Idx = 0; Idx < Count; Idx++) {
> + PciInitController (mBaseAddresses[Idx].ExsBase,
> + mBaseAddresses[Idx].DbiBase,
> + mBaseAddresses[Idx].ConfigBase,
> + &RootBridges[Idx]);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (4 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 14:45 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support Ard Biesheuvel
` (7 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
The Synquacer SOC has two separate PCIe RCs, which means there is
no single value for the translation offset between I/O port accesses
and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
that takes the two disjoint I/O windows into account.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c | 588 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf | 50 ++
2 files changed, 638 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
new file mode 100644
index 000000000000..8591a251aea3
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
@@ -0,0 +1,588 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Platform/Pcie.h>
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS SYNQUACER_PCI_SEG1_PORTIO_MAX
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all oveflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ switch (Address) {
+ case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
+ Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
+ break;
+ case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
+ Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ switch (Address) {
+ case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
+ Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
+ break;
+ case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
+ Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+SynquacerPciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
new file mode 100644
index 000000000000..8b56561f029d
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
@@ -0,0 +1,50 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SynquacerPciCpuIo2Dxe
+ FILE_GUID = cee8beea-507a-49f4-a3d7-d1100a2008cc
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SynquacerPciCpuIo2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ SynquacerPciCpuIo2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
2017-09-08 18:23 ` [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL Ard Biesheuvel
@ 2017-09-11 14:45 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 14:45 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:07PM +0100, Ard Biesheuvel wrote:
> The Synquacer SOC has two separate PCIe RCs, which means there is
> no single value for the translation offset between I/O port accesses
> and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
> that takes the two disjoint I/O windows into account.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c | 588 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf | 50 ++
> 2 files changed, 638 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
> new file mode 100644
> index 000000000000..8591a251aea3
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
> @@ -0,0 +1,588 @@
> +/** @file
> + Produces the CPU I/O 2 Protocol.
> +
> +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +This program and the accompanying materials
> +are licensed and made available under the terms and conditions of the BSD License
> +which accompanies this distribution. The full text of the license may be found at
> +http://opensource.org/licenses/bsd-license.php
> +
> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Platform/Pcie.h>
> +#include <Protocol/CpuIo2.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#define MAX_IO_PORT_ADDRESS SYNQUACER_PCI_SEG1_PORTIO_MAX
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE mHandle = NULL;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mInStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 0, // EfiCpuIoWidthFifoUint8
> + 0, // EfiCpuIoWidthFifoUint16
> + 0, // EfiCpuIoWidthFifoUint32
> + 0, // EfiCpuIoWidthFifoUint64
> + 1, // EfiCpuIoWidthFillUint8
> + 2, // EfiCpuIoWidthFillUint16
> + 4, // EfiCpuIoWidthFillUint32
> + 8 // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mOutStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 1, // EfiCpuIoWidthFifoUint8
> + 2, // EfiCpuIoWidthFifoUint16
> + 4, // EfiCpuIoWidthFifoUint32
> + 8, // EfiCpuIoWidthFifoUint64
> + 0, // EfiCpuIoWidthFillUint8
> + 0, // EfiCpuIoWidthFillUint16
> + 0, // EfiCpuIoWidthFillUint32
> + 0 // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> + Check parameters to a CPU I/O 2 Protocol service request.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> + be handled by the driver.
> +
> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The parameters for this request pass the checks.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> + IN BOOLEAN MmioOperation,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + UINT64 MaxCount;
> + UINT64 Limit;
> +
> + //
> + // Check to see if Buffer is NULL
> + //
> + if (Buffer == NULL) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Width is in the valid range
> + //
> + if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // For FIFO type, the target address won't increase during the access,
> + // so treat Count as 1
> + //
> + if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
> + Count = 1;
> + }
> +
> + //
> + // Check to see if Width is in the valid range for I/O Port operations
> + //
> + Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
No space before (Width?
> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Address is aligned
> + //
> + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check to see if any address associated with this transfer exceeds the maximum
> + // allowed address. The maximum address implied by the parameters passed in is
> + // Address + Size * Count. If the following condition is met, then the transfer
> + // is not supported.
> + //
> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
> + //
> + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
> + // can also be the maximum integer value supported by the CPU, this range
> + // check must be adjusted to avoid all oveflow conditions.
> + //
> + // The following form of the range check is equivalent but assumes that
> + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
> + //
> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
> + if (Count == 0) {
> + if (Address > Limit) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + MaxCount = RShiftU64 (Limit, Width);
> + if (MaxCount < (Count - 1)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + }
> +
> + //
> + // Check to see if Buffer is aligned
> + //
> + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> + be handled by the driver.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
I know this is arguably just a question of preference (and taken from
the template), but why not VOID * and BufferPointer (or something)?
Casts to UINT8 * tingle my spidey sense.
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
Obviously a *((UINT8 *) would be needed.
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> + be handled by the driver.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
Same comment.
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> + be handled by the driver.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
Same comment.
> +
> + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + switch (Address) {
> + case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
Is the '...' extension permitted?
This wouldn't look horrifically worse as an if ... else if .. else,
and it would be portable.
> + Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
> + break;
> + case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
> + Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
> + break;
> + default:
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
Drop space before (Width?
> +
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> + be handled by the driver.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
Same comment?
> +
> + //
> + // Make sure the parameters are valid
> + //
> + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + switch (Address) {
> + case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
Same comment.
> + Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
> + break;
> + case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
> + Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
> + break;
> + default:
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
Drop space before (Width?
> +
> + for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// CPU I/O 2 Protocol instance
> +//
> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
> + {
> + CpuMemoryServiceRead,
> + CpuMemoryServiceWrite
> + },
> + {
> + CpuIoServiceRead,
> + CpuIoServiceWrite
> + }
> +};
> +
> +
> +/**
> + The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SynquacerPciCpuIo2Initialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mHandle,
> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> new file mode 100644
> index 000000000000..8b56561f029d
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
> +#
> +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Bump.
> + BASE_NAME = SynquacerPciCpuIo2Dxe
> + FILE_GUID = cee8beea-507a-49f4-a3d7-d1100a2008cc
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SynquacerPciCpuIo2Initialize
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = ARM AARCH64
> +#
> +
> +[Sources]
> + SynquacerPciCpuIo2Dxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> + UefiDriverEntryPoint
> + BaseLib
> + DebugLib
> + IoLib
> + PcdLib
> + UefiBootServicesTableLib
Sort, please?
/
Leif
> +
> +[Protocols]
> + gEfiCpuIo2ProtocolGuid ## PRODUCES
> +
> +[Depex]
> + TRUE
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (5 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 14:48 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller Ard Biesheuvel
` (6 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Wire up the various drivers and libraries for the SynquacerEvalBoard
platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
and the various bus, partition and file system drivers that we need
to make use of PCIe devices.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 49 ++++++++++++++++++++
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 38 +++++++++++++++
2 files changed, 87 insertions(+)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 2a9a0037dcda..aea39b46d91b 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -100,6 +100,7 @@
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
# BDS Libraries
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -148,6 +149,12 @@
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ #
+ # PCI
+ #
+ PciSegmentLib|Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
+ PciHostBridgeLib|Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
+
[LibraryClasses.common.UEFI_APPLICATION]
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@@ -184,6 +191,7 @@
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
# Ashbrook 12-Cluster profile
gArmPlatformTokenSpaceGuid.PcdCoreCount|2
@@ -392,3 +400,44 @@
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
}
+
+ #
+ # PCI
+ #
+ Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # USB
+ #
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # RNG
+ #
+ Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index 6c00e16b169e..befad354918e 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -128,6 +128,44 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
+ #
+ # PCI
+ #
+ INF Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # USB
+ #
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # RNG
+ #
+ INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support
2017-09-08 18:23 ` [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support Ard Biesheuvel
@ 2017-09-11 14:48 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 14:48 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:08PM +0100, Ard Biesheuvel wrote:
> Wire up the various drivers and libraries for the SynquacerEvalBoard
> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
> and the various bus, partition and file system drivers that we need
> to make use of PCIe devices.
If you're folding ChaosKey driver in here (as you are) it deserves a
mention in the commit message.
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 49 ++++++++++++++++++++
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 38 +++++++++++++++
> 2 files changed, 87 insertions(+)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index 2a9a0037dcda..aea39b46d91b 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -100,6 +100,7 @@
> DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>
> # BDS Libraries
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> @@ -148,6 +149,12 @@
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>
> + #
> + # PCI
> + #
> + PciSegmentLib|Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> + PciHostBridgeLib|Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> +
> [LibraryClasses.common.UEFI_APPLICATION]
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> @@ -184,6 +191,7 @@
> gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
> gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
>
> # Ashbrook 12-Cluster profile
> gArmPlatformTokenSpaceGuid.PcdCoreCount|2
> @@ -392,3 +400,44 @@
> NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> }
> +
> + #
> + # PCI
> + #
> + Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> + # AHCI Support
> + #
> + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> + #
> + # USB
> + #
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
Is there a good reason for leaving out Uhci/Ehci?
/
Leif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # RNG
> + #
> + Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index 6c00e16b169e..befad354918e 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -128,6 +128,44 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> INF MdeModulePkg/Application/UiApp/UiApp.inf
>
> + #
> + # PCI
> + #
> + INF Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> + # AHCI Support
> + #
> + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> + #
> + # USB
> + #
> + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # RNG
> + #
> + INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> +
> [FV.FVMAIN_COMPACT]
> FvAlignment = 8
> ERASE_POLARITY = 1
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (6 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 16:12 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver Ard Biesheuvel
` (5 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
This adds the NetSecDxe driver provided by Socionext, but reworked
extensively to improve compliance with the SimpleNetworkProtocol API,
and to avoid uncached allocations for streaming DMA.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1000 ++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 88 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 265 ++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++
21 files changed, 8013 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
new file mode 100644
index 000000000000..7c3f12362f14
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
@@ -0,0 +1,1000 @@
+/** @file
+
+ Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/NetLib.h>
+
+#include "NetsecDxe.h"
+#include "netsec_for_uefi/pfdep.h"
+
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+STATIC NETSEC_DEVICE_PATH NetsecPathTemplate = {
+ {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_MAC_ADDR_DP,
+ {
+ (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)),
+ (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH) >> 8)
+ }
+ },
+ {
+ {
+ 0
+ }
+ },
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ sizeof(EFI_DEVICE_PATH_PROTOCOL), 0
+ }
+ }
+};
+
+STATIC
+VOID
+GetCurrentMacAddress(
+ OUT UINT8 *Mac)
+{
+ Mac[0] = MmioRead8(MAC_ADDRESS + 3);
+ Mac[1] = MmioRead8(MAC_ADDRESS + 2);
+ Mac[2] = MmioRead8(MAC_ADDRESS + 1);
+ Mac[3] = MmioRead8(MAC_ADDRESS + 0);
+ Mac[4] = MmioRead8(MAC_ADDRESS + 7);
+ Mac[5] = MmioRead8(MAC_ADDRESS + 6);
+}
+
+/*
+ * Probe()
+ */
+STATIC
+EFI_STATUS
+Probe (
+ IN EFI_HANDLE Handle,
+ IN NETSEC_DRIVER *LanDriver
+ )
+{
+ ogma_param_t Param;
+ ogma_err_t ogma_err;
+ UINT64 dmac_hm_cmd_base, dmac_mh_cmd_base, core_cmd_base;
+ UINT32 dmac_hm_cmd_size, dmac_mh_cmd_size, core_cmd_size;
+
+ SetMem (&Param, sizeof(Param), 0);
+
+ Param.use_gmac_flag = OGMA_TRUE;
+
+ Param.use_jumbo_pkt_flag = PcdGet8 (PcdJumboPacket);
+
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].little_endian_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].tmr_mode_flag = OGMA_FALSE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].entry_num = PcdGet16 (PcdEncTxDescNum);
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].little_endian_flag = OGMA_TRUE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].tmr_mode_flag = OGMA_FALSE;
+ Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].entry_num = PcdGet16 (PcdDecRxDescNum);
+
+ // phy-interface
+ Param.gmac_config.phy_interface = OGMA_PHY_INTERFACE_RGMII;
+
+ // Read and save the Permanent MAC Address
+ GetCurrentMacAddress (LanDriver->SnpMode.PermanentAddress.Addr);
+
+ LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
+ DEBUG ((DEBUG_NET | DEBUG_INFO,
+ "Netsec: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
+ LanDriver->SnpMode.PermanentAddress.Addr[0],
+ LanDriver->SnpMode.PermanentAddress.Addr[1],
+ LanDriver->SnpMode.PermanentAddress.Addr[2],
+ LanDriver->SnpMode.PermanentAddress.Addr[3],
+ LanDriver->SnpMode.PermanentAddress.Addr[4],
+ LanDriver->SnpMode.PermanentAddress.Addr[5]));
+
+ // Get hm microcode's physical addresses
+ dmac_hm_cmd_base = MmioRead32 (HM_ME_ADDRESS_H);
+ dmac_hm_cmd_base <<= 32;
+ dmac_hm_cmd_base |= MmioRead32 (HM_ME_ADDRESS_L);
+ dmac_hm_cmd_size = MmioRead32 (HM_ME_SIZE);
+
+ // Get mh microcode's physical addresses
+ dmac_mh_cmd_base = MmioRead32 (MH_ME_ADDRESS_H);
+ dmac_mh_cmd_base <<= 32;
+ dmac_mh_cmd_base |= MmioRead32 (MH_ME_ADDRESS_L);
+ dmac_mh_cmd_size = MmioRead32 (MH_ME_SIZE);
+
+ // Get core microcode's physical addresses
+ core_cmd_base = MmioRead32 (PACKET_ME_ADDRESS);
+ core_cmd_size = MmioRead32 (PACKET_ME_SIZE);
+
+ ogma_err = ogma_init ((VOID *)((UINTN)PcdGet32(PcdNetsecDxeBaseAddress)),
+ Handle, &Param,
+ (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
+ (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
+ (VOID *)core_cmd_base, core_cmd_size,
+ &LanDriver->Handle);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
+ ogma_err));
+ return EFI_DEVICE_ERROR;
+ }
+
+ ogma_enable_top_irq (LanDriver->Handle,
+ OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * UEFI Stop() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStop (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // Check state of the driver
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkStarted:
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Change the state
+ Snp->Mode->State = EfiSimpleNetworkStopped;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Initialize() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINTN RxBufferSize OPTIONAL,
+ IN UINTN TxBufferSize OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ ogma_phy_link_status_t phy_link_status;
+ ogma_err_t ogma_err;
+ ogma_gmac_mode_t ogma_gmac_mode;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // Check that driver was started but not initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkStarted:
+ break;
+ case EfiSimpleNetworkInitialized:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver already initialized\n"));
+ ReturnUnlock (EFI_SUCCESS);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ // ##### open
+ ogma_err = ogma_clean_rx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_rx_desc_ring() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_tx_desc_ring() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_clear_desc_ring_irq_status (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ // ##### open_sub
+ ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+ OGMA_DESC_RING_ID_NRM_RX,
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_set_irq_coalesce_param(LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX,
+ RXINT_PKTCNT,
+ OGMA_FALSE,
+ RXINT_TMR_CNT_US);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_irq_coalesce_param() failed with error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+ OGMA_DESC_RING_ID_NRM_TX,
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ // ##### configure_mac
+ ogma_err = ogma_stop_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_stop_gmac() failed with error status %d\n",
+ ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_get_phy_link_status(LanDriver->Handle, PcdGet8(PcdPhyDevAddr), &phy_link_status);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_phy_link_status() failed error code %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ SetMem (&ogma_gmac_mode, sizeof(ogma_gmac_mode_t), 0);
+ ogma_gmac_mode.link_speed = phy_link_status.link_speed;
+ ogma_gmac_mode.half_duplex_flag = (ogma_bool)phy_link_status.half_duplex_flag;
+ if ((!phy_link_status.half_duplex_flag) && PcdGet8(PcdFlowCtrl)) {
+ ogma_gmac_mode.flow_ctrl_enable_flag = (ogma_bool)PcdGet8(PcdFlowCtrl);
+ ogma_gmac_mode.flow_ctrl_start_threshold = (ogma_uint16)PcdGet16(PcdFlowCtrlStartThreshold);
+ ogma_gmac_mode.flow_ctrl_stop_threshold = (ogma_uint16)PcdGet16(PcdFlowCtrlStopThreshold);
+ ogma_gmac_mode.pause_time = (ogma_uint16)PcdGet16(PcdPauseTime);
+ }
+
+ ogma_err = ogma_set_gmac_mode(LanDriver->Handle, &ogma_gmac_mode);
+ if(ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_gmac() failed with error status %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_start_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+ if(ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_start_gmac() failed with error status %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Declare the driver as initialized
+ Snp->Mode->State = EfiSimpleNetworkInitialized;
+ Status = EFI_SUCCESS;
+
+ DEBUG ((DEBUG_INFO | DEBUG_LOAD, "NETSEC: Driver started\n"));
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Shutdown () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // First check that driver has already been initialized
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver in stopped state\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+
+ ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+ ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+ Snp->Mode->State = EfiSimpleNetworkStarted;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+STATIC
+VOID
+EFIAPI
+NotifyExitBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+ EFI_STATUS Status;
+
+ Snp = Context;
+
+ if (Snp->Mode != EfiSimpleNetworkStopped) {
+ Status = SnpShutdown (Snp);
+ if (!EFI_ERROR (Status)) {
+ SnpStop (Snp);
+ }
+ }
+ gBS->CloseEvent (Event);
+}
+
+/*
+ * UEFI Start() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStart (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
+ )
+{
+ EFI_SIMPLE_NETWORK_MODE *Mode;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ // Check Snp instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+ Mode = Snp->Mode;
+
+ // Check state of the driver
+ switch (Mode->State) {
+ case EfiSimpleNetworkStopped:
+ break;
+ case EfiSimpleNetworkStarted:
+ case EfiSimpleNetworkInitialized:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver already started\n"));
+ ReturnUnlock (EFI_ALREADY_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, NETSEC_TPL,
+ NotifyExitBoot, Snp, &LanDriver->ExitBootEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ // Change state
+ Mode->State = EfiSimpleNetworkStarted;
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+
+}
+
+/*
+ * UEFI ReceiveFilters() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINT32 Enable,
+ IN UINT32 Disable,
+ IN BOOLEAN Reset,
+ IN UINTN NumMfilter OPTIONAL,
+ IN EFI_MAC_ADDRESS *Mfilter OPTIONAL
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ // Check Snp Instance
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // First check that driver has already been initialized
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n", (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI GetStatus () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ OUT UINT32 *IrqStat OPTIONAL,
+ OUT VOID **TxBuff OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ pfdep_pkt_handle_t pkt_handle;
+ LIST_ENTRY *Link;
+
+ ogma_phy_link_status_t phy_link_status;
+ ogma_err_t ogma_err;
+
+ // Check preliminaries
+ if (Snp == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ // Update the media status
+ ogma_err = ogma_get_phy_link_status (LanDriver->Handle,
+ PcdGet8(PcdPhyDevAddr),
+ &phy_link_status);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_phy_link_status failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ Snp->Mode->MediaPresent = phy_link_status.up_flag;
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+
+ if (TxBuff != NULL) {
+ *TxBuff = NULL;
+ //
+ // Find a buffer in the list that has been released
+ //
+ for (Link = GetFirstNode (&LanDriver->TxBufferList);
+ !IsNull (&LanDriver->TxBufferList, Link);
+ Link = GetNextNode (&LanDriver->TxBufferList, Link)) {
+
+ pkt_handle = BASE_CR (Link, PACKET_HANDLE, Link);
+ if (pkt_handle->Released) {
+ *TxBuff = pkt_handle->Buffer;
+ RemoveEntryList (Link);
+ FreePool (pkt_handle);
+ break;
+ }
+ }
+ }
+
+ if (IrqStat != 0) {
+ *IrqStat = 0;
+ }
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Transmit() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ IN UINTN HdrSize,
+ IN UINTN BufSize,
+ IN VOID *BufAddr,
+ IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
+ IN EFI_MAC_ADDRESS *DstAddr OPTIONAL,
+ IN UINT16 *Protocol OPTIONAL
+ )
+{
+ NETSEC_DRIVER *LanDriver;
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+
+ ogma_tx_pkt_ctrl_t tx_pkt_ctrl;
+ ogma_frag_info_t scat_info;
+ ogma_uint16 tx_avail_num;
+ ogma_err_t ogma_err;
+ UINT16 Proto;
+ pfdep_pkt_handle_t pkt_handle;
+
+ // Check preliminaries
+ if ((Snp == NULL) || (BufAddr == NULL)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", Snp, BufAddr));
+ return EFI_DEVICE_ERROR;
+ }
+
+ pkt_handle = AllocateZeroPool (sizeof *pkt_handle);
+ if (pkt_handle == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ pkt_handle->Buffer = BufAddr;
+ pkt_handle->RecycleForTx = TRUE;
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ ogma_err = ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clear_desc_ring_irq_status failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_clean_tx_desc_ring failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Ensure header is correct size if non-zero
+ if (HdrSize) {
+ if (HdrSize != Snp->Mode->MediaHeaderSize) {
+ DEBUG ((DEBUG_ERROR, "NETSEC: SnpTransmit(): Invalid HdrSize %d\n",
+ HdrSize));
+ ReturnUnlock (EFI_INVALID_PARAMETER);
+ }
+
+ if ((DstAddr == NULL) || (Protocol == NULL)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
+ DstAddr, Protocol));
+ ReturnUnlock (EFI_INVALID_PARAMETER);
+ }
+
+ // Copy destination address
+ CopyMem (BufAddr, (VOID *)DstAddr, NET_ETHER_ADDR_LEN);
+ // Copy source address
+ CopyMem (BufAddr + NET_ETHER_ADDR_LEN, (VOID *)SrcAddr, NET_ETHER_ADDR_LEN);
+ // Copy protocol
+ Proto = HTONS(*Protocol);
+ CopyMem (BufAddr + (NET_ETHER_ADDR_LEN * 2), (VOID *)&Proto, sizeof(UINT16));
+ }
+
+ Status = DmaMap (MapOperationBusMasterRead, BufAddr, &BufSize,
+ &scat_info.phys_addr, &pkt_handle->Mapping);
+ if (EFI_ERROR (Status)) {
+ goto ExitUnlock;
+ }
+
+ scat_info.addr = BufAddr;
+ scat_info.len = BufSize;
+
+ SetMem (&tx_pkt_ctrl, sizeof (ogma_tx_pkt_ctrl_t), 0);
+
+ tx_pkt_ctrl.pass_through_flag = OGMA_TRUE;
+ tx_pkt_ctrl.target_desc_ring_id = OGMA_DESC_RING_ID_GMAC;
+
+ // check empty slot
+ do {
+ tx_avail_num = ogma_get_tx_avail_num (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX);
+ } while (tx_avail_num < SCAT_NUM);
+
+ // send
+ ogma_err = ogma_set_tx_pkt_data (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ &tx_pkt_ctrl,
+ SCAT_NUM,
+ &scat_info,
+ pkt_handle);
+
+ if (ogma_err != OGMA_ERR_OK) {
+ DmaUnmap (pkt_handle->Mapping);
+ FreePool (pkt_handle);
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_set_tx_pkt_data failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ //
+ // Queue the descriptor so we can release the buffer once it has been
+ // consumed by the hardware.
+ //
+ InsertTailList (&LanDriver->TxBufferList, &pkt_handle->Link);
+
+ gBS->RestoreTPL (SavedTpl);
+ return EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ FreePool (pkt_handle);
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * UEFI Receive() function
+ */
+EFI_STATUS
+EFIAPI
+SnpReceive (
+ IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
+ OUT UINTN *HdrSize OPTIONAL,
+ IN OUT UINTN *BuffSize,
+ OUT VOID *Data,
+ OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
+ OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,
+ OUT UINT16 *Protocol OPTIONAL
+ )
+{
+ EFI_TPL SavedTpl;
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+
+ ogma_err_t ogma_err;
+ ogma_rx_pkt_info_t rx_pkt_info;
+ ogma_frag_info_t rx_data;
+ ogma_uint16 len;
+ pfdep_pkt_handle_t pkt_handle;
+
+ // Check preliminaries
+ if ((Snp == NULL) || (Data == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Serialize access to data and registers
+ SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+ // Check that driver was started and initialised
+ switch (Snp->Mode->State) {
+ case EfiSimpleNetworkInitialized:
+ break;
+ case EfiSimpleNetworkStarted:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ case EfiSimpleNetworkStopped:
+ DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+ ReturnUnlock (EFI_NOT_STARTED);
+ default:
+ DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+ (UINTN)Snp->Mode->State));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ // Find the LanDriver structure
+ LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+ if (ogma_get_rx_num (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX) > 0) {
+
+ ogma_err = ogma_get_rx_pkt_data(LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_RX,
+ &rx_pkt_info, &rx_data, &len, &pkt_handle);
+ if (ogma_err != OGMA_ERR_OK) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC: ogma_get_rx_pkt_data failed with error code: %d\n",
+ (INT32)ogma_err));
+ ReturnUnlock (EFI_DEVICE_ERROR);
+ }
+
+ DmaUnmap (pkt_handle->Mapping);
+ pkt_handle->Mapping = NULL;
+
+ CopyMem (Data, (VOID*)rx_data.addr, len);
+ *BuffSize = len;
+
+ pfdep_free_pkt_buf (LanDriver->Handle, rx_data.len, rx_data.addr,
+ rx_data.phys_addr, PFDEP_TRUE, pkt_handle);
+ } else {
+ // not received any packets
+ ReturnUnlock (EFI_NOT_READY);
+ }
+
+ if (HdrSize != NULL) {
+ *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
+ }
+
+ ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+ OGMA_DESC_RING_ID_NRM_TX,
+ OGMA_CH_IRQ_REG_EMPTY);
+
+ ogma_clean_tx_desc_ring(LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+ ogma_enable_top_irq (LanDriver->Handle,
+ OGMA_TOP_IRQ_REG_NRM_TX | OGMA_TOP_IRQ_REG_NRM_RX);
+
+ Status = EFI_SUCCESS;
+
+ // Restore TPL and return
+ExitUnlock:
+ gBS->RestoreTPL (SavedTpl);
+ return Status;
+}
+
+/*
+ * Entry point for the Netxec driver
+ */
+EFI_STATUS
+NetsecDxeEntry (
+ IN EFI_HANDLE Handle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ NETSEC_DRIVER *LanDriver;
+ EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+ EFI_SIMPLE_NETWORK_MODE *SnpMode;
+ NETSEC_DEVICE_PATH *NetsecPath;
+
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+ ASSERT_EFI_ERROR(Status);
+
+ // Allocate Resources
+ LanDriver = AllocateZeroPool (sizeof(NETSEC_DRIVER));
+ NetsecPath = AllocateCopyPool (sizeof(NETSEC_DEVICE_PATH),
+ &NetsecPathTemplate);
+
+ // Initialize pointers
+ Snp = &(LanDriver->Snp);
+ SnpMode = &(LanDriver->SnpMode);
+ Snp->Mode = SnpMode;
+
+ // Set the signature of the LAN Driver structure
+ LanDriver->Signature = NETSEC_SIGNATURE;
+
+ // Probe the device
+ Status = Probe (Handle, LanDriver);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "NETSEC:NetsecDxeEntry(): Probe failed with status %d\n", Status));
+ return Status;
+ }
+
+ // Assign fields and func pointers
+ Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
+ Snp->WaitForPacket = NULL;
+ Snp->Initialize = SnpInitialize;
+ Snp->Start = SnpStart;
+ Snp->Stop = SnpStop;
+ Snp->Reset = NULL;
+ Snp->Shutdown = SnpShutdown;
+ Snp->ReceiveFilters = SnpReceiveFilters;
+ Snp->StationAddress = NULL;
+ Snp->Statistics = NULL;
+ Snp->MCastIpToMac = NULL;
+ Snp->NvData = NULL;
+ Snp->GetStatus = SnpGetStatus;
+ Snp->Transmit = SnpTransmit;
+ Snp->Receive = SnpReceive;
+
+ // Fill in simple network mode structure
+ SnpMode->State = EfiSimpleNetworkStopped;
+ SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN; // HW address is 6 bytes
+ SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD); // Size of an Ethernet header
+ SnpMode->MaxPacketSize = EFI_PAGE_SIZE; // Ethernet Frame (with VLAN tag +4 bytes)
+
+ // Supported receive filters
+ SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
+ EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+
+ // Initially-enabled receive filters
+ SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+ EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
+
+ // Netsec has 64bit hash table. We can filter an infinite MACs, but
+ // higher-level software must filter out any hash collisions.
+ SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
+ SnpMode->MCastFilterCount = 0;
+ ZeroMem (&SnpMode->MCastFilter,
+ MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
+
+ // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
+ SnpMode->IfType = NET_IFTYPE_ETHERNET;
+
+ // Mac address is changeable
+ SnpMode->MacAddressChangeable = TRUE;
+
+ // We can only transmit one packet at a time
+ SnpMode->MultipleTxSupported = FALSE;
+
+ // MediaPresent checks for cable connection and partner link
+ SnpMode->MediaPresentSupported = TRUE;
+ SnpMode->MediaPresent = FALSE;
+
+ // Set broadcast address
+ SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+ // Assign fields for device path
+ NetsecPath->Netsec.MacAddress = SnpMode->PermanentAddress;
+ NetsecPath->Netsec.IfType = SnpMode->IfType;
+
+ InitializeListHead (&LanDriver->TxBufferList);
+
+ // Initialise the protocol
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &LanDriver->ControllerHandle,
+ &gEfiSimpleNetworkProtocolGuid, Snp,
+ &gEfiDevicePathProtocolGuid, NetsecPath,
+ NULL);
+
+ // Say what the status of loading the protocol structure is
+ if (EFI_ERROR(Status)) {
+ ogma_terminate (LanDriver->Handle);
+ FreePool (LanDriver);
+ }
+
+ return Status;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
new file mode 100644
index 000000000000..7537d1059b28
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
@@ -0,0 +1,47 @@
+## @file
+#
+# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = OpenPlatformDriversNetNetsecDxePkg
+ PACKAGE_GUID = bd8ddfdd-2e8d-4081-8117-99405df3ffc8
+ PACKAGE_VERSION = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+ gNetsecDxeTokenSpaceGuid = { 0x47d6c028, 0x2413, 0x416d, { 0xa8, 0xef, 0xe4, 0x5c, 0x58, 0x83, 0x5e, 0x49 }}
+
+[PcdsFixedAtBuild.common]
+ # Netsec Ethernet Driver PCDs
+ gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x0|UINT32|0x00000000
+ gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x0|UINT32|0x00000001
+ gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|0x0|UINT16|0x00000002
+ gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|0x0|UINT16|0x00000003
+ gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0x0|UINT8|0x00000004
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007
+ gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008
+ gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|0x0|UINT8|0x00000009
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
new file mode 100644
index 000000000000..f0acdc1448d7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NETSEC_DXE_H_
+#define __NETSEC_DXE_H_
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+// Synchronization TPLs
+#define NETSEC_TPL TPL_CALLBACK
+
+/*--------------- Simple Network Driver entry point functions ----------------*/
+
+// Refer to the Simple Network Protocol section (21.1)
+// in the UEFI 2.3.1 Specification for documentation.
+
+#define ReturnUnlock(s) do { Status = (s); goto ExitUnlock; } while (0)
+
+/*------------------------------------------------------------------------------
+ NETSEC Information Structure
+------------------------------------------------------------------------------*/
+
+typedef struct {
+ // Driver signature
+ UINT32 Signature;
+ EFI_HANDLE ControllerHandle;
+
+ // EFI SNP protocol instances
+ EFI_SIMPLE_NETWORK_PROTOCOL Snp;
+ EFI_SIMPLE_NETWORK_MODE SnpMode;
+
+ // EFI Snp statistics instance
+ EFI_NETWORK_STATISTICS Stats;
+
+ // ogma handle
+ ogma_handle_t Handle;
+
+ // List of submitted TX buffers
+ LIST_ENTRY TxBufferList;
+
+ EFI_EVENT ExitBootEvent;
+} NETSEC_DRIVER;
+
+#define NETSEC_SIGNATURE SIGNATURE_32('n', 't', 's', 'c')
+#define INSTANCE_FROM_SNP_THIS(a) CR(a, NETSEC_DRIVER, Snp, NETSEC_SIGNATURE)
+
+typedef struct {
+ MAC_ADDR_DEVICE_PATH Netsec;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NETSEC_DEVICE_PATH;
+
+/*------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------*/
+
+#define EEPROM_BASE ((UINT32)PcdGet32(PcdEepRomBase))
+
+#define MAC_ADDRESS (0x00 + EEPROM_BASE)
+
+#define HM_ME_ADDRESS_H (0x08 + EEPROM_BASE)
+#define HM_ME_ADDRESS_L (0x0C + EEPROM_BASE)
+#define HM_ME_SIZE (0x10 + EEPROM_BASE)
+
+#define MH_ME_ADDRESS_H (0x14 + EEPROM_BASE)
+#define MH_ME_ADDRESS_L (0x18 + EEPROM_BASE)
+#define MH_ME_SIZE (0x1C + EEPROM_BASE)
+
+#define PACKET_ME_ADDRESS (0x20 + EEPROM_BASE)
+#define PACKET_ME_SIZE (0x24 + EEPROM_BASE)
+
+#define SCAT_NUM 1
+
+#define RXINT_TMR_CNT_US 0
+#define RXINT_PKTCNT 1
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
new file mode 100644
index 000000000000..42de56d89c30
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
@@ -0,0 +1,69 @@
+## @file
+#
+# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = NetsecDxe
+ FILE_GUID = a4eed3af-9837-46b3-9275-c71cb47071f9
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 0.1
+ ENTRY_POINT = NetsecDxeEntry
+
+[Sources]
+ NetsecDxe.c
+
+ netsec_for_uefi/pfdep_uefi.c
+ netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
+ netsec_for_uefi/netsec_sdk/src/ogma_misc.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ NetworkPkg/NetworkPkg.dec
+ Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DevicePathLib
+ DmaLib
+ IoLib
+ NetLib
+ SynchronizationLib
+ TimerLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gEfiSimpleNetworkProtocolGuid
+ gEfiDevicePathProtocolGuid
+
+[FixedPcd]
+ gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress
+ gNetsecDxeTokenSpaceGuid.PcdEepRomBase
+ gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum
+ gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum
+ gNetsecDxeTokenSpaceGuid.PcdJumboPacket
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrl
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold
+ gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr
+ gNetsecDxeTokenSpaceGuid.PcdPauseTime
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
new file mode 100644
index 000000000000..336325109e33
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
@@ -0,0 +1,736 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_API_H
+#define OGMA_API_H
+
+#include "ogma_version.h"
+#include "netsec_for_uefi/ogma_config.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/pfdep.h"
+/**
+ * Check configuration macro settings.
+ */
+#ifdef OGMA_CONFIG_CLK_HZ
+#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
+#error "OGMA_CONFIG_CLK_HZ is not appropriate."
+#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
+#else /* ! OGMA_CONFIG_CLK_HZ */
+#error "OGMA_CONFIG_CLK_HZ is not given."
+#endif /* OGMA_CONFIG_CLK_HZ */
+
+#ifndef OGMA_CONFIG_GMAC_CLK_HZ
+#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
+#endif
+
+/**
+ * Number of hardware limits
+ */
+
+
+/**
+ * Number of Common Descriptor ring id
+ */
+#define OGMA_DESC_RING_ID_NRM_TX 0
+#define OGMA_DESC_RING_ID_NRM_RX 1
+
+#define OGMA_DESC_RING_ID_GMAC 15
+#define OGMA_DESC_RING_ID_MAX 1
+
+/**
+ * Numbre of TCP Segmentation length limits
+ */
+#define OGMA_TCP_SEG_LEN_MAX 1460
+#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
+
+/**
+ * Number of ER check result for received packet
+ */
+#define OGMA_RX_ER_RESULT_NG 0x1
+#define OGMA_RX_ER_RESULT_OK 0x0
+
+/**
+ * Number of checksum calculation result for received packet
+ */
+#define OGMA_RX_CKSUM_RESULT_OK 0x1
+#define OGMA_RX_CKSUM_RESULT_NG 0x2
+#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
+
+/**
+ * Number of ErrorCode for received packet
+ */
+#define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR 0x2
+#define OGMA_RX_ERRCODE_IP_HEADER_ERR 0x1
+#define OGMA_RX_ERRCODE_NONE 0x0
+
+/**
+ * Number of top interrupt enable register bit field
+ */
+#define OGMA_TOP_IRQ_REG_ME_START (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MAC (1UL << 19)
+#define OGMA_TOP_IRQ_REG_PKT (1UL << 18)
+#define OGMA_TOP_IRQ_REG_BOOTCODE_TX (1UL << 5)
+#define OGMA_TOP_IRQ_REG_NRM_RX (1UL << 1)
+#define OGMA_TOP_IRQ_REG_NRM_TX (1UL << 0)
+
+
+/**
+ * Number of top channel enable register bit field
+ */
+#define OGMA_CH_IRQ_REG_EMPTY (1UL << 17)
+#define OGMA_CH_IRQ_REG_ERR (1UL << 16)
+#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
+#define OGMA_CH_IRQ_REG_TIMEUP (1UL << 14)
+#define OGMA_CH_IRQ_REG_RCV (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
+
+/**
+ * Number of top channel enable register bit field for F_NETSEC_C
+ */
+#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
+#define OGMA_CH_IRQ_REG_SND (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
+
+
+/**
+ * Number of packet interrupt enable register bit field
+ */
+#define OGMA_PKT_IRQ_MAC_ER (1UL << 5)
+#define OGMA_PKT_IRQ_JUMBO_ER (1UL << 4)
+#define OGMA_PKT_IRQ_CHKSUM_ER (1UL << 3)
+#define OGMA_PKT_IRQ_HD_INCOMPLETE (1UL << 2)
+#define OGMA_PKT_IRQ_HD_ER (1UL << 1)
+#define OGMA_PKT_IRQ_DRP_NO_MATCH (1UL << 0)
+
+
+/**
+ * Number of mac irq enable register bit field
+ */
+#define OGMA_MAC_IRQ_INT_PMT (1UL << 31)
+#define OGMA_MAC_IRQ_INT_SBD (1UL << 30)
+#define OGMA_MAC_IRQ_INT_LPI (1UL << 29)
+#define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27)
+#define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26)
+#define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25)
+#define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24)
+#define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23)
+
+
+/**
+ * Number of SR IER register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TTI (1U << 29)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GPI (1U << 28)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GMI (1U << 27)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLI (1U << 26)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_NIS (1U << 16)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_AIS (1U << 15)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ERI (1U << 14)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_FBI (1U << 13)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ETI (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RWT (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RPS (1U << 8)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RU (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RI (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_UNF (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_OVF (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TJT (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TU (1U << 2)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TPS (1U << 1)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TI (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TTI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GPI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GMI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_GLI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+ OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+/**
+ * Number of ISR IMR register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_COI (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TI (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RI (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_MI (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_PI (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_TSI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_COI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_TI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_RI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_MI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_PI | \
+ OGMA_GMAC_INT_SBD_IRQ_ISR_RGI)
+
+/**
+ * Number of LPICSR register bit field
+ */
+#define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19)
+#define OGMA_GMAC_LPICSR_REG_PLSEN (1U << 18)
+#define OGMA_GMAC_LPICSR_REG_PLS (1U << 17)
+#define OGMA_GMAC_LPICSR_REG_LPIEN (1U << 16)
+#define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9)
+#define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8)
+#define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3)
+#define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2)
+#define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1)
+#define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0)
+
+/**
+ * Number of RGSR register bit field
+ */
+#define OGMA_GMAC_RGSR_REG_LS (1U << 3)
+#define OGMA_GMAC_RGSR_REG_LSP (1U << 1)
+#define OGMA_GMAC_RGSR_REG_LM (1U << 0)
+
+/**
+ * Number of various limits
+ */
+#define OGMA_DESC_ENTRY_NUM_MIN 2
+#define OGMA_DESC_ENTRY_NUM_MAX 2047
+#define OGMA_INT_PKTCNT_MAX 2047
+#define OGMA_L4_MIN_LEN_MAX 64
+
+/**
+ * Number of ogma phy interface setting
+ */
+#define OGMA_PHY_INTERFACE_GMII 0
+#define OGMA_PHY_INTERFACE_RGMII 1
+#define OGMA_PHY_INTERFACE_RMII 4
+
+/**
+ * Number of ogma link speed setting
+ */
+#define OGMA_PHY_LINK_SPEED_1G 0
+#define OGMA_PHY_LINK_SPEED_100M 1U
+#define OGMA_PHY_LINK_SPEED_10M 2U
+#define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U
+
+/**
+ * Number of flow control limits
+ */
+#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95
+#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX 95
+#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN 5
+
+enum ogma_err_e{
+ OGMA_ERR_OK = 0,
+ OGMA_ERR_PARAM,
+ OGMA_ERR_ALLOC,
+ OGMA_ERR_BUSY,
+ OGMA_ERR_RANGE,
+ OGMA_ERR_DATA,
+ OGMA_ERR_NOTAVAIL,
+ OGMA_ERR_INTERRUPT,
+ OGMA_ERR_AGAIN,
+ OGMA_ERR_INVALID,
+};
+
+typedef void *ogma_handle_t;
+typedef struct ogma_param_s ogma_param_t;
+typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
+typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
+typedef enum ogma_err_e ogma_err_t;
+typedef ogma_uint8 ogma_desc_ring_id_t;
+typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
+typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
+typedef struct ogma_frag_info_s ogma_frag_info_t;
+typedef struct ogma_gmac_config_s ogma_gmac_config_t;
+typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
+
+struct ogma_gmac_config_s{
+ ogma_uint8 phy_interface;
+};
+
+struct ogma_pkt_ctrl_param_s{
+ ogma_uint log_chksum_er_flag:1;
+ ogma_uint log_hd_imcomplete_flag:1;
+ ogma_uint log_hd_er_flag:1;
+ ogma_uint drp_no_match_flag:1;
+};
+
+struct ogma_desc_ring_param_s{
+ ogma_uint valid_flag:1;
+ ogma_uint little_endian_flag:1;
+ ogma_uint tmr_mode_flag:1;
+ ogma_uint16 entry_num;
+};
+
+struct ogma_param_s{
+
+ ogma_uint use_gmac_flag:1;
+ ogma_uint use_jumbo_pkt_flag:1;
+ ogma_pkt_ctrl_param_t pkt_ctrl_param;
+ ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
+ ogma_gmac_config_t gmac_config;
+ ogma_uint8 mac_addr[6];
+};
+
+struct ogma_tx_pkt_ctrl_s{
+ ogma_uint pass_through_flag:1;
+ ogma_uint cksum_offload_flag:1;
+ ogma_uint tcp_seg_offload_flag:1;
+ ogma_desc_ring_id_t target_desc_ring_id;
+ ogma_uint16 tcp_seg_len;
+};
+
+struct ogma_rx_pkt_info_s{
+ ogma_uint fragmented_flag:1;
+ ogma_uint err_flag:1;
+ ogma_uint rx_cksum_result:2;
+ ogma_uint8 err_code;
+};
+
+struct ogma_frag_info_s{
+ pfdep_phys_addr_t phys_addr;
+ void *addr;
+ ogma_uint32 len;
+};
+
+struct ogma_gmac_mode_s{
+ ogma_uint half_duplex_flag:1;
+ ogma_uint flow_ctrl_enable_flag:1;
+ ogma_uint8 link_speed;
+ ogma_uint16 flow_ctrl_start_threshold;
+ ogma_uint16 flow_ctrl_stop_threshold;
+ ogma_uint16 pause_time;
+};
+
+#ifdef OGMA_CONFIG_REC_STAT
+typedef struct ogma_stat_info_s {
+ ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+ ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+} ogma_stat_info_t;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+typedef struct ogma_gmac_int_sbd_regs_s{
+ ogma_uint32 base;
+ ogma_uint32 extended;
+} ogma_gmac_int_sbd_regs_t;
+
+typedef struct ogma_phy_link_status_s{
+ ogma_uint up_flag:1;
+ ogma_uint auto_nego_enable_flag:1;
+ ogma_uint auto_nego_complete_flag:1;
+ ogma_uint half_duplex_flag:1;
+ ogma_uint latched_link_down_flag:1;
+ ogma_uint lpi_capable_flag:1;
+ ogma_uint8 link_speed;
+} ogma_phy_link_status_t;
+
+/**************************
+***************************
+***************************/
+
+ogma_err_t ogma_init (
+ void *base_addr,
+ pfdep_dev_handle_t dev_handle,
+ const ogma_param_t *param_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len,
+ ogma_handle_t *ogma_handle_p
+ );
+
+void ogma_terminate (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_err_t ogma_start_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ );
+
+ogma_err_t ogma_stop_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ );
+
+ogma_err_t ogma_set_gmac_mode (
+ ogma_handle_t ogma_handle,
+ const ogma_gmac_mode_t *gmac_mode_p
+ );
+
+void ogma_set_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ );
+
+ogma_uint16 ogma_get_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ );
+
+ogma_err_t ogma_get_gmac_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool *valid_flag_p,
+ ogma_gmac_mode_t *gmac_mode_p,
+ ogma_bool *rx_running_flag_p,
+ ogma_bool *tx_running_flag_p
+ );
+
+ogma_uint32 ogma_get_top_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_top_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \
+ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag)
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 value
+ );
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_pkt_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+/* ogma_desc_ring_access.c */
+ogma_err_t ogma_start_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_stop_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint16 ogma_get_rx_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_uint16 ogma_get_tx_avail_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_clean_tx_desc_ring(
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_clean_rx_desc_ring(
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ );
+
+ogma_err_t ogma_set_tx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_uint8 scat_num,
+ const ogma_frag_info_t *scat_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ );
+
+ogma_err_t ogma_get_rx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ );
+
+ogma_err_t ogma_enable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_enable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_enable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_uint32 ogma_get_hw_ver (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_uint32 ogma_get_mcr_ver (
+ ogma_handle_t ogma_handle
+ );
+
+/**
+ * Set up IRQ coalesce parameters.
+ *
+ * [Note]
+ * - This is a tentative implementation.
+ * Not tested enough. Use with care.
+ *
+ * - Call this function after every invocation of ogma_start_desc_ring()
+ * because ogma_start_desc_ring() resets IRQ coalesce settings.
+ *
+ */
+ogma_err_t ogma_set_irq_coalesce_param (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint16 int_pktcnt,
+ ogma_bool int_tmr_unit_ms_flag,
+ ogma_uint16 int_tmr_cnt
+ );
+
+ogma_uint32 ogma_get_mac_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+
+ogma_uint32 ogma_get_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_mac_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_err_t ogma_enable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+ogma_err_t ogma_disable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ );
+
+#ifdef OGMA_CONFIG_REC_STAT
+/**
+ * Get statistics information.
+ */
+ogma_err_t ogma_get_stat_info (
+ ogma_handle_t ogma_handle,
+ ogma_stat_info_t *stat_info_p,
+ ogma_bool clear_flag
+ );
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ );
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ );
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 ls_timer_ms,
+ ogma_uint16 tw_timer_ms
+ );
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 *ls_timer_ms_p,
+ ogma_uint16 *tw_timer_ms_p
+ );
+
+void ogma_set_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ );
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+ogma_err_t ogma_get_phy_link_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_phy_link_status_t *phy_link_status_p
+ );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+ ogma_handle_t ogma_handle
+ );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ );
+
+#define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ );
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ );
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p,
+ ogma_bool reset_flag
+ );
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+ ogma_handle_t ogma_handle
+ );
+
+/**************************
+***************************
+***************************/
+
+#endif /* OGMA_API_H*/
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
new file mode 100644
index 000000000000..7c39b7c9cdd7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
@@ -0,0 +1,45 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_TYPE_H
+#define OGMA_BASIC_TYPE_H
+#include "netsec_for_uefi/pfdep.h"
+
+/**
+ *
+ */
+#define OGMA_TRUE PFDEP_TRUE
+#define OGMA_FALSE PFDEP_FALSE
+
+/**
+ * OGMA SDK BASIC DATA TYPE
+ */
+typedef pfdep_int8 ogma_int8;
+typedef pfdep_uint8 ogma_uint8;
+typedef pfdep_int16 ogma_int16;
+typedef pfdep_uint16 ogma_uint16;
+typedef pfdep_int32 ogma_int32;
+typedef pfdep_uint32 ogma_uint32;
+typedef int ogma_int;
+typedef unsigned int ogma_uint;
+typedef pfdep_bool ogma_bool;
+typedef pfdep_char ogma_char;
+
+#ifdef PFDEP_INT64_AVAILABLE
+typedef signed long long ogma_int64;
+typedef unsigned long long ogma_uint64;
+#endif /* PFDEP_INT64_AVAILABLE*/
+
+#endif /* OGMA_BASIC_TYPE_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
new file mode 100644
index 000000000000..61335b96db77
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_VERSION_H
+#define OGMA_VERSION_H
+
+#define OGMA_VER_NETSEC (0x00050050UL)
+
+#define OGMA_INVALID_VER 0x0
+#define OGMA_VER_MAJOR_NUM(x) (x&0xffff0000UL)
+
+#endif /* OGMA_VERSION_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
new file mode 100644
index 000000000000..7b399beaedb2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+void ogma_set_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr,
+ ogma_uint32 value)
+{
+
+ ogma_uint32 cmd;
+
+ ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DATA,
+ value);
+
+ cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+}
+
+ogma_uint32 ogma_get_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr)
+{
+ ogma_uint32 cmd;
+
+ ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /*
+ * Argument check is omitted because this function is
+ * of private use only.
+ */
+
+ cmd = addr | OGMA_GMAC_CMD_ST_READ;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD,
+ cmd);
+
+ /*
+ * Waits until BUSY bit is cleared.
+ */
+ while ( ( ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_CMD)
+ & OGMA_GMAC_CMD_ST_BUSY)
+ != 0) {
+ ;
+ }
+ return ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DATA);
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
new file mode 100644
index 000000000000..a81b9249f4a2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
@@ -0,0 +1,52 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_ACCESS_H
+#define OGMA_BASIC_ACCESS_H
+
+#include "ogma_internal.h"
+
+static __inline void ogma_write_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 reg_addr,
+ ogma_uint32 value
+ )
+{
+
+ pfdep_iomem_write( (void *) ( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+ ( reg_addr << 2) ),
+ value);
+}
+
+static __inline ogma_uint32 ogma_read_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 reg_addr
+ )
+{
+
+ return ( ogma_uint32)pfdep_iomem_read( (void *)( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+ ( reg_addr << 2) ) );
+}
+
+void ogma_set_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr,
+ ogma_uint32 value);
+
+ogma_uint32 ogma_get_mac_reg (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 addr);
+
+#endif/* OGMA_BASIC_ACCESS_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
new file mode 100644
index 000000000000..a38aff3ce4a5
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
@@ -0,0 +1,1391 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_desc_ring_access_internal.h"
+
+
+const ogma_uint32 ogma_desc_start_reg_addr_upper[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DESC_START_UP,
+ OGMA_REG_ADDR_NRM_RX_DESC_START_UP,
+};
+
+const ogma_uint32 ogma_desc_start_reg_addr_lower[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DESC_START_LW,
+ OGMA_REG_ADDR_NRM_RX_DESC_START_LW,
+};
+
+const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN,
+ OGMA_REG_ADDR_NRM_RX_INTEN,
+};
+
+const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN_SET,
+ OGMA_REG_ADDR_NRM_RX_INTEN_SET,
+};
+
+const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_INTEN_CLR,
+ OGMA_REG_ADDR_NRM_RX_INTEN_CLR,
+};
+
+static const ogma_uint32 int_tmr_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_TXINT_TMR,
+ OGMA_REG_ADDR_NRM_RX_RXINT_TMR,
+};
+
+static const ogma_uint32 rx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ 0,
+ OGMA_REG_ADDR_NRM_RX_PKTCNT,
+};
+
+static const ogma_uint32 tx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_PKTCNT,
+ 0,
+
+};
+
+static const ogma_uint32 int_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT,
+ OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT,
+};
+
+static const ogma_uint32 tx_done_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+ OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT,
+ 0,
+};
+
+
+STATIC void ogma_set_tx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_bool first_flag,
+ ogma_bool last_flag,
+ ogma_bool trs_flag,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_set_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_get_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p);
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC void ogma_inc_desc_head_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment);
+
+STATIC void ogma_inc_desc_tail_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment);
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p
+ );
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+static __inline void ogma_desc_ring_cpy_to_mem(
+ void *dst_p,
+ void *src_p,
+ ogma_uint32 len)
+{
+ pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_cpy_from_mem(
+ void *dst_p,
+ void *src_p,
+ ogma_uint32 len)
+{
+ pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_memclr(
+ void *dst_p,
+ ogma_uint32 len)
+{
+ pfdep_memset(dst_p,0,len);
+}
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_alloc_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_desc_ring_t *desc_ring_p = &ctrl_p->desc_ring[ring_id];
+ ogma_desc_ring_param_t *desc_ring_param_p = &ctrl_p->desc_ring[ring_id].param;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p->param.desc_ring_param[ring_id].valid_flag) &&
+ ( ( ctrl_p->param.desc_ring_param[ring_id].entry_num <
+ OGMA_DESC_ENTRY_NUM_MIN) ||
+ ( ctrl_p->param.desc_ring_param[ring_id].entry_num >
+ OGMA_DESC_ENTRY_NUM_MAX) ) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Please set entry_num between %d and %d.\n",
+ OGMA_DESC_ENTRY_NUM_MIN, OGMA_DESC_ENTRY_NUM_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p->ring_id = ring_id;
+
+ pfdep_memcpy( desc_ring_param_p,
+ &ctrl_p->param.desc_ring_param[ring_id],
+ sizeof( ogma_desc_ring_param_t) );
+
+ if ( !desc_ring_param_p->valid_flag) {
+
+ desc_ring_p->desc_ring_phys_addr = ctrl_p->dummy_desc_entry_phys_addr;
+
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_upper[ring_id],
+ (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_lower[ring_id],
+ (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+ return OGMA_ERR_OK;
+ }
+
+ switch ( ring_id) {
+ case OGMA_DESC_RING_ID_NRM_TX:
+ desc_ring_p->tx_desc_ring_flag = OGMA_TRUE;
+ desc_ring_p->desc_entry_len = sizeof( ogma_tx_desc_entry_t);
+ break;
+
+ case OGMA_DESC_RING_ID_NRM_RX:
+ desc_ring_p->rx_desc_ring_flag = OGMA_TRUE;
+ desc_ring_p->desc_entry_len = sizeof( ogma_rx_desc_entry_t);
+ break;
+
+ default:
+ pfdep_assert(0);
+ }
+
+ if ( ( pfdep_err = pfdep_init_hard_lock ( &desc_ring_p->inten_reg_hard_lock) )
+ != PFDEP_ERR_OK) {
+ pfdep_memset( desc_ring_param_p,
+ 0,
+ sizeof( ogma_desc_ring_param_t) );
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to inten_reg_hard_lock's initialization.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ if ( ( pfdep_err = pfdep_init_soft_lock ( &desc_ring_p->soft_lock) )
+ != PFDEP_ERR_OK) {
+ pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+ pfdep_memset( desc_ring_param_p,
+ 0,
+ sizeof( ogma_desc_ring_param_t) );
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to soft_lock's initialization.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ if ( ( pfdep_err = pfdep_dma_malloc (
+ ( pfdep_dev_handle_t) ctrl_p->dev_handle,
+ ( pfdep_uint32) desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num,
+ ( void **) &desc_ring_p->desc_ring_cpu_addr,
+ ( pfdep_phys_addr_t *) &desc_ring_p->desc_ring_phys_addr) )
+ != PFDEP_ERR_OK) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to desc_ring entry memory allocation.\n");
+ goto err;
+ }
+
+ ogma_desc_ring_memclr(
+ desc_ring_p->desc_ring_cpu_addr,
+ ( ogma_uint32)desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num);
+
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_upper[ring_id],
+ (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+ ogma_write_reg( ctrl_p,
+ ogma_desc_start_reg_addr_lower[ring_id],
+ (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+ if ( ( desc_ring_p->frag_info_p =
+ pfdep_malloc( sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num) )
+ == NULL) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to fragment infomation memory allocation.\n");
+ goto err;
+ }
+
+ pfdep_memset(
+ desc_ring_p->frag_info_p,
+ 0,
+ sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num);
+
+ if ( ( desc_ring_p->priv_data_p =
+ pfdep_malloc( sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num) )
+ == NULL) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_alloc_desc_ring.\n"
+ "Failed to private data memory allocation.\n");
+ goto err;
+ }
+
+ pfdep_memset(
+ desc_ring_p->priv_data_p,
+ 0,
+ sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num);
+
+ return OGMA_ERR_OK;
+
+err:
+ ogma_free_desc_ring( ctrl_p, desc_ring_p);
+ return ogma_err;
+}
+
+void ogma_free_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ if ( !desc_ring_p->param.valid_flag) {
+ return ;
+ }
+ if ( ogma_is_pkt_desc_ring ( desc_ring_p) ) {
+ if ( ( desc_ring_p->desc_ring_cpu_addr != NULL) &&
+ ( desc_ring_p->frag_info_p != NULL) &&
+ ( desc_ring_p->priv_data_p != NULL) ) {
+ ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+ }
+ }
+ if ( desc_ring_p->desc_ring_cpu_addr != NULL) {
+ pfdep_dma_free( ctrl_p->dev_handle,
+ ( ogma_uint32)desc_ring_p->desc_entry_len *
+ desc_ring_p->param.entry_num,
+ desc_ring_p->desc_ring_cpu_addr,
+ desc_ring_p->desc_ring_phys_addr);
+ }
+
+ if ( desc_ring_p->frag_info_p != NULL) {
+ pfdep_free(desc_ring_p->frag_info_p);
+ }
+
+ if ( desc_ring_p->priv_data_p != NULL) {
+ pfdep_free( desc_ring_p->priv_data_p);
+ }
+
+ pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+
+ pfdep_uninit_soft_lock ( &desc_ring_p->soft_lock);
+
+ pfdep_memset( desc_ring_p, 0, sizeof( ogma_desc_ring_t) );
+}
+
+ogma_err_t ogma_setup_rx_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 idx;
+ ogma_frag_info_t frag_info= {0,0,0};
+
+ pfdep_err_t pfdep_err;
+ pfdep_pkt_handle_t tmp_pkt_handle;
+
+ frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+ for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+ if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+ ( pfdep_dev_handle_t)ctrl_p->dev_handle,
+ ( ogma_uint16)frag_info.len,
+ ( void **)&frag_info.addr,
+ ( pfdep_phys_addr_t *)&frag_info.phys_addr,
+ ( pfdep_pkt_handle_t *)&tmp_pkt_handle) )
+ != PFDEP_ERR_OK) {
+ ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_setup_rx_desc_ring.\n"
+ "Failed to rx packet memory allocation.\n");
+ return OGMA_ERR_ALLOC;
+ }
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ idx,
+ &frag_info,
+ tmp_pkt_handle);
+ }
+ return OGMA_ERR_OK;
+}
+
+void ogma_uninit_pkt_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 idx;
+ ogma_uint32 tmp;
+ ogma_bool last_flag;
+
+ for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+ if ( desc_ring_p->frag_info_p[idx].addr == NULL ) {
+ continue;
+ }
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+
+ last_flag = ( ( ( tmp >> 8) & 0x1) != 0);
+
+ pfdep_free_pkt_buf (
+ ctrl_p->dev_handle,
+ desc_ring_p->frag_info_p[idx].len,
+ desc_ring_p->frag_info_p[idx].addr,
+ desc_ring_p->frag_info_p[idx].phys_addr,
+ last_flag,
+ desc_ring_p->priv_data_p[idx].pkt_handle);
+ }
+
+ /* clear frag_info_p */
+ pfdep_memset( desc_ring_p->frag_info_p,
+ 0,
+ sizeof( ogma_frag_info_t) * desc_ring_p->param.entry_num);
+
+ /* clear pkt_handle_p */
+ pfdep_memset( desc_ring_p->priv_data_p,
+ 0,
+ sizeof( ogma_desc_entry_priv_t) * desc_ring_p->param.entry_num);
+
+ /* clear desc ring entry*/
+ ogma_desc_ring_memclr ( desc_ring_p->desc_ring_cpu_addr,
+ ( ogma_uint32)desc_ring_p->desc_entry_len *
+ desc_ring_p->param.entry_num);
+}
+
+STATIC void ogma_set_tx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_bool first_flag,
+ ogma_bool last_flag,
+ ogma_bool trs_flag,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_tx_desc_entry_t tx_desc_entry;
+ ogma_uint32 attr, i, *debug_desc_entry_p;
+
+ ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &tx_desc_entry, 0, sizeof( ogma_tx_desc_entry_t) );
+
+ attr = ( 1UL << OGMA_TX_PKT_DESC_RING_OWN_FIELD) |
+ ( desc_ring_p->ring_id << OGMA_TX_PKT_DESC_RING_DRID_FIELD) |
+ ( tx_pkt_ctrl_p->pass_through_flag <<
+ OGMA_TX_PKT_DESC_RING_PT_FIELD) |
+ ( tx_pkt_ctrl_p->target_desc_ring_id <<
+ OGMA_TX_PKT_DESC_RING_TDRID_FIELD) |
+ ( first_flag << OGMA_TX_PKT_DESC_RING_FS_FIELD) |
+ ( last_flag << OGMA_TX_PKT_DESC_RING_LS_FIELD) |
+ ( tx_pkt_ctrl_p->cksum_offload_flag <<
+ OGMA_TX_PKT_DESC_RING_CO_FIELD) |
+ ( tx_pkt_ctrl_p->tcp_seg_offload_flag <<
+ OGMA_TX_PKT_DESC_RING_SO_FIELD) |
+ ( trs_flag << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
+
+ if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+ attr |= ( 0x1U << OGMA_TX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+ }
+
+ tx_desc_entry.attr = attr;
+
+ tx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+ tx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+ tx_desc_entry.buf_len_info =
+ ( tx_pkt_ctrl_p->tcp_seg_len << 16) | frag_info_p->len;
+
+ ogma_desc_ring_cpy_to_mem( ( (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx) ),
+ ( void *)&tx_desc_entry,
+ desc_ring_p->desc_entry_len);
+
+ debug_desc_entry_p = ( ogma_uint32 *)&tx_desc_entry;
+
+ for ( i = 0; i < ( sizeof( ogma_tx_desc_entry_t) >> 2); i++) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%08x\n", debug_desc_entry_p[i]);
+ }
+
+ desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+ desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+ desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+ desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+
+}
+
+STATIC void ogma_set_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ const ogma_frag_info_t *frag_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_rx_desc_entry_t rx_desc_entry;
+
+ ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &rx_desc_entry, 0, sizeof ( ogma_rx_desc_entry_t) );
+
+ rx_desc_entry.attr = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
+ ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
+
+ rx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+ rx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+ rx_desc_entry.buf_len_info = frag_info_p->len;
+
+ if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+ rx_desc_entry.attr |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+ }
+
+ ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx + 4) ),
+ ( void *) ( ( pfdep_cpu_addr_t)&rx_desc_entry + 4),
+ ( ogma_uint32)( desc_ring_p->desc_entry_len - 4U) );
+
+ pfdep_write_mem_barrier();
+
+ ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx) ),
+ ( void *)&rx_desc_entry,
+ 4);
+
+ desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+ desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+ desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+ desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+}
+
+STATIC void ogma_get_rx_desc_entry (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p)
+{
+ ogma_uint32 *debug_desc_entry_p;
+ ogma_rx_desc_entry_t rx_desc_entry;
+
+ ogma_check_desc_own_sanity( ctrl_p, desc_ring_p, idx, 0);
+
+ pfdep_memset( &rx_desc_entry, 0, sizeof( ogma_rx_desc_entry_t) );
+ pfdep_memset( rx_pkt_info_p, 0, sizeof( ogma_rx_pkt_info_t) );
+
+ ogma_desc_ring_cpy_from_mem( &rx_desc_entry,
+ (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx),
+ desc_ring_p->desc_entry_len);
+
+ debug_desc_entry_p = (ogma_uint32 *)&rx_desc_entry;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%08x\n", *debug_desc_entry_p);
+
+ *len_p = rx_desc_entry.buf_len_info >> 16;
+
+ rx_pkt_info_p->fragmented_flag =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_FR_FIELD) & 0x1; /* FR*/
+
+ rx_pkt_info_p->err_flag =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ER_FIELD) & 0x1; /* ER */
+
+ rx_pkt_info_p->rx_cksum_result =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_CO_FIELD) & 0x3; /* CO */
+
+ rx_pkt_info_p->err_code =
+ ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD) &
+ OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK; /* Error Code */
+
+ pfdep_memcpy( frag_info_p,
+ &desc_ring_p->frag_info_p[idx],
+ sizeof(ogma_frag_info_t) );
+
+ *pkt_handle_p = desc_ring_p->priv_data_p[idx].pkt_handle;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+STATIC __inline ogma_uint16 ogma_calc_busy_entry_num (
+ ogma_uint16 head_idx,
+ ogma_uint16 tail_idx,
+ ogma_uint16 entry_num,
+ ogma_bool full_flag
+ )
+{
+
+ ogma_int16 busy_entry_num;
+
+ if (full_flag) {
+ busy_entry_num = entry_num;
+ } else if (head_idx >= tail_idx) {
+ busy_entry_num = head_idx - tail_idx;
+ } else {
+ busy_entry_num = entry_num + head_idx - tail_idx;
+ }
+
+ return busy_entry_num;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ ogma_uint32 tmp;
+
+ ogma_get_tx_done_num_sub( ctrl_p, desc_ring_p);
+
+ while( ( (desc_ring_p->tail_idx != desc_ring_p->head_idx) ||
+ desc_ring_p->full_flag) && ( desc_ring_p->tx_done_num != 0) ) {
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p,
+ desc_ring_p->tail_idx);
+
+ pfdep_free_pkt_buf (
+ ctrl_p->dev_handle,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].len,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].addr,
+ desc_ring_p->frag_info_p[desc_ring_p->tail_idx].phys_addr,
+ ( ( ( tmp >> OGMA_TX_PKT_DESC_RING_LS_FIELD) & 0x1) != 0),
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+ pfdep_memset( &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ 0,
+ sizeof( ogma_frag_info_t) );
+
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+ if ( ( tmp & ( 1UL << OGMA_TX_PKT_DESC_RING_LS_FIELD) ) != 0) {
+
+ pfdep_assert( desc_ring_p->tx_done_num != 0);
+
+ desc_ring_p->tx_done_num--;
+
+ }
+ }
+
+}
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+
+ while( desc_ring_p->full_flag ||
+ ( desc_ring_p->tail_idx != desc_ring_p->head_idx) ) {
+
+ ogma_set_rx_desc_entry(
+ ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+ --desc_ring_p->rx_num;
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+ }
+
+ pfdep_assert( desc_ring_p->rx_num == 0);/* error check*/
+
+}
+
+STATIC void ogma_inc_desc_head_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment)
+{
+ ogma_uint32 sum;
+
+ if ( ( desc_ring_p->tail_idx > desc_ring_p->head_idx) ||
+ desc_ring_p->full_flag) {
+ pfdep_assert( increment <=
+ ( desc_ring_p->tail_idx -
+ desc_ring_p->head_idx));
+ } else {
+ pfdep_assert( increment <=
+ ( desc_ring_p->param.entry_num +
+ desc_ring_p->tail_idx -
+ desc_ring_p->head_idx) );
+ }
+
+ sum = (ogma_uint32) desc_ring_p->head_idx + increment;
+
+ if ( sum >= desc_ring_p->param.entry_num) {
+ sum -= desc_ring_p->param.entry_num;
+ }
+
+ desc_ring_p->head_idx = ( ogma_uint16)sum;
+
+ if ( desc_ring_p->head_idx == desc_ring_p->tail_idx) {
+ desc_ring_p->full_flag = OGMA_TRUE;
+ }
+
+}
+
+STATIC void ogma_inc_desc_tail_idx (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 increment)
+{
+ ogma_uint32 sum;
+
+ if ( ( desc_ring_p->head_idx >= desc_ring_p->tail_idx) &&
+ ( !desc_ring_p->full_flag) ) {
+ pfdep_assert( increment <=
+ ( desc_ring_p->head_idx -
+ desc_ring_p->tail_idx) );
+ } else {
+ pfdep_assert( increment <=
+ ( desc_ring_p->param.entry_num +
+ desc_ring_p->head_idx -
+ desc_ring_p->tail_idx) );
+ }
+
+ sum = (ogma_uint32) desc_ring_p->tail_idx + increment;
+
+ if ( sum >= desc_ring_p->param.entry_num) {
+ sum -= desc_ring_p->param.entry_num;
+ }
+
+ desc_ring_p->tail_idx = ( ogma_uint16)sum;
+
+ desc_ring_p->full_flag = OGMA_FALSE;
+}
+
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint16 tx_avail_num;
+
+ if ( desc_ring_p->full_flag) {
+
+ tx_avail_num = 0;
+
+ } else if ( desc_ring_p->tail_idx > desc_ring_p->head_idx) {
+
+ tx_avail_num = desc_ring_p->tail_idx - desc_ring_p->head_idx;
+
+ } else {
+
+ tx_avail_num =
+ desc_ring_p->param.entry_num +
+ desc_ring_p->tail_idx -
+ desc_ring_p->head_idx;
+ }
+
+ return tx_avail_num;
+}
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ )
+{
+ ogma_uint32 value;
+
+ value = ogma_read_reg ( ctrl_p,
+ tx_done_pkt_cnt_reg_addr[desc_ring_p->ring_id] );
+
+ desc_ring_p->tx_done_num += value;
+
+ return desc_ring_p->tx_done_num;
+}
+
+
+ogma_err_t ogma_start_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_BUSY;
+ }
+
+ if ( desc_ring_p->rx_desc_ring_flag) {
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ OGMA_CH_IRQ_REG_RCV);
+
+ ogma_write_reg ( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ 1);
+ }
+
+ if ( desc_ring_p->tx_desc_ring_flag) {
+
+
+ value = OGMA_CH_IRQ_REG_EMPTY;
+
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ value);
+
+ ogma_write_reg ( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ 1);
+
+ }
+
+ desc_ring_p->running_flag = OGMA_TRUE;
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+
+ogma_err_t ogma_stop_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id] ) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_INVALID;
+ }
+
+ value = ( OGMA_CH_IRQ_REG_RCV |
+ OGMA_CH_IRQ_REG_EMPTY |
+ OGMA_CH_IRQ_REG_SND);
+
+ ogma_write_reg ( ctrl_p,
+ desc_ring_irq_inten_clr_reg_addr[ring_id],
+ value);
+
+ desc_ring_p->running_flag = OGMA_FALSE;
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_uint16 ogma_get_rx_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_uint32 result;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p = NULL;
+ ogma_desc_ring_id_t tmp_ring_id;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please set valid argument.\n");
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please set valid argument.\n");
+ return 0;
+ }
+
+ tmp_ring_id = ring_id;
+
+ if (! ctrl_p->desc_ring[tmp_ring_id].rx_desc_ring_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Please select rx packet desc ring or bulk desc ring.\n");
+ return 0;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_rx_num.\n"
+ "Failed to get soft lock.\n");
+ return 0;
+ }
+
+ result = ogma_read_reg( ctrl_p, rx_pkt_cnt_reg_addr[tmp_ring_id]);
+
+ desc_ring_p->rx_num += result;
+
+ if ( desc_ring_p->rx_desc_ring_flag && ( result != 0) ) {
+ ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, ( ogma_uint16)result);
+ }
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return desc_ring_p->rx_num;
+}
+
+
+ogma_uint16 ogma_get_tx_avail_num (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_uint16 result;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_id_t tmp_ring_id;
+ ogma_desc_ring_t *desc_ring_p = NULL;
+
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+ pfdep_err_t pfdep_err;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ||
+ ( !ctrl_p->desc_ring[ring_id].param.valid_flag) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select valid argument.\n");
+ return 0;
+ }
+
+ tmp_ring_id = ring_id;
+
+ if (! ctrl_p->desc_ring[tmp_ring_id].tx_desc_ring_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select tx packet desc ring or bulk desc ring.\n");
+ return 0;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Failed to get soft lock.\n");
+ return 0;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_tx_avail_num.\n"
+ "Please select running desc ring.\n");
+ return 0;
+ }
+
+ result = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return result;
+}
+
+ogma_err_t ogma_clean_tx_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ ogma_clean_tx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_OK;
+
+
+}
+
+ogma_err_t ogma_clean_rx_desc_ring (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ ogma_clean_rx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_tx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+ ogma_uint8 scat_num,
+ const ogma_frag_info_t *scat_info_p,
+ pfdep_pkt_handle_t pkt_handle
+ )
+{
+ ogma_uint i;
+ ogma_uint16 tx_avail_num;
+ ogma_uint32 sum_len = 0;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+ if ( ( ctrl_p == NULL) ||
+ ( tx_pkt_ctrl_p == NULL) ||
+ ( scat_info_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ {
+ if ( !ctrl_p->param.use_gmac_flag ||
+ ( tx_pkt_ctrl_p->target_desc_ring_id != OGMA_DESC_RING_ID_GMAC) ) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+
+ if ( tx_pkt_ctrl_p->tcp_seg_offload_flag &&
+ ( !tx_pkt_ctrl_p->cksum_offload_flag) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+ if ( tx_pkt_ctrl_p->tcp_seg_len == 0) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ctrl_p->param.use_jumbo_pkt_flag) {
+ if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_JUMBO_SEG_LEN_MAX) {
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_SEG_LEN_MAX) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ } else {
+ if ( tx_pkt_ctrl_p->tcp_seg_len != 0) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+
+ if ( scat_num == 0) {
+ return OGMA_ERR_RANGE;
+ }
+
+ for ( i = 0; i < scat_num; i++) {
+ if ( ( scat_info_p[i].len == 0) ||
+ ( scat_info_p[i].len > 0xffffU) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_set_tx_pkt_data.\n"
+ "Pleas check scat_info_p[%u].len.\n",
+ i);
+ return OGMA_ERR_DATA;
+ }
+ sum_len += scat_info_p[i].len;
+ }
+
+ if ( !tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+ if ( ctrl_p->param.use_jumbo_pkt_flag) {
+ if ( sum_len > OGMA_MAX_TX_JUMBO_PKT_LEN) {
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ if ( sum_len > OGMA_MAX_TX_PKT_LEN) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ ogma_err = OGMA_ERR_NOTAVAIL;
+ goto end;
+ }
+
+ tx_avail_num = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+ if ( scat_num > tx_avail_num ) {
+ ogma_err = OGMA_ERR_BUSY;
+ goto end;
+ }
+
+ for ( i = 0; i < scat_num; i++) {
+
+
+ ogma_set_tx_desc_entry(
+ ctrl_p,
+ desc_ring_p,
+ desc_ring_p->head_idx,
+ tx_pkt_ctrl_p,
+ ( i == 0),
+ ( i == ( scat_num - 1U) ),
+ OGMA_TRUE,
+ &scat_info_p[i],
+ pkt_handle);
+ ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, 1);
+ }
+
+ pfdep_write_mem_barrier();
+
+ ogma_write_reg( ctrl_p,
+ tx_pkt_cnt_reg_addr[ring_id],
+ (ogma_uint32)1);
+
+end:
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_get_rx_pkt_data (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_rx_pkt_info_t *rx_pkt_info_p,
+ ogma_frag_info_t *frag_info_p,
+ ogma_uint16 *len_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+ ogma_frag_info_t tmp_frag_info;
+
+ pfdep_err_t pfdep_err;
+ pfdep_pkt_handle_t tmp_pkt_handle;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+ if ( ( ctrl_p == NULL) ||
+ ( rx_pkt_info_p == NULL) ||
+ ( frag_info_p == NULL) ||
+ ( len_p == NULL) ||
+ ( pkt_handle_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+ return OGMA_ERR_PARAM;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ if ( ( pfdep_err = pfdep_acquire_soft_lock(
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( desc_ring_p->rx_num == 0 ) {
+ ogma_err = OGMA_ERR_INVALID;
+ goto end;
+ }
+
+ tmp_frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+ pfdep_read_mem_barrier();
+
+ if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+ ctrl_p->dev_handle,
+ tmp_frag_info.len,
+ &tmp_frag_info.addr,
+ &tmp_frag_info.phys_addr,
+ &tmp_pkt_handle) ) != PFDEP_ERR_OK) {
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+ desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+ ogma_err = OGMA_ERR_ALLOC;
+
+ } else {
+
+ ogma_get_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ rx_pkt_info_p,
+ frag_info_p,
+ len_p,
+ pkt_handle_p);
+
+
+ ogma_set_rx_desc_entry( ctrl_p,
+ desc_ring_p,
+ desc_ring_p->tail_idx,
+ &tmp_frag_info,
+ tmp_pkt_handle);
+ }
+
+ ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+ --desc_ring_p->rx_num;
+
+end:
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_set_irq_coalesce_param (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint16 int_pktcnt,
+ ogma_bool int_tmr_unit_ms_flag,
+ ogma_uint16 int_tmr_cnt
+ )
+{
+
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( int_pktcnt > OGMA_INT_PKTCNT_MAX) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id]) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ ogma_write_reg( ctrl_p,
+ int_pkt_cnt_reg_addr[ring_id],
+ int_pktcnt);
+
+ ogma_write_reg( ctrl_p,
+ int_tmr_reg_addr[ring_id],
+ ( ( ( ( ogma_uint32)int_tmr_unit_ms_flag) << 31) |
+ int_tmr_cnt) );
+
+ return ogma_err;
+
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
new file mode 100644
index 000000000000..34490e2d1c78
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
@@ -0,0 +1,111 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_DESC_RING_ACCESS_INTERNAL_H
+#define OGMA_DESC_RING_ACCESS_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "ogma_internal.h"
+
+#define OGMA_TX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_TX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_TX_PKT_DESC_RING_DRID_FIELD (24)
+#define OGMA_TX_PKT_DESC_RING_PT_FIELD (21)
+#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD (16)
+#define OGMA_TX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_TX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_TX_PKT_DESC_RING_CO_FIELD (7)
+#define OGMA_TX_PKT_DESC_RING_SO_FIELD (6)
+#define OGMA_TX_PKT_DESC_RING_USRKEY_FIELD (5)
+#define OGMA_TX_PKT_DESC_RING_TRS_FIELD (4)
+
+#define OGMA_RX_PKT_DESC_RING_OWN_FIELD (31)
+#define OGMA_RX_PKT_DESC_RING_LD_FIELD (30)
+#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD (24)
+#define OGMA_RX_PKT_DESC_RING_FR_FIELD (23)
+#define OGMA_RX_PKT_DESC_RING_ER_FIELD (21)
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
+#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD (12)
+#define OGMA_RX_PKT_DESC_RING_FS_FIELD (9)
+#define OGMA_RX_PKT_DESC_RING_LS_FIELD (8)
+#define OGMA_RX_PKT_DESC_RING_CO_FIELD (6)
+
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
+
+#define OGMA_MAX_TX_PKT_LEN 1518U
+#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
+
+typedef struct ogma_tx_desc_entry_s ogma_tx_desc_entry_t;
+typedef struct ogma_rx_desc_entry_s ogma_rx_desc_entry_t;
+
+struct ogma_tx_desc_entry_s{
+
+ ogma_uint32 attr;
+
+ ogma_uint32 data_buf_addr_upper;
+
+ ogma_uint32 data_buf_addr_lower;
+
+ ogma_uint32 buf_len_info;
+};
+
+struct ogma_rx_desc_entry_s{
+
+ ogma_uint32 attr;
+
+ ogma_uint32 data_buf_addr_upper;
+
+ ogma_uint32 data_buf_addr_lower;
+
+ ogma_uint32 buf_len_info;
+};
+
+static __inline ogma_bool ogma_is_pkt_desc_ring (
+ const ogma_desc_ring_t *desc_ring_p
+ )
+{
+ return ( desc_ring_p->rx_desc_ring_flag ||
+ desc_ring_p->tx_desc_ring_flag);
+}
+
+static __inline ogma_uint32 ogma_get_desc_ring_attr (
+ const ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx
+ )
+{
+ ogma_uint32 *addr =
+ (ogma_uint32 *)
+ ((pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+ desc_ring_p->desc_entry_len * idx);
+
+ return *addr;
+}
+
+
+
+static __inline void ogma_check_desc_own_sanity (
+ ogma_ctrl_t *ctrl_p,
+ const ogma_desc_ring_t *desc_ring_p,
+ ogma_uint16 idx,
+ ogma_uint expected_own)
+{
+ ogma_uint32 tmp;
+ ( void)ctrl_p; /* Suppress compiler warning */
+
+ tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+ pfdep_assert( ( tmp >> 31) == expected_own);
+}
+
+#endif /* OGMA_DESC_RING_ACCESS_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
new file mode 100644
index 000000000000..d08bb53a54e8
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
@@ -0,0 +1,1454 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+
+/**
+ * Clock range index for F_GMAC4MT::GAR::CR field.
+ */
+#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
+#else
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
+#endif
+
+
+/**********************************************************************
+ * Local function declarations
+ **********************************************************************/
+static void ogma_set_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ );
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ );
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p);
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+static void ogma_set_phy_target_mmd_reg_addr (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+static void ogma_set_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ );
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ );
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_start_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ pfdep_err_t pfdep_err;
+ ogma_err_t ogma_err;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( !ctrl_p->gmac_mode_valid_flag) {
+ return OGMA_ERR_INVALID;
+ }
+
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+
+ if ( ctrl_p->gmac_rx_running_flag &&
+ ctrl_p->gmac_tx_running_flag) {
+ return OGMA_ERR_OK;
+ }
+
+
+ if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) &&
+ !tx_flag) {
+ return OGMA_ERR_OK;
+ }
+
+ if ( ( tx_flag && ctrl_p->gmac_tx_running_flag) &&
+ !rx_flag ) {
+ return OGMA_ERR_OK;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ if ( (! ctrl_p->gmac_rx_running_flag) &&
+ (! ctrl_p->gmac_tx_running_flag) ) {
+
+ /* Initializes F_GMAC4MT */
+ if ( ctrl_p->gmac_mode.link_speed ==
+ OGMA_PHY_LINK_SPEED_1G) {
+ /* Writes 0 to FGMAC4 MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ 0);
+ } else {
+ /* Writes PS bit to FGMAC4 MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ OGMA_GMAC_MCR_10M_HALF);/* 10M half Reset */
+ }
+
+ /* F_GMAC4MT soft reset*/
+ if ( ( ogma_err = ogma_softreset_gmac( ctrl_p)) != OGMA_ERR_OK) {
+ return ogma_err;
+ }
+
+ /* MAC desc soft reset */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
+ OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
+
+ /* Wait MAC desc soft reset */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_start_gmac.\n");
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for MAC desc soft reset error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Check MAC desc soft reset done */
+ if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_SOFT_RST) &
+ OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "ogma_start_gmac():MAC desc soft reset timeout. Try Again.\n");
+
+ return OGMA_ERR_AGAIN;
+ }
+
+ /* MAC desc init */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_INIT,
+ OGMA_MAC_DESC_INIT_REG_INIT);
+
+ /* Wait MAC desc init done */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_start_gmac().\n");
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for MAC desc init done error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Check MAC desc init done */
+ if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT) &
+ OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "ogma_start_gmac():MAC desc init timeout. Try Again.\n");
+
+ return OGMA_ERR_AGAIN;
+ }
+
+ /* set BMR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_COMMON);
+ /* set RDLAR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_RDLAR,
+ OGMA_GMAC_RDLAR_REG_COMMON);
+ /* set TDLAR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_TDLAR,
+ OGMA_GMAC_TDLAR_REG_COMMON);
+ /* set MFFR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MFFR,
+ 0x80000001UL);
+
+ /* calc MCR setting val */
+ value = ( ctrl_p->gmac_mode.half_duplex_flag ?
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
+
+ if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
+ value |= OGMA_GMAC_MCR_REG_PS;
+ }
+
+ if ( ( ctrl_p->param.gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_GMII ) &&
+ ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
+ value |= OGMA_GMAC_MCR_REG_FES;
+ }
+ /* set CST bit */
+ value |= OGMA_GMAC_MCR_REG_CST;
+
+ /* set JE bit */
+ value |= OGMA_GMAC_MCR_REG_JE;
+
+ if ( ctrl_p->param.gmac_config.phy_interface ==
+ OGMA_PHY_INTERFACE_RGMII) {
+ /* set ignore in-band-status watch option. force tx clk out. */
+ value |= 0x40000000U;
+ }
+
+ /* set MCR */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_MCR,
+ value);
+
+ if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
+ /* Set Flow Control Threshold */
+ value =
+ ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
+ ctrl_p->gmac_mode.flow_ctrl_start_threshold;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_FLOW_TH,
+ value);
+ /* Set Flow Control Threshold F_GMAC4MT*/
+ value =
+ ( ctrl_p->gmac_mode.pause_time << 16) |
+ OGMA_GMAC_FCR_REG_RFE |
+ OGMA_GMAC_FCR_REG_TFE;
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_FCR,
+ value);
+ }
+
+ }
+
+ if ( ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) ||
+ ( tx_flag && (! ctrl_p->gmac_tx_running_flag) )
+ ) {
+ /* Read F_GMAC4MT OMR*/
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR);
+
+ if ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) {
+ value |= OGMA_GMAC_OMR_REG_SR;
+ ctrl_p->gmac_rx_running_flag = OGMA_TRUE;
+ }
+
+ if ( tx_flag && (! ctrl_p->gmac_tx_running_flag) ) {
+ value |= OGMA_GMAC_OMR_REG_ST;
+ ctrl_p->gmac_tx_running_flag = OGMA_TRUE;
+ }
+
+ /* set OMR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR,
+ value);
+
+ }
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_stop_gmac (
+ ogma_handle_t ogma_handle,
+ ogma_bool rx_flag,
+ ogma_bool tx_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+
+ if ( ( !rx_flag) && ( !tx_flag) ) {
+ return OGMA_ERR_OK;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) ||
+ ( tx_flag && ctrl_p->gmac_tx_running_flag) ) {
+ /* Read F_GMAC4MT OMR*/
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR);
+
+ if ( rx_flag && ctrl_p->gmac_rx_running_flag) {
+ value &= (~OGMA_GMAC_OMR_REG_SR);
+ ctrl_p->gmac_rx_running_flag = OGMA_FALSE;
+ }
+
+ if ( tx_flag && ctrl_p->gmac_tx_running_flag) {
+ value &= (~OGMA_GMAC_OMR_REG_ST);
+ ctrl_p->gmac_tx_running_flag = OGMA_FALSE;
+ }
+
+ /* set F_GMAC4MT OMR*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_OMR,
+ value);
+ }
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+ ogma_dump_gmac_stat (ctrl_p);
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_gmac_mode (
+ ogma_handle_t ogma_handle,
+ const ogma_gmac_mode_t *gmac_mode_p
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( gmac_mode_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ if ( ( ctrl_p->gmac_rx_running_flag) ||
+ ( ctrl_p->gmac_tx_running_flag) ) {
+ return OGMA_ERR_BUSY;
+ }
+
+ if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G ) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
+ ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
+ ( gmac_mode_p->half_duplex_flag) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->half_duplex_flag &&
+ gmac_mode_p->flow_ctrl_enable_flag) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->flow_ctrl_enable_flag) {
+
+ if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
+ ( gmac_mode_p->flow_ctrl_start_threshold >
+ OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
+ gmac_mode_p->flow_ctrl_start_threshold) ||
+ ( gmac_mode_p->flow_ctrl_stop_threshold >
+ OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
+ return OGMA_ERR_DATA;
+ }
+
+ if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
+ return OGMA_ERR_DATA;
+ }
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "%s call.\n", __func__);
+
+ pfdep_memcpy( ( void *)&ctrl_p->gmac_mode,
+ ( void *)gmac_mode_p,
+ sizeof( ogma_gmac_mode_t) );
+
+ ctrl_p->gmac_mode_valid_flag = OGMA_TRUE;
+
+
+ return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ )
+{
+
+ ogma_uint32 cmd;
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GDR,
+ value);
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+ ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+ ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+ OGMA_GMAC_GAR_REG_GW |
+ OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+}
+
+void ogma_set_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr,
+ ogma_uint16 value
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if (( ctrl_p == NULL)
+ || ( !ctrl_p->param.use_gmac_flag)
+ || ( phy_addr >= 32)
+ || ( reg_addr >= 32) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_set_phy_reg.\nPlease set valid argument.\n");
+ return;
+ }
+
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ )
+{
+
+ ogma_uint32 cmd;
+
+ cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+ ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+ ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+ OGMA_GMAC_GAR_REG_GB);
+
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_GAR,
+ cmd);
+
+ while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+ OGMA_GMAC_GAR_REG_GB)
+ != 0) {
+ ;
+ }
+ return (ogma_uint16)ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GDR);
+
+}
+
+ogma_uint16 ogma_get_phy_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 reg_addr
+ )
+{
+ ogma_uint16 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL)
+ || ( !ctrl_p->param.use_gmac_flag)
+ || ( phy_addr >= 32)
+ || ( reg_addr >= 32) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_phy_reg.\nPlease set valid argument.\n");
+ return 0;
+ }
+
+ value = ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr);
+
+
+ return value;
+}
+
+#if ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) )
+static const struct {
+ ogma_uint32 addr;
+ ogma_char *name_p;
+} ogma_gmac_mmc_reg_info[] = {
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_RX , "MMC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_TX , "MMC_INTR_TX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX , "MMC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX , "MMC_INTR_MASK_TX"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB , "TXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB , "TXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB , "TX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB , "TX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB , "TXUNICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR , "TXUNDERFLOWERROR"},
+ {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G , "TXSINGLECOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXMULTICOL_G , "TXMULTICOL_G"},
+ {OGMA_GMAC_REG_ADDR_TXDEFERRED , "TXDEFERRED"},
+ {OGMA_GMAC_REG_ADDR_TXLATECOL , "TXLATECOL"},
+ {OGMA_GMAC_REG_ADDR_TXEXESSCOL , "TXEXESSCOL"},
+ {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR , "TXCARRIERERRROR"},
+ {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G , "TXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G , "TXFRAMECOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_TXEXECESSDEF , "TXEXECESSDEF"},
+ {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES , "TXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G , "TXVLANFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB , "RXFRAMECOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB , "RXOCTETCOUNT_GB"},
+ {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G , "RXOCTETCOUNT_G"},
+ {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXCRCERROR , "RXCRCERROR"},
+ {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR , "RXALLIGNMENTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXRUNTERROR , "RXRUNTERROR"},
+ {OGMA_GMAC_REG_ADDR_RXJABBERERROR , "RXJABBERERROR"},
+ {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G , "RXUNDERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G , "RXOVERSIZE_G"},
+ {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB , "RX64OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB , "RX65TO127OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
+ {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G , "RXUNICASTFRAMES_G"},
+ {OGMA_GMAC_REG_ADDR_RXLENGTHERROR , "RXLENGTHERROR"},
+ {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE , "RXOUTOFRANGETYPE"},
+ {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES , "RXPAUSEFRAMES"},
+ {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW , "RXFIFOOVERFLOW"},
+ {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB , "RXVLANFRAMES_GB"},
+ {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR , "RXWATCHDOGERROR"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
+ {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX , "MMC_IPC_INTR_RX"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS , "RXIPV4_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS , "RXIPV4_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS , "RXIPV4_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS , "RXIPV4_FRAG_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS , "RXIPV4_UDSBL_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS , "RXIPV6_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS , "RXIPV6_HDRERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS , "RXIPV6_NOPAY_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS , "RXUDP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS , "RXUDP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS , "RXTCP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS , "RXTCP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS , "RXICMP_GD_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS , "RXICMP_ERR_FRMS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS , "RXIPV4_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS , "RXIPV4_FRAG_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS , "RXIPV6_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS , "RXUDP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS , "RXUDP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS , "RXTCP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS , "RXTCP_ERR_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS , "RXICMP_GD_OCTETS"},
+ {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS , "RXICMP_ERR_OCTETS"}
+};
+#endif /* ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) ) */
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p)
+{
+
+ ogma_uint i;
+
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "Dumping GMAC statistics registers(MMC registers):\n");
+
+ for (i = 0;
+ i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
+ i++) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ " %s => 0x%08x\n",
+ ogma_gmac_mmc_reg_info[i].name_p,
+ ( unsigned long)ogma_get_mac_reg(ctrl_p,
+ ogma_gmac_mmc_reg_info[i].addr));
+ }
+
+
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+}
+
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+ogma_err_t ogma_get_gmac_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool *valid_flag_p,
+ ogma_gmac_mode_t *gmac_mode_p,
+ ogma_bool *rx_running_flag_p,
+ ogma_bool *tx_running_flag_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( valid_flag_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ( ctrl_p == NULL) ||
+ ( gmac_mode_p == NULL) ||
+ ( rx_running_flag_p == NULL) ||
+ ( tx_running_flag_p == NULL) ) {
+ *valid_flag_p = OGMA_FALSE;
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ *valid_flag_p = OGMA_FALSE;
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+
+ *valid_flag_p = ctrl_p->gmac_mode_valid_flag;
+
+ *rx_running_flag_p = ctrl_p->gmac_rx_running_flag;
+ *tx_running_flag_p = ctrl_p->gmac_tx_running_flag;
+
+ pfdep_memcpy( ( void *)gmac_mode_p,
+ ( const void *)&ctrl_p->gmac_mode,
+ sizeof( ogma_gmac_mode_t) );
+
+
+ return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_target_mmd_reg_addr (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ ogma_uint32 cmd;
+
+ /* set MMD ADDR */
+ cmd = ( ogma_uint32)dev_addr;
+
+ /*set command to MMD access control register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+
+ /* set MMD access address data register Write reg_addr */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr);
+
+ /* write value to MMD ADDR */
+ cmd = ( (1U << 14) | dev_addr);
+
+ /* set command to MMD access control register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+}
+
+static void ogma_set_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ )
+{
+ /* set target mmd reg_addr */
+ ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+ /* Write value to MMD access address data register */
+ ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ /* set target mmd reg_addr */
+ ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+ /* Read value for MMD access address data register */
+ return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD);
+}
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* set value tp LSIPCR Register */
+ ogma_set_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_LPICSR, value);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read LSIPCR Register */
+ *value_p = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPICSR);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 ls_timer_ms,
+ ogma_uint16 tw_timer_ms
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ls_timer_ms > 1024U) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* make LPICTR value*/
+ value = ( ( ( ogma_uint32)ls_timer_ms << OGMA_GMAC_LPITCR_REG_LIT) |
+ ( tw_timer_ms << OGMA_GMAC_LPITCR_REG_TWT) );
+
+ /* Write timer value to LSIPCR Register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPITCR,
+ value);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint16 *ls_timer_ms_p,
+ ogma_uint16 *tw_timer_ms_p
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ls_timer_ms_p == NULL) ||
+ ( tw_timer_ms_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read timer value for LSIPCR Register */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_LPITCR);
+
+ /* make ls_timer_ms value*/
+ *ls_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_LIT) &
+ OGMA_GMAC_LPITCR_REG_MASK_LIT);
+
+ /* make tw_timer_ms value*/
+ *tw_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_TWT) &
+ OGMA_GMAC_LPITCR_REG_MASK_TWT);
+
+
+ return OGMA_ERR_OK;
+}
+
+void ogma_set_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr,
+ ogma_uint16 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return;
+ }
+
+ if ( ( phy_addr > 31U) ||
+ ( dev_addr > 31U) ) {
+ return;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return;
+ }
+
+ ogma_set_phy_mmd_reg_sub ( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr,
+ value);
+
+
+ return;
+}
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_uint8 dev_addr,
+ ogma_uint16 reg_addr
+ )
+{
+ ogma_uint16 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ if ( ( phy_addr > 31U) ||
+ ( dev_addr > 31U) ) {
+ return 0;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return 0;
+ }
+
+ value = ogma_get_phy_mmd_reg_sub ( ctrl_p,
+ phy_addr,
+ dev_addr,
+ reg_addr);
+
+
+ return value;
+}
+
+ogma_err_t ogma_get_phy_link_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint8 phy_addr,
+ ogma_phy_link_status_t *phy_link_status_p
+ )
+{
+ ogma_uint32 value, tmp, exp;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( phy_link_status_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( phy_addr >= 32) {
+ return OGMA_ERR_RANGE;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) );
+
+ /* Read PHY CONTROL Register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONTROL);
+
+ /* Read PHY STATUS Register */
+ value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+ /* check latched_link_down_flag */
+ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) == 0) {
+ phy_link_status_p->latched_link_down_flag = OGMA_TRUE;
+
+ /* Read PHY STATUS Register */
+ value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "CONTROL Register value %08x\n", tmp);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "PHY STATUS register value %08x\n", value);
+
+ /* Check Current Link Status */
+ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) != 0 ) {
+ phy_link_status_p->up_flag = OGMA_TRUE;
+ }
+
+ /* check Auto-Negotiation Enable */
+ if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE) ) != 0) &&
+ ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY) ) != 0) ) {
+ phy_link_status_p->auto_nego_enable_flag = OGMA_TRUE;
+ }
+
+ /* Check Current Autonegotiation Complete Status */
+ if ( phy_link_status_p->up_flag &&
+ phy_link_status_p->auto_nego_enable_flag &&
+ ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP) ) != 0) ) {
+ phy_link_status_p->auto_nego_complete_flag = OGMA_TRUE;
+ }
+
+ /* start Check Current Link Speed */
+ if ( phy_link_status_p->up_flag) {
+
+ if ( phy_link_status_p->auto_nego_enable_flag == OGMA_FALSE) {
+
+ /* Speed check */
+ if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) == 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ } else if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) == 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ } else {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+ }
+
+ /* Duplex check */
+ if ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_DUPLEX_MODE) ) == 0) {
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+ }
+
+ } else if ( phy_link_status_p->auto_nego_complete_flag == OGMA_TRUE) {
+ /* case auto_nego_enable_flag TRUE && auto_nego_complete_flag TRUE */
+
+ /* Read MASTER-SLAVE Control Register */
+ value = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL);
+
+ /* Read MASTER-SLAVE Status Register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS);
+
+ /* Check Current Link Speed */
+ if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_FULL) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_FULL) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ } else if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_HALF) ) != 0) &&
+ ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_HALF) ) != 0) ) {
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+ } else {
+
+ /* Read Auto-Negotiation Advertisement register */
+ value = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY);
+
+ /* Read Auto-Negotiation Link Partner Base Page Ability register */
+ tmp = ogma_get_phy_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY);
+
+ value = ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) &
+ OGMA_PHY_ANA_REG_TAF_MASK);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "TAF value %08x\n", value);
+
+ if ( value & OGMA_PHY_TAF_REG_100BASE_FULL) { /* 100M full */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ } else if ( value & OGMA_PHY_TAF_REG_100BASE_HALF) { /* 100M half */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+ } else if ( value & OGMA_PHY_TAF_REG_10BASE_FULL) { /* 10M full */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+ } else { /* value = OGMA_PHY_TAF_REG_10BASE_HALF 10M Half */
+
+ phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+ phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+ }
+
+ }
+ }
+ } /* End Check Current Link Speed */
+
+ /* Check LPI Capable */
+ if ( phy_link_status_p->up_flag &&
+ phy_link_status_p->auto_nego_complete_flag &&
+ phy_link_status_p->link_speed != OGMA_PHY_LINK_SPEED_10M &&
+ phy_link_status_p->half_duplex_flag == OGMA_FALSE &&
+ ctrl_p->param.gmac_config.phy_interface != OGMA_PHY_INTERFACE_RMII) {
+
+ /* Read EEE advertisement register */
+ value = ogma_get_phy_mmd_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+ OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE);
+
+ /* Read EEE link partner ability register */
+ tmp = ogma_get_phy_mmd_reg_sub( ctrl_p,
+ phy_addr,
+ OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+ OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY);
+
+ exp = ( ( phy_link_status_p->link_speed == OGMA_PHY_LINK_SPEED_1G) ?
+ OGMA_PHY_AUTO_NEGO_1000BASE_EEE:
+ OGMA_PHY_AUTO_NEGO_100BASE_EEE);
+
+ /* Check EEE Advertise and EEE LP Ability */
+ if ( ( value & tmp & exp) != 0 ) {
+ phy_link_status_p->lpi_capable_flag = OGMA_TRUE;
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE advertisement register value %08x\n",
+ value);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE link partner ability register value %08x\n",
+ tmp);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "EEE LPI EXP value %08x\n",
+ exp);
+ }
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->latched_link_down_flag %u\n",
+ phy_link_status_p->latched_link_down_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->up_flag %u\n",
+ phy_link_status_p->up_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->auto_nego_enable_flag %u\n",
+ phy_link_status_p->auto_nego_enable_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->auto_nego_complete_flag %u\n",
+ phy_link_status_p->auto_nego_complete_flag);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->link_speed %u\n",
+ phy_link_status_p->link_speed);
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+ "phy_link_status_p->lpi_capable_flag %u\n",
+ phy_link_status_p->lpi_capable_flag);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return gmac_int_sbd_regs;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return gmac_int_sbd_regs;
+ }
+
+ /* Read IER register */
+ gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Read IMR register */
+ gmac_int_sbd_regs.extended = ( ( ~( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR) ) ) &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+
+
+
+ return gmac_int_sbd_regs;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status_non_clear (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return gmac_int_sbd_regs;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return gmac_int_sbd_regs;
+ }
+
+ /* Read SR register */
+ gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_SR);
+
+ /* Read ISR register */
+ gmac_int_sbd_regs.extended = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_ISR);
+
+ if ( mask_flag) {
+
+ /* Read IER register */
+ gmac_int_sbd_regs.base &= ( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER) |
+ ( ~OGMA_GMAC_INT_SBD_IRQ_IER_ALL) );
+ /* Read IMR register */
+ gmac_int_sbd_regs.extended &= ( ( ~( ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR) ) ) &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+ }
+
+
+ return gmac_int_sbd_regs;
+}
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Write Clear SR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_SR,
+ ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read IER register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Write IER register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER,
+ ( value | ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_IER_ALL) ) );
+
+ /* Read IMR register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR);
+ /* Write IMR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR,
+ ( value & ( ~( int_sbd_regs.extended &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) ) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+ ogma_handle_t ogma_handle,
+ ogma_gmac_int_sbd_regs_t int_sbd_regs
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read IER register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER);
+ /* Write IER register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IER,
+ ( value & ( ~(int_sbd_regs.base) ) ) );
+
+ /* Read IMR register for No Change Value Keep */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR);
+ /* Write IMR register */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_IMR,
+ ( value | ( int_sbd_regs.extended &
+ OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) );
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ){
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->param.use_gmac_flag) {
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Read RGMII Status Register */
+ *value_p = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_RSR);
+
+
+ return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 *value_p,
+ ogma_bool reset_flag
+ )
+{
+
+ ogma_uint i;
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) ||
+ ( value_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+
+ for ( i = 0;
+ i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0] );
+ i++) {
+
+ value_p[i] = ogma_get_mac_reg(ctrl_p,
+ ogma_gmac_mmc_reg_info[i].addr);
+ }
+
+ if ( reset_flag) {
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+ }
+
+
+ return OGMA_ERR_OK;
+}
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+
+ /* Reset all counters. */
+ ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_softreset_gmac (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_uint32 value;
+ pfdep_err_t pfdep_err;
+
+ /* F_GMAC4MT soft reset*/
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_RESET);
+ /* Wait soft reset */
+ pfdep_err = pfdep_msleep( 1);
+
+ if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "Wait for BMR soft reset error.\n");
+
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ /* Read F_GMAC4MT BMR */
+ value = ogma_get_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR);
+
+ /* check software reset result*/
+ if ( value & OGMA_GMAC_BMR_REG_SWR) {
+ return OGMA_ERR_AGAIN;
+ }
+
+ return OGMA_ERR_OK;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
new file mode 100644
index 000000000000..e2e25c71abaa
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
@@ -0,0 +1,210 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_INTERNAL_H
+#define OGMA_INTERNAL_H
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+#include "ogma_reg.h"
+#include "pfdep.h"
+
+/* Just a million to prevent typing errors. */
+#define OGMA_CLK_MHZ (1000000)
+
+#define OGMA_INSTANCE_NUM_MAX 1
+
+#define OGMA_RX_PKT_BUF_LEN 1522
+#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
+#define OGMA_DUMMY_DESC_ENTRY_LEN 48
+
+#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
+
+extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
+
+typedef struct ogma_ctrl_s ogma_ctrl_t;
+typedef struct ogma_desc_ring_s ogma_desc_ring_t;
+typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
+typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
+
+struct ogma_clk_ctrl_s{
+ ogma_uint8 mac_req_num;
+};
+
+
+struct ogma_desc_ring_s{
+
+ ogma_desc_ring_id_t ring_id;
+
+ ogma_desc_ring_param_t param;
+
+ ogma_uint rx_desc_ring_flag:1;
+
+ ogma_uint tx_desc_ring_flag:1;
+
+ ogma_uint running_flag:1;
+
+ ogma_uint full_flag:1;
+
+ ogma_uint8 desc_entry_len;
+
+ ogma_uint16 head_idx;
+
+ ogma_uint16 tail_idx;
+
+ ogma_uint16 rx_num;
+
+ ogma_uint16 tx_done_num;
+
+ pfdep_hard_lock_t inten_reg_hard_lock;
+
+ pfdep_soft_lock_t soft_lock;
+
+ void *desc_ring_cpu_addr;
+
+ pfdep_phys_addr_t desc_ring_phys_addr;
+
+ ogma_frag_info_t *frag_info_p;
+
+ ogma_desc_entry_priv_t *priv_data_p;
+};
+
+struct ogma_ctrl_s{
+ ogma_ctrl_t *next_p;
+
+ ogma_uint core_enabled_flag:1;
+
+ ogma_uint gmac_rx_running_flag:1;
+
+ ogma_uint gmac_tx_running_flag:1;
+
+ ogma_uint gmac_mode_valid_flag:1;
+
+ ogma_uint normal_desc_ring_valid:1;
+
+ void *base_addr;
+
+ pfdep_dev_handle_t dev_handle;
+
+ ogma_param_t param;
+
+ ogma_clk_ctrl_t clk_ctrl;
+
+ ogma_uint32 rx_pkt_buf_len;
+
+ ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
+
+ ogma_gmac_mode_t gmac_mode;
+
+ pfdep_hard_lock_t inten_reg_hard_lock;
+
+ pfdep_hard_lock_t clk_ctrl_hard_lock;
+
+ void *dummy_desc_entry_addr;
+
+ pfdep_phys_addr_t dummy_desc_entry_phys_addr;
+
+#ifdef OGMA_CONFIG_REC_STAT
+ /**
+ * Statistics information.
+ *
+ * Note: Since mutual access exclusion is omitted,
+ * these values might be inaccurate.
+ */
+ ogma_stat_info_t stat_info;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+};
+
+union ogma_desc_entry_priv_u{
+ pfdep_pkt_handle_t pkt_handle;
+};
+
+/*****************************************************************
+ *****************************************************************
+ *****************************************************************/
+
+/**
+ *
+ */
+ogma_err_t ogma_alloc_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_id_t ring_idx
+ );
+/**
+ *
+ */
+void ogma_free_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+ogma_err_t ogma_setup_rx_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+void ogma_uninit_pkt_desc_ring (
+ ogma_ctrl_t *ctrl_p,
+ ogma_desc_ring_t *desc_ring_p
+ );
+
+/**
+ *
+ */
+void ogma_push_clk_req (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ );
+
+void ogma_pop_clk_req(
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ );
+
+
+ogma_err_t ogma_softreset_gmac (
+ ogma_ctrl_t *ctrl_p
+ );
+
+#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
+#include "ogma_basic_access.h"
+/*include for ogma_read_reg*/
+static __inline void ogma_check_clk_supply (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ ogma_uint32 value;
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
+
+ pfdep_assert( ( ( value & domain ) == domain) );
+}
+
+#else
+
+#define ogma_check_clk_supply( ctrl_p, domain)
+
+#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
+
+#endif /* OGMA_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
new file mode 100644
index 000000000000..3c54c63126a7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
@@ -0,0 +1,1385 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_misc_internal.h"
+
+#include <Library/IoLib.h>
+
+ogma_global_t ogma_global = {
+ OGMA_FALSE,
+ 0,
+ NULL
+};
+
+
+static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
+static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
+
+static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_STATUS,
+ OGMA_REG_ADDR_NRM_RX_STATUS,
+};
+
+static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+ OGMA_REG_ADDR_NRM_TX_CONFIG,
+ OGMA_REG_ADDR_NRM_RX_CONFIG,
+
+};
+
+
+/* Internal function definition*/
+#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
+STATIC void ogma_set_clk_en_reg (
+ ogma_ctrl_t *ctrl_p
+ );
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_global_init ( void);
+
+STATIC ogma_err_t ogma_probe_hardware (
+ void *base_addr
+ );
+
+STATIC void ogma_reset_hardware (
+ ogma_ctrl_t *ctrl_p
+ );
+
+STATIC void ogma_set_microcode(
+ ogma_ctrl_t *ctrl_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len
+ );
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+ const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+ );
+
+STATIC void ogma_internal_terminate (
+ ogma_ctrl_t *ctrl_p
+ );
+
+#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
+
+#define ogma_set_clk_en_reg( ctrl_p)
+
+#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_set_clk_en_reg (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_uint32 value = 0;
+
+ if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
+ value |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
+}
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+
+void ogma_push_clk_req (
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+ pfdep_acquire_hard_lock (
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+
+ if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+ ++ctrl_p->clk_ctrl.mac_req_num;
+ }
+
+ ogma_set_clk_en_reg( ctrl_p);
+
+ pfdep_release_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+}
+
+void ogma_pop_clk_req(
+ ogma_ctrl_t *ctrl_p,
+ ogma_uint32 domain
+ )
+{
+ pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+ pfdep_acquire_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+
+ if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+ --ctrl_p->clk_ctrl.mac_req_num;
+ }
+
+ ogma_set_clk_en_reg( ctrl_p);
+
+ pfdep_release_hard_lock(
+ &ctrl_p->clk_ctrl_hard_lock,
+ &clk_ctrl_hard_lock_ctx);
+}
+
+/* Internal function */
+STATIC void ogma_global_init ( void)
+{
+ ogma_global.valid_flag = OGMA_TRUE;
+}
+
+STATIC ogma_err_t ogma_probe_hardware (
+ void *base_addr
+ )
+{
+
+ ogma_uint32 value;
+
+ /* Read HW_VER Register */
+ value = pfdep_iomem_read((void *)
+ ((pfdep_cpu_addr_t)base_addr +
+ (OGMA_REG_ADDR_HW_VER << 2)));
+
+ if ( value != OGMA_VER_NETSEC) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
+ "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
+ (unsigned int)value,
+ (unsigned int)OGMA_VER_NETSEC);
+ }
+
+ if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
+ pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
+ "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
+ (unsigned int)OGMA_VER_MAJOR_NUM(value),
+ (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Print hardware version information. */
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "NETSEC found. Hardware version: %08x\n",
+ value);
+
+
+ return OGMA_ERR_OK;
+}
+
+STATIC void ogma_reset_hardware (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_CLK_EN,
+ OGMA_CLK_EN_REG_DOM_ALL);
+
+
+ /*
+ * Stop dma engines if cores are enabled
+ */
+ if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_HM_CTRL,
+ OGMA_DMA_CTRL_REG_STOP);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_MH_CTRL,
+ OGMA_DMA_CTRL_REG_STOP);
+
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
+ & OGMA_DMA_CTRL_REG_STOP) != 0) {
+ ;
+ }
+
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
+ & OGMA_DMA_CTRL_REG_STOP) != 0) {
+ ;
+ }
+ }
+
+ if ( ctrl_p->param.use_gmac_flag) {
+
+ /* Reset F_GMAC4MT */
+ ogma_set_mac_reg( ctrl_p,
+ OGMA_GMAC_REG_ADDR_BMR,
+ OGMA_GMAC_BMR_REG_RESET);
+
+ }
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_SOFT_RST,
+ OGMA_SOFT_RST_REG_RESET);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_SOFT_RST,
+ OGMA_SOFT_RST_REG_RUN);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_COM_INIT,
+ OGMA_COM_INIT_REG_ALL);
+
+ while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
+ ;
+ }
+
+ if ( ctrl_p->param.use_gmac_flag) {
+
+
+ /* MAC desc init */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_DESC_INIT,
+ OGMA_MAC_DESC_INIT_REG_INIT);
+
+ /* Wait MAC desc init done */
+ while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
+ & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+ ;
+ }
+
+
+ /* set MAC_INTF_SEL */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTF_SEL,
+ ctrl_p->param.gmac_config.phy_interface);
+
+
+ }
+}
+
+#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
+
+STATIC void ogma_set_microcode (
+ ogma_ctrl_t *ctrl_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len
+ )
+{
+ ogma_uint i;
+
+ const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
+ const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
+ const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
+
+ /* Loads microcodes to microengines. */
+ for( i = 0; i < dma_hm_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
+ data );
+ dmac_hm_cmd_data++;
+ }
+
+ for( i = 0; i < dma_mh_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
+ data );
+ dmac_mh_cmd_data++;
+ }
+
+ for( i = 0; i < pktc_mc_len; i++) {
+ UINT32 data = MmioRead32((UINTN)core_cmd_data);
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKTC_CMD_BUF,
+ data );
+ core_cmd_data++;
+ }
+
+}
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+ const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+ )
+{
+ ogma_uint32 param = 0;
+
+ if ( pkt_ctrl_param_p->log_chksum_er_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
+ }
+
+ if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
+ }
+
+ if ( pkt_ctrl_param_p->log_hd_er_flag) {
+ param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
+ }
+
+ if ( pkt_ctrl_param_p->drp_no_match_flag) {
+ param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
+ }
+
+ return param;
+}
+
+ogma_err_t ogma_init (
+ void *base_addr,
+ pfdep_dev_handle_t dev_handle,
+ const ogma_param_t *param_p,
+ const void *dma_hm_mc_addr,
+ ogma_uint32 dma_hm_mc_len,
+ const void *dma_mh_mc_addr,
+ ogma_uint32 dma_mh_mc_len,
+ const void *pktc_mc_addr,
+ ogma_uint32 pktc_mc_len,
+ ogma_handle_t *ogma_handle_p
+ )
+{
+ ogma_int i;
+ ogma_uint32 domain = 0, value;
+ ogma_err_t ogma_err;
+ ogma_ctrl_t *ctrl_p = NULL;
+
+ ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
+ ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
+
+ ogma_bool all_lock_init_done_flag = OGMA_FALSE;
+
+ pfdep_err_t pfdep_err;
+
+ if ( ( param_p == NULL) ||
+ ( ogma_handle_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
+ return OGMA_ERR_INVALID;
+ }
+
+ if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
+ (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set invalid packet desc_ring_param valid_flag.\n");
+ return OGMA_ERR_DATA;
+ }
+
+ if ( param_p->use_gmac_flag) {
+ if ( ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_GMII) &&
+ ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_RGMII) &&
+ ( param_p->gmac_config.phy_interface !=
+ OGMA_PHY_INTERFACE_RMII) ) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set phy_interface to valid value.\n");
+ return OGMA_ERR_DATA;
+ }
+ } else {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Please set use_gmac_flag OGMA_TRUE.\n");
+ return OGMA_ERR_DATA;
+ }
+
+ ogma_err = ogma_probe_hardware( base_addr);
+
+ if ( ogma_err != OGMA_ERR_OK) {
+ return ogma_err;
+ }
+
+ if ( !ogma_global.valid_flag) {
+ ogma_global_init();
+ }
+
+ if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to ogma_handle memory allocation.\n");
+ return OGMA_ERR_ALLOC;
+ }
+
+ pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
+
+ ctrl_p->base_addr = base_addr;
+
+ ctrl_p->dev_handle = dev_handle;
+
+ pfdep_memcpy( ( void *)&ctrl_p->param,
+ ( void *)param_p,
+ sizeof( ogma_param_t) );
+
+ /* Initialize hardware lock */
+ pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to inten_reg_hard_lock's initialization.\n");
+ ogma_err = OGMA_ERR_ALLOC;
+ goto err;
+ }
+ inten_reg_hard_lock_init_flag = OGMA_TRUE;
+
+ pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to clk_ctrl_hard_lock's initialization.\n");
+ ogma_err = OGMA_ERR_ALLOC;
+ goto err;
+ }
+ clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
+
+ all_lock_init_done_flag = OGMA_TRUE;
+
+ pfdep_err = pfdep_dma_malloc( dev_handle,
+ OGMA_DUMMY_DESC_ENTRY_LEN,
+ &ctrl_p->dummy_desc_entry_addr,
+ &ctrl_p->dummy_desc_entry_phys_addr);
+
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ ogma_err = OGMA_ERR_ALLOC;
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to dummy_desc_entry's memory allocation.\n");
+ goto err;
+ }
+
+ /* clear dummy desc entry */
+ pfdep_memset( ctrl_p->dummy_desc_entry_addr,
+ 0,
+ OGMA_DUMMY_DESC_ENTRY_LEN);
+
+ ogma_reset_hardware( ctrl_p);
+
+ if ( param_p->use_gmac_flag) {
+ domain |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ ogma_push_clk_req( ctrl_p, domain);
+
+ /* set PKT_CTRL */
+ value = ogma_calc_pkt_ctrl_reg_param( ¶m_p->pkt_ctrl_param);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+
+ if ( param_p->use_jumbo_pkt_flag) {
+
+ ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL);
+
+ value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+ } else {
+
+ ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
+
+ }
+
+ /* set pkt desc ring config */
+ for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ if ( ctrl_p->param.desc_ring_param[i].valid_flag) {
+ value =
+ ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
+ OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
+ ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
+ OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
+
+ ogma_write_reg( ctrl_p,
+ desc_ring_config_reg_addr[i],
+ value);
+
+ }
+ }
+
+ /* set microengines */
+ ogma_set_microcode(ctrl_p,
+ dma_hm_mc_addr,
+ dma_hm_mc_len,
+ dma_mh_mc_addr,
+ dma_mh_mc_len,
+ pktc_mc_addr,
+ pktc_mc_len);
+
+ /* alloc desc_ring*/
+ for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
+ if ( ogma_err != OGMA_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to ring id NO.%d memory allocation.\n",
+ i);
+ goto err;
+ }
+ }
+
+ if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
+ if ( ( ogma_err = ogma_setup_rx_desc_ring(
+ ctrl_p,
+ &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
+ != OGMA_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to NRM_RX packet memory allocation.\n");
+ goto err;
+ }
+ }
+
+ /* microengines need domain G */
+ ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ /* set DMA tmr ctrl*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
+ ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
+
+ /* start microengines */
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
+
+ if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to waiting for microcode initialize end.\n");
+ ogma_err = OGMA_ERR_INTERRUPT;
+ goto err;
+ }
+
+ /* check microcode load end & start core */
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+ if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_init.\n"
+ "Failed to microcode loading.\n");
+ ogma_err = OGMA_ERR_INVALID;
+ goto err;
+ }
+
+ /* clear microcode load end status */
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
+ OGMA_TOP_IRQ_REG_ME_START);
+
+ ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+ ctrl_p->core_enabled_flag = OGMA_TRUE;
+
+ ctrl_p->next_p = ogma_global.list_head_p;
+
+ ogma_global.list_head_p = ctrl_p;
+
+ ++ogma_global.list_entry_num;
+
+ *ogma_handle_p = ctrl_p;
+
+#if 1
+ {
+
+#define OGMA_PKT_CTRL_REG_MODE_TAIKI (1UL << 28)
+#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL << 4)
+#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
+
+ /* Read Pkt ctrl register */
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
+ value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
+
+ /* change to noromal mode */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_DMA_MH_CTRL,
+ OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_CTRL,
+ value);
+
+ while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
+ OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
+ ;
+ }
+
+ }
+#endif
+
+ /* Print microcode version information. */
+ pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+ "Microcode version: %08x\n",
+ ogma_read_reg( ctrl_p,
+ mc_ver_reg_addr) );
+
+ return OGMA_ERR_OK;
+
+err:
+ if ( !all_lock_init_done_flag) {
+
+
+ if ( clk_ctrl_hard_lock_init_flag) {
+ pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+ }
+
+ if ( inten_reg_hard_lock_init_flag) {
+ pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
+ }
+
+ } else {
+
+ ogma_internal_terminate( ctrl_p);
+
+ }
+
+ pfdep_free( ctrl_p);
+
+ return ogma_err;
+}
+
+STATIC void ogma_internal_terminate (
+ ogma_ctrl_t *ctrl_p
+ )
+{
+ ogma_int i;
+
+ ogma_reset_hardware( ctrl_p);
+
+ /* free desc_ring */
+ for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+ ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
+ }
+
+ if ( ctrl_p->dummy_desc_entry_addr != NULL) {
+ pfdep_dma_free( ctrl_p->dev_handle,
+ OGMA_DUMMY_DESC_ENTRY_LEN,
+ ctrl_p->dummy_desc_entry_addr,
+ ctrl_p->dummy_desc_entry_phys_addr);
+ }
+
+ pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
+
+
+ pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
+
+}
+
+void ogma_terminate (
+ ogma_handle_t ogma_handle
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
+ ogma_uint32 domain = 0;
+
+ if ( ( ctrl_p == NULL) ||
+ ( ogma_global.list_entry_num == 0) ) {
+ return;
+ }
+
+ pfdep_assert( ogma_global.list_head_p != NULL);
+
+ if ( ctrl_p->param.use_gmac_flag) {
+ domain |= OGMA_CLK_EN_REG_DOM_G;
+ }
+
+ /* pop domain clock */
+ ogma_pop_clk_req( ctrl_p, domain);
+
+ tmp_ctrl_p = ogma_global.list_head_p;
+
+ while(1) {
+ if ( tmp_ctrl_p == NULL) {
+ /* Could not found ctrl_p specified from the list */
+ return;
+ }
+ if ( ctrl_p == tmp_ctrl_p) {
+ if ( old_tmp_ctrl_p != NULL) {
+ old_tmp_ctrl_p->next_p = ctrl_p->next_p;
+ } else {
+ ogma_global.list_head_p = ctrl_p->next_p;
+ }
+ break;
+ }
+ old_tmp_ctrl_p = tmp_ctrl_p;
+ tmp_ctrl_p = tmp_ctrl_p->next_p;
+ }
+
+ ogma_internal_terminate( ctrl_p);
+
+ --ogma_global.list_entry_num;
+
+ pfdep_free( ctrl_p);
+ return;
+}
+
+ogma_err_t ogma_enable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_top_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* clear irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
+
+ return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ ogma_desc_ring_t *desc_ring_p;
+
+ pfdep_err_t pfdep_err;
+ pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+ /* get soft lock */
+ pfdep_err = pfdep_acquire_soft_lock (
+ &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+
+ if ( pfdep_err != PFDEP_ERR_OK) {
+ return OGMA_ERR_INTERRUPT;
+ }
+
+ if ( !desc_ring_p->running_flag) {
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_desc_ring_irq.\n"
+ "Please select running desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_inten_set_reg_addr[ring_id],
+ irq_factor);
+
+ /* free soft_lock*/
+ pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+ &soft_lock_ctx);
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_desc_ring_irq (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_desc_ring_irq.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Clear irq factor*/
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_inten_clr_reg_addr[ring_id],
+ irq_factor);
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_enable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* set irq_factor*/
+ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
+ ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_pkt_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return OGMA_ERR_PARAM;
+ }
+
+ /* clear irq_factor*/
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_INTEN_CLR,
+ ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+ return ogma_err;
+}
+
+
+ogma_uint32 ogma_get_top_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_top_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+
+ return value;
+
+}
+
+
+ogma_uint32 ogma_get_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_top_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+ }
+
+ return value;
+}
+
+ogma_err_t ogma_clear_top_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_top_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* Write clear irq top status */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_TOP_STATUS,
+
+ ( value & OGMA_TOP_IRQ_REG_ME_START) );
+
+ return OGMA_ERR_OK;
+}
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+ "Please select valid desc ring.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ desc_ring_irq_inten_reg_addr[ring_id] );
+
+ return value;
+}
+
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return 0;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_desc_ring_irq_status.\n"
+ "Please select valid desc ring.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ desc_ring_irq_status_reg_addr[ring_id] );
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p,
+ desc_ring_irq_inten_reg_addr[ring_id] );
+ }
+
+ return value;
+}
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_desc_ring_id_t ring_id,
+ ogma_uint32 value
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please select ring id number between 0 and %d.\n",
+ OGMA_DESC_RING_ID_MAX);
+ return OGMA_ERR_PARAM;
+ }
+
+ if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+ "Please select valid desc ring.\n");
+ return OGMA_ERR_NOTAVAIL;
+ }
+
+ /* Write clear descring irq status */
+ ogma_write_reg( ctrl_p,
+ desc_ring_irq_status_reg_addr[ring_id],
+ ( value & ( OGMA_CH_IRQ_REG_EMPTY |
+ OGMA_CH_IRQ_REG_ERR) ) );
+
+ return OGMA_ERR_OK;
+
+}
+
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_pkt_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+
+ value &= OGMA_PKT_IRQ_ALL;
+
+ return value;
+
+}
+
+ogma_uint32 ogma_get_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+ }
+
+ return value;
+}
+
+ogma_err_t ogma_clear_pkt_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_pkt_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* Write clear irq pkt status */
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_PKT_STATUS,
+ ( value & ( ( OGMA_PKT_IRQ_MAC_ER |
+ OGMA_PKT_IRQ_JUMBO_ER |
+ OGMA_PKT_IRQ_CHKSUM_ER |
+ OGMA_PKT_IRQ_HD_INCOMPLETE |
+ OGMA_PKT_IRQ_HD_ER |
+ OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
+
+ return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+ogma_err_t ogma_get_stat_info (
+ ogma_handle_t ogma_handle,
+ ogma_stat_info_t *stat_info_p,
+ ogma_bool clear_flag
+ )
+{
+
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
+ return OGMA_ERR_PARAM;
+ }
+
+ pfdep_memcpy( stat_info_p,
+ &ctrl_p->stat_info,
+ sizeof( ogma_stat_info_t) );
+
+
+ if ( clear_flag) {
+ pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
+ }
+
+ return OGMA_ERR_OK;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_uint32 ogma_get_hw_ver (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ hw_ver_reg_addr);
+
+ return value;
+}
+
+
+ogma_uint32 ogma_get_mcr_ver (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p,
+ mc_ver_reg_addr);
+
+ return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_enable (
+ ogma_handle_t ogma_handle
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+
+
+ return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_bool mask_flag
+ )
+{
+ ogma_uint32 value;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_get_mac_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return 0;
+ }
+
+
+ value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
+
+ if ( mask_flag) {
+ value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+ }
+
+
+ return value;
+}
+
+ogma_err_t ogma_clear_mac_irq_status (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 value
+ )
+{
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_clear_mac_irq_status.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+
+ /* Commented out because no write-clear bit exists now. */
+#if 0
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_STATUS,
+ ( value & /* T.B.D. */) );
+#endif
+
+
+ return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_enable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_uint32 value;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+ pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_enable_mac_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* get inten_reg_hard_lock */
+ pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN);
+
+ value |= irq_factor;
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN,
+ value);
+
+
+ /* free inten_reg_hard_lock*/
+ pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+ return ogma_err;
+}
+
+ogma_err_t ogma_disable_mac_irq (
+ ogma_handle_t ogma_handle,
+ ogma_uint32 irq_factor
+ )
+{
+ ogma_uint32 value;
+ ogma_err_t ogma_err = OGMA_ERR_OK;
+ ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+ pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+
+ if ( ctrl_p == NULL) {
+ pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+ "An error occurred at ogma_disable_mac_irq.\n"
+ "Please set valid ogma_handle.\n");
+ return OGMA_ERR_PARAM;
+ }
+
+ /* get inten_reg_hard_lock */
+ pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+
+ value = ogma_read_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN);
+
+ value &= (~irq_factor);
+
+ ogma_write_reg( ctrl_p,
+ OGMA_REG_ADDR_MAC_INTEN,
+ value);
+
+
+ /* free inten_reg_hard_lock*/
+ pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+ &inten_reg_hard_lock_ctx);
+ return ogma_err;
+
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
new file mode 100644
index 000000000000..3bbf8de57a8b
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
@@ -0,0 +1,38 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_MISC_INTERNAL_H
+#define OGMA_MISC_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+#define OGMA_CLK_EN_REG_DOM_ALL 0x24
+
+#define OGMA_PKT_IRQ_ALL ( OGMA_PKT_IRQ_MAC_ER | OGMA_PKT_IRQ_JUMBO_ER | \
+ OGMA_PKT_IRQ_CHKSUM_ER | OGMA_PKT_IRQ_HD_INCOMPLETE | \
+ OGMA_PKT_IRQ_HD_ER | OGMA_PKT_IRQ_DRP_NO_MATCH)
+
+typedef struct ogma_global_s ogma_global_t;
+
+struct ogma_global_s{
+ ogma_uint valid_flag:1;
+
+ ogma_uint8 list_entry_num;
+
+ ogma_ctrl_t *list_head_p;
+};
+
+#endif /* OGMA_MISC_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
new file mode 100644
index 000000000000..910b37a25f14
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
@@ -0,0 +1,219 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_H
+#define OGMA_REG_H
+
+#include "ogma_reg_netsec.h"
+#include "ogma_reg_f_gmac_4mt.h"
+
+/* aliases */
+#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
+#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
+#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
+/* aliases end here */
+
+/* need fixing */
+#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF (0x87)
+
+
+/*bit fields for PKT_CTRL*/
+#define OGMA_PKT_CTRL_REG_EN_JUMBO (1UL << 27)
+#define OGMA_PKT_CTRL_REG_EN_BITPATF (1UL << 4 )
+#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER (1UL << 3 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_ER (1UL << 1 )
+#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH (1UL << 0 )
+
+#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
+
+/************************************************************
+ * Bit fields
+ ************************************************************/
+/* bit fields for com_init */
+#define OGMA_COM_INIT_REG_DB (1UL << 2)
+#define OGMA_COM_INIT_REG_CLS (1UL << 1)
+#define OGMA_COM_INIT_REG_ALL ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
+
+/* bit fields for soft_rst */
+#define OGMA_SOFT_RST_REG_RESET (0)
+#define OGMA_SOFT_RST_REG_RUN (1UL << 31)
+
+/* bit fields for dma_hm_ctrl */
+#define OGMA_DMA_CTRL_REG_STOP 1UL
+
+/* bit fields for gmac_cmd */
+#define OGMA_GMAC_CMD_ST_READ (0)
+#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
+#define OGMA_GMAC_CMD_ST_BUSY (1UL << 31)
+
+/* bit fields for F_GMAC4MT BMR*/
+#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
+#define OGMA_GMAC_BMR_REG_RESET (0x00020181)
+#define OGMA_GMAC_BMR_REG_SWR (0x00000001)
+
+/* bit fields for F_GMAC4MT OMR*/
+#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
+#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
+
+/* bit fields for F_GMAC4MT MCR*/
+#define OGMA_GMAC_MCR_REG_CST (1UL << 25)
+#define OGMA_GMAC_MCR_REG_JE (1UL << 20)
+#define OGMA_GMAC_MCR_REG_PS (1UL << 15)
+#define OGMA_GMAC_MCR_REG_FES (1UL << 14)
+#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
+#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
+
+#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_PS | \
+ OGMA_GMAC_MCR_REG_FES | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_FES | \
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_PS | \
+ OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+ OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+/*bit fields for F_GMAC4MT FCR*/
+#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
+#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
+
+/* bit fields for F_GMAC4MT GAR */
+#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
+#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
+
+/* bit fields for F_GMAC4MT RDLAR*/
+#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
+
+/* bit fields for F_GMAC4MT TDLAR*/
+#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
+
+
+#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
+#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
+#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
+
+#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ (2)
+#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ (3)
+#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ (0)
+#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
+#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
+#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
+
+/* bit fields for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_LIT (16)
+#define OGMA_GMAC_LPITCR_REG_TWT (0)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
+#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
+
+/**
+ * PHY regtister Address
+ */
+#define OGMA_PHY_REG_ADDR_CONTROL 0
+#define OGMA_PHY_REG_ADDR_STATUS 1U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY 4U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL 9U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS 10U
+#define OGMA_PHY_REG_ADDR_MMD_AC 13U
+#define OGMA_PHY_REG_ADDR_MMD_AAD 14U
+
+/* bit fields for PHY CONTROL Register */
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
+#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8)
+#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12)
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
+
+/* bit fields for PHY STATUS Register */
+#define OGMA_PHY_STATUS_REG_LINK_STATUS (2)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP (5)
+
+/* bit fields for PHY MASTER-SLAVE Control Register */
+#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
+#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
+
+/* bit fields for PHY MASTER-SLAVE Status Register */
+#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
+#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
+
+/* bit fields for PHY Auto-Negotiation Advertisement Register */
+#define OGMA_PHY_ANA_REG_TAF (5)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
+
+/* bit fields for PHY Technology Ability Field */
+#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
+#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
+#define OGMA_PHY_TAF_REG_10BASE_FULL (1U << 1)
+#define OGMA_PHY_TAF_REG_10BASE_HALF (1U << 0)
+
+/**
+ * PHY Device Address
+ */
+#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
+
+/**
+ * PHY Register Address for Device Address 7
+ */
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE (60U)
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
+
+/* bit fields for PHY AutoNegotiation Field */
+#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
+#define OGMA_PHY_AUTO_NEGO_100BASE_EEE (1U << 1)
+
+/* bit fields for DESC RING CONFIG */
+#define OGMA_REG_DESC_RING_CONFIG_CFG_UP (31)
+#define OGMA_REG_DESC_RING_CONFIG_CH_RST (30)
+#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE (4)
+#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
+
+
+/* bit fields for mac_desc_soft_rst */
+#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
+
+/* bit fields for mac_desc_init */
+#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
+
+/* bit fields for dis_core */
+#define OGMA_DIS_CORE_REG_DIS_PCORE (1UL << 2)
+#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
+#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
+
+#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
+ OGMA_DIS_CORE_REG_DIS_MHCORE | \
+ OGMA_DIS_CORE_REG_DIS_PCORE)
+
+/* bit fields for dma_info */
+#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
+#define OGMA_DMA_INFO_REG_AXI_READ_BUSY (1UL << 2)
+
+#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
+ OGMA_DMA_INFO_REG_AXI_READ_BUSY)
+
+#endif /*OGMA_REG_H*/
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
new file mode 100644
index 000000000000..e12b317218fb
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
@@ -0,0 +1,222 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_F_GMAC_4MT_H
+#define OGMA_REG_F_GMAC_4MT_H
+
+/**
+ * GMAC register
+ */
+#define OGMA_GMAC_REG_ADDR_MCR (0x0000)
+#define OGMA_GMAC_REG_ADDR_MFFR (0x0004)
+#define OGMA_GMAC_REG_ADDR_MHTRH (0x0008)
+#define OGMA_GMAC_REG_ADDR_MHTRL (0x000c)
+#define OGMA_GMAC_REG_ADDR_GAR (0x0010)
+#define OGMA_GMAC_REG_ADDR_GDR (0x0014)
+#define OGMA_GMAC_REG_ADDR_FCR (0x0018)
+#define OGMA_GMAC_REG_ADDR_VTR (0x001c)
+#define OGMA_GMAC_REG_ADDR_RWFFR (0x0028)
+#define OGMA_GMAC_REG_ADDR_PMTR (0x002c)
+#define OGMA_GMAC_REG_ADDR_LPICSR (0x0030)
+#define OGMA_GMAC_REG_ADDR_LPITCR (0x0034)
+#define OGMA_GMAC_REG_ADDR_ISR (0x0038)
+#define OGMA_GMAC_REG_ADDR_IMR (0x003c)
+#define OGMA_GMAC_REG_ADDR_MAR0H (0x0040)
+#define OGMA_GMAC_REG_ADDR_MAR0L (0x0044)
+#define OGMA_GMAC_REG_ADDR_MAR1H (0x0048)
+#define OGMA_GMAC_REG_ADDR_MAR1L (0x004c)
+#define OGMA_GMAC_REG_ADDR_MAR2H (0x0050)
+#define OGMA_GMAC_REG_ADDR_MAR2L (0x0054)
+#define OGMA_GMAC_REG_ADDR_MAR3H (0x0058)
+#define OGMA_GMAC_REG_ADDR_MAR3L (0x005c)
+#define OGMA_GMAC_REG_ADDR_MAR4H (0x0060)
+#define OGMA_GMAC_REG_ADDR_MAR4L (0x0064)
+#define OGMA_GMAC_REG_ADDR_MAR5H (0x0068)
+#define OGMA_GMAC_REG_ADDR_MAR5L (0x006c)
+#define OGMA_GMAC_REG_ADDR_MAR6H (0x0070)
+#define OGMA_GMAC_REG_ADDR_MAR6L (0x0074)
+#define OGMA_GMAC_REG_ADDR_MAR7H (0x0078)
+#define OGMA_GMAC_REG_ADDR_MAR7L (0x007c)
+#define OGMA_GMAC_REG_ADDR_MAR8H (0x0080)
+#define OGMA_GMAC_REG_ADDR_MAR8L (0x0084)
+#define OGMA_GMAC_REG_ADDR_MAR9H (0x0088)
+#define OGMA_GMAC_REG_ADDR_MAR9L (0x008c)
+#define OGMA_GMAC_REG_ADDR_MAR10H (0x0090)
+#define OGMA_GMAC_REG_ADDR_MAR10L (0x0094)
+#define OGMA_GMAC_REG_ADDR_MAR11H (0x0098)
+#define OGMA_GMAC_REG_ADDR_MAR11L (0x009c)
+#define OGMA_GMAC_REG_ADDR_MAR12H (0x00a0)
+#define OGMA_GMAC_REG_ADDR_MAR12L (0x00a4)
+#define OGMA_GMAC_REG_ADDR_MAR13H (0x00a8)
+#define OGMA_GMAC_REG_ADDR_MAR13L (0x00ac)
+#define OGMA_GMAC_REG_ADDR_MAR14H (0x00b0)
+#define OGMA_GMAC_REG_ADDR_MAR14L (0x00b4)
+#define OGMA_GMAC_REG_ADDR_MAR15H (0x00b8)
+#define OGMA_GMAC_REG_ADDR_MAR15L (0x00bc)
+#define OGMA_GMAC_REG_ADDR_RSR (0x00d8)
+#define OGMA_GMAC_REG_ADDR_TSCR (0x0700)
+#define OGMA_GMAC_REG_ADDR_SSIR (0x0704)
+#define OGMA_GMAC_REG_ADDR_STSR (0x0708)
+#define OGMA_GMAC_REG_ADDR_STNR (0x070c)
+#define OGMA_GMAC_REG_ADDR_STSUR (0x0710)
+#define OGMA_GMAC_REG_ADDR_STNUR (0x0714)
+#define OGMA_GMAC_REG_ADDR_TSAR (0x0718)
+#define OGMA_GMAC_REG_ADDR_TTSR (0x071c)
+#define OGMA_GMAC_REG_ADDR_TTNR (0x0720)
+#define OGMA_GMAC_REG_ADDR_STHWSR (0x0724)
+#define OGMA_GMAC_REG_ADDR_TSR (0x0728)
+#define OGMA_GMAC_REG_ADDR_PPSCR (0x072c)
+#define OGMA_GMAC_REG_ADDR_ANTR (0x0730)
+#define OGMA_GMAC_REG_ADDR_ATSR (0x0734)
+#define OGMA_GMAC_REG_ADDR_MAR16H (0x0800)
+#define OGMA_GMAC_REG_ADDR_MAR16L (0x0804)
+#define OGMA_GMAC_REG_ADDR_MAR17H (0x0808)
+#define OGMA_GMAC_REG_ADDR_MAR17L (0x080c)
+#define OGMA_GMAC_REG_ADDR_MAR18H (0x0810)
+#define OGMA_GMAC_REG_ADDR_MAR18L (0x0814)
+#define OGMA_GMAC_REG_ADDR_MAR19H (0x0818)
+#define OGMA_GMAC_REG_ADDR_MAR19L (0x081c)
+#define OGMA_GMAC_REG_ADDR_MAR20H (0x0820)
+#define OGMA_GMAC_REG_ADDR_MAR20L (0x0824)
+#define OGMA_GMAC_REG_ADDR_MAR21H (0x0828)
+#define OGMA_GMAC_REG_ADDR_MAR21L (0x082c)
+#define OGMA_GMAC_REG_ADDR_MAR22H (0x0830)
+#define OGMA_GMAC_REG_ADDR_MAR22L (0x0834)
+#define OGMA_GMAC_REG_ADDR_MAR23H (0x0838)
+#define OGMA_GMAC_REG_ADDR_MAR23L (0x083c)
+#define OGMA_GMAC_REG_ADDR_MAR24H (0x0840)
+#define OGMA_GMAC_REG_ADDR_MAR24L (0x0844)
+#define OGMA_GMAC_REG_ADDR_MAR25H (0x0848)
+#define OGMA_GMAC_REG_ADDR_MAR25L (0x084c)
+#define OGMA_GMAC_REG_ADDR_MAR26H (0x0850)
+#define OGMA_GMAC_REG_ADDR_MAR26L (0x0854)
+#define OGMA_GMAC_REG_ADDR_MAR27H (0x0858)
+#define OGMA_GMAC_REG_ADDR_MAR27L (0x085c)
+#define OGMA_GMAC_REG_ADDR_MAR28H (0x0860)
+#define OGMA_GMAC_REG_ADDR_MAR28L (0x0864)
+#define OGMA_GMAC_REG_ADDR_MAR29H (0x0868)
+#define OGMA_GMAC_REG_ADDR_MAR29L (0x086c)
+#define OGMA_GMAC_REG_ADDR_MAR30H (0x0870)
+#define OGMA_GMAC_REG_ADDR_MAR30L (0x0874)
+#define OGMA_GMAC_REG_ADDR_MAR31H (0x0878)
+#define OGMA_GMAC_REG_ADDR_MAR31L (0x087c)
+
+/**
+ * GMAC MAC Management Counters(Option) register
+ */
+#define OGMA_GMAC_REG_ADDR_MMC_CNTL (0x0100)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX (0x0104)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX (0x0108)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX (0x010c)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX (0x0110)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB (0x0114)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB (0x0118)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G (0x011c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G (0x0120)
+#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB (0x0124)
+#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB (0x0128)
+#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB (0x012c)
+#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB (0x0130)
+#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB (0x0134)
+#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB (0x0138)
+#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB (0x013c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB (0x0140)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB (0x0144)
+#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR (0x0148)
+#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G (0x014c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G (0x0150)
+#define OGMA_GMAC_REG_ADDR_TXDEFERRED (0x0154)
+#define OGMA_GMAC_REG_ADDR_TXLATECOL (0x0158)
+#define OGMA_GMAC_REG_ADDR_TXEXESSCOL (0x015c)
+#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR (0x0160)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G (0x0164)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G (0x0168)
+#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF (0x016c)
+#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES (0x0170)
+#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G (0x0174)
+#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB (0x0180)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB (0x0184)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G (0x0188)
+#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G (0x018c)
+#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G (0x0190)
+#define OGMA_GMAC_REG_ADDR_RXCRCERROR (0x0194)
+#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR (0x0198)
+#define OGMA_GMAC_REG_ADDR_RXRUNTERROR (0x019c)
+#define OGMA_GMAC_REG_ADDR_RXJABBERERROR (0x01a0)
+#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G (0x01a4)
+#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G (0x01a8)
+#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB (0x01ac)
+#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB (0x01b0)
+#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB (0x01b4)
+#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB (0x01b8)
+#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB (0x01bc)
+#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB (0x01c0)
+#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G (0x01c4)
+#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR (0x01c8)
+#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE (0x01cc)
+#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES (0x01d0)
+#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW (0x01d4)
+#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB (0x01d8)
+#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR (0x01dc)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX (0x0200)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX (0x0208)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS (0x0210)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS (0x0214)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS (0x0218)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS (0x021c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS (0x0220)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS (0x0224)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS (0x0228)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS (0x022c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS (0x0230)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS (0x0234)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS (0x0238)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS (0x023c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS (0x0240)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS (0x0244)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS (0x0250)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS (0x0254)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS (0x0258)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS (0x025c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS (0x0260)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS (0x0264)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS (0x0268)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS (0x026c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS (0x0270)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS (0x0274)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS (0x0278)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS (0x027c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS (0x0280)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS (0x0284)
+/**
+ * GMAC DMA register
+ */
+#define OGMA_GMAC_REG_ADDR_BMR (0x1000)
+#define OGMA_GMAC_REG_ADDR_TPDR (0x1004)
+#define OGMA_GMAC_REG_ADDR_RPDR (0x1008)
+#define OGMA_GMAC_REG_ADDR_RDLAR (0x100c)
+#define OGMA_GMAC_REG_ADDR_TDLAR (0x1010)
+#define OGMA_GMAC_REG_ADDR_SR (0x1014)
+#define OGMA_GMAC_REG_ADDR_OMR (0x1018)
+#define OGMA_GMAC_REG_ADDR_IER (0x101c)
+#define OGMA_GMAC_REG_ADDR_MFOCR (0x1020)
+#define OGMA_GMAC_REG_ADDR_RIWTR (0x1024)
+#define OGMA_GMAC_REG_ADDR_AHBSR (0x102c)
+#define OGMA_GMAC_REG_ADDR_CHTDR (0x1048)
+#define OGMA_GMAC_REG_ADDR_CHRDR (0x104c)
+#define OGMA_GMAC_REG_ADDR_CHTBAR (0x1050)
+#define OGMA_GMAC_REG_ADDR_CHRBAR (0x1054)
+
+#endif /* OGMA_REG_F_GMAC_4MT_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
new file mode 100644
index 000000000000..457be2aa0cba
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
@@ -0,0 +1,368 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_NETSEC_H
+#define OGMA_REG_NETSEC_H
+
+#define OGMA_REG_ADDR_SOFT_RST (0x41)
+#define OGMA_REG_ADDR_COM_INIT (0x48)
+#define OGMA_REG_ADDR_MC_BASE_ADDR (0x97)
+#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
+#define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89)
+#define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A)
+#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
+#define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C)
+#define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D)
+#define OGMA_REG_ADDR_DIS_CORE (0x86)
+#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
+#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
+#define OGMA_REG_ADDR_CLK_EN_0 (0x40)
+#define OGMA_REG_ADDR_CLK_EN_1 (0x64)
+#define OGMA_REG_ADDR_PKT_CTRL (0x50)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292)
+#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C)
+#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C)
+#define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C)
+#define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C)
+#define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C)
+#define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C)
+#define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC)
+#define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C)
+#define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C)
+#define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C)
+#define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C)
+#define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C)
+#define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C)
+#define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C)
+#define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C)
+#define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C)
+#define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C)
+#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
+#define OGMA_REG_ADDR_TOP_STATUS (0x80)
+#define OGMA_REG_ADDR_TOP_INTEN_A (0x81)
+#define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D)
+#define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E)
+#define OGMA_REG_ADDR_TOP_INTEN_B (0x8F)
+#define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90)
+#define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91)
+#define OGMA_REG_ADDR_PKT_STATUS (0x3)
+#define OGMA_REG_ADDR_PKT_INTEN (0x4)
+#define OGMA_REG_ADDR_PKT_INTEN_SET (0x7)
+#define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8)
+#define OGMA_REG_ADDR_TLS_STATUS (0x5)
+#define OGMA_REG_ADDR_TLS_INTEN (0x6)
+#define OGMA_REG_ADDR_TLS_INTEN_SET (0x9)
+#define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA)
+#define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE)
+#define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12)
+#define OGMA_REG_ADDR_MAC_STATUS (0x409)
+#define OGMA_REG_ADDR_MAC_INTEN (0x40A)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487)
+#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
+#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B)
+#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
+#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B)
+#define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B)
+#define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B)
+#define OGMA_REG_ADDR_MISC_RX_STATUS (0x140)
+#define OGMA_REG_ADDR_MISC_RX_INTEN (0x141)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B)
+#define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B)
+#define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB)
+#define OGMA_REG_ADDR_DEC_TX_STATUS (0x200)
+#define OGMA_REG_ADDR_DEC_TX_INTEN (0x201)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B)
+#define OGMA_REG_ADDR_ENC_RX_STATUS (0x210)
+#define OGMA_REG_ADDR_ENC_RX_INTEN (0x211)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B)
+#define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B)
+#define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B)
+#define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B)
+#define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B)
+#define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B)
+#define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B)
+#define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B)
+#define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B)
+#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
+#define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134)
+#define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4)
+#define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204)
+#define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224)
+#define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234)
+#define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264)
+#define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274)
+#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275)
+#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276)
+#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
+#define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137)
+#define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7)
+#define OGMA_REG_ADDR_DEC_TX_TMR (0x207)
+#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
+#define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138)
+#define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8)
+#define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208)
+#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
+#define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125)
+#define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145)
+#define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5)
+#define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215)
+#define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245)
+#define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255)
+#define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285)
+#define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
+#define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126)
+#define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146)
+#define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196)
+#define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6)
+#define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216)
+#define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246)
+#define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256)
+#define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286)
+#define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296)
+#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
+#define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127)
+#define OGMA_REG_ADDR_MISC_RX_TMR (0x147)
+#define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
+#define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128)
+#define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148)
+#define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8)
+#define OGMA_REG_ADDR_PODB_CMD_ST (0x20)
+#define OGMA_REG_ADDR_PODB_DATA (0x21)
+#define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A)
+#define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B)
+#define OGMA_REG_ADDR_CLS_CMD_ST (0x2C)
+#define OGMA_REG_ADDR_CLS_DATA (0x2D)
+#define OGMA_REG_ADDR_SADB_CMD_ST (0x2E)
+#define OGMA_REG_ADDR_SADB_DATA (0x2F)
+#define OGMA_REG_ADDR_MAC_CMD (0x471)
+#define OGMA_REG_ADDR_MAC_DATA (0x470)
+#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
+#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479)
+#define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A)
+#define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B)
+#define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C)
+#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F)
+#define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480)
+#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
+#define OGMA_REG_ADDR_IV_INIT_VAL (0x45)
+#define OGMA_REG_ADDR_MAC_ADD_UP (0x43)
+#define OGMA_REG_ADDR_MAC_ADD_LW (0x44)
+#define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65)
+#define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66)
+#define OGMA_REG_ADDR_ST_INFO_SIZE (0x67)
+#define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68)
+#define OGMA_REG_ADDR_LOGIC_GR_ID (0x69)
+#define OGMA_REG_ADDR_ST_FOR_PBC (0x6A)
+#define OGMA_REG_ADDR_ALARM_INFO (0x6B)
+#define OGMA_REG_ADDR_MC_VER (0x8B)
+#define OGMA_REG_ADDR_HW_VER (0x8C)
+
+#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
+
+#endif /* OGMA_REG_F_TAIKI_H */
+
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
new file mode 100644
index 000000000000..1caf64e30623
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_CONFIG_H
+#define OGMA_CONFIG_H
+
+#define OGMA_CONFIG_CLK_HZ 125000000UL
+#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
+#define OGMA_CONFIG_CHECK_CLK_SUPPLY
+
+#define OGMA_CONFIG_USE_READ_GMAC_STAT
+
+#endif /* OGMA_CONFIG_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
new file mode 100644
index 000000000000..f617f1c70183
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
@@ -0,0 +1,265 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PFDEP_H
+#define PFDEP_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <Library/BaseLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+
+#include <Protocol/Cpu.h>
+
+extern EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+#define PFDEP_INT64_AVAILABLE
+
+/**********************************************************************
+ * Elementary type definitions
+ **********************************************************************/
+typedef int8_t pfdep_int8;
+typedef uint8_t pfdep_uint8;
+typedef int16_t pfdep_int16;
+typedef uint16_t pfdep_uint16;
+typedef int pfdep_int32;
+typedef unsigned int pfdep_uint32;
+typedef int64_t pfdep_int64;
+typedef uint64_t pfdep_uint64;
+typedef int pfdep_bool;
+typedef char pfdep_char;
+
+#define PFDEP_TRUE ((pfdep_bool)1)
+#define PFDEP_FALSE ((pfdep_bool)0)
+
+
+/**********************************************************************
+ * Complex type definitions
+ **********************************************************************/
+
+typedef enum pfdep_err_e {
+ PFDEP_ERR_OK = 0,
+ PFDEP_ERR_PARAM,
+ PFDEP_ERR_ALLOC,
+ PFDEP_ERR_INTERRUPT
+} pfdep_err_t;
+
+
+typedef struct {
+ LIST_ENTRY Link;
+ VOID *Buffer;
+ VOID *Mapping;
+ BOOLEAN RecycleForTx;
+ BOOLEAN Released;
+} PACKET_HANDLE;
+
+typedef VOID *pfdep_dev_handle_t;
+typedef PACKET_HANDLE *pfdep_pkt_handle_t;
+typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
+typedef UINT64 pfdep_cpu_addr_t;
+
+typedef int pfdep_hard_lock_t;
+typedef int pfdep_soft_lock_t;
+
+typedef BOOLEAN pfdep_hard_lock_ctx_t;
+typedef int pfdep_soft_lock_ctx_t;
+
+typedef unsigned int pfdep_debug_level_t;
+
+#define PFDEP_DEBUG_LEVEL_FATAL ((pfdep_debug_level_t)1)
+#define PFDEP_DEBUG_LEVEL_WARNING ((pfdep_debug_level_t)2)
+#define PFDEP_DEBUG_LEVEL_NOTICE ((pfdep_debug_level_t)3)
+#define PFDEP_DEBUG_LEVEL_DEBUG ((pfdep_debug_level_t)4)
+#define PFDEP_DEBUG_LEVEL_DEBUG_DETAILED ((pfdep_debug_level_t)5)
+#define PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED ((pfdep_debug_level_t)6)
+
+/**********************************************************************
+ * Variable declarations
+ **********************************************************************/
+extern pfdep_debug_level_t pfdep_debug_level; /* defined in pfdep_uefi.c */
+
+
+/**********************************************************************
+ * Function declarations
+ **********************************************************************/
+
+static __inline pfdep_uint32 pfdep_iomem_read(void *addr)
+{
+ return *((volatile pfdep_uint32 *)(addr));
+}
+
+static __inline void pfdep_iomem_write(void *addr, pfdep_uint32 val)
+{
+ *((volatile pfdep_uint32 *)(addr)) = val;
+
+
+}
+
+#define pfdep_read_mem_barrier() MemoryFence()
+#define pfdep_write_mem_barrier() MemoryFence()
+#define pfdep_mem_barrier() MemoryFence()
+
+void *pfdep_malloc(pfdep_uint32 len);
+
+void pfdep_free(void *addr);
+
+pfdep_err_t pfdep_dma_malloc (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint32 len,
+ void **addr_p,
+ pfdep_phys_addr_t *phys_addr_p
+ );
+
+void pfdep_dma_free (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint32 len,
+ void *addr,
+ pfdep_phys_addr_t phys_addr
+ );
+
+pfdep_err_t pfdep_alloc_pkt_buf (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint16 len,
+ void **addr_p,
+ pfdep_phys_addr_t *phys_addr_p,
+ pfdep_pkt_handle_t *pkt_handle_p
+ );
+
+void pfdep_free_pkt_buf (
+ pfdep_dev_handle_t dev_handle,
+ pfdep_uint16 len,
+ void *addr,
+ pfdep_phys_addr_t phys_addr,
+ pfdep_bool last_flag,
+ pfdep_pkt_handle_t pkt_handle
+ );
+
+static __inline pfdep_err_t pfdep_init_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+ return;
+}
+
+static __inline void pfdep_acquire_hard_lock (
+ pfdep_hard_lock_t *hard_lock_p, /* not used */
+ pfdep_hard_lock_ctx_t *ctx_p
+ )
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+
+ *ctx_p = SaveAndDisableInterrupts();
+}
+
+
+static __inline void pfdep_release_hard_lock (
+ pfdep_hard_lock_t *hard_lock_p, /* not used */
+ pfdep_hard_lock_ctx_t *ctx_p
+ )
+{
+ (void)hard_lock_p; /* suppress compiler warning */
+
+ SetInterruptState(*ctx_p);
+}
+
+static __inline pfdep_err_t pfdep_init_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p
+ )
+{
+ *soft_lock_p = 0; /* suppress compiler warning */
+
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+
+ return;
+}
+
+static __inline pfdep_err_t pfdep_acquire_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p,
+ pfdep_soft_lock_ctx_t *ctx_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+ (void)ctx_p; /* suppress compiler warning */
+
+ return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_release_soft_lock (
+ pfdep_soft_lock_t *soft_lock_p,
+ pfdep_soft_lock_ctx_t *ctx_p
+ )
+{
+ (void)soft_lock_p; /* suppress compiler warning */
+ (void)ctx_p; /* suppress compiler warning */
+}
+
+
+static __inline void pfdep_memcpy(void *dst_p, const void *src_p, pfdep_uint32 len)
+{
+ memcpy(dst_p, src_p, (size_t)len);
+}
+
+static __inline void pfdep_memset(void *dst_p, pfdep_uint8 c, pfdep_uint32 len)
+{
+ memset(dst_p, c, (size_t)len);
+}
+
+static __inline pfdep_err_t pfdep_msleep(pfdep_uint32 wait_ms)
+{
+
+ MicroSecondDelay ((UINTN)wait_ms * 1000);
+
+ return PFDEP_ERR_OK;
+}
+
+#define pfdep_print(level,...) \
+do { \
+ if (level <= pfdep_debug_level) { \
+ DEBUG ((DEBUG_INFO, "[NETSEC] " __VA_ARGS__)); \
+ } \
+} while (0)
+
+
+static __inline pfdep_debug_level_t pfdep_get_debug_level(void)
+{
+ return pfdep_debug_level;
+}
+
+static __inline void pfdep_set_debug_level(pfdep_debug_level_t level)
+{
+ pfdep_debug_level = level;
+}
+
+
+#define pfdep_assert(cond) ASSERT(cond)
+
+#endif /* PFDEP_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
new file mode 100644
index 000000000000..b43d1aaff037
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
@@ -0,0 +1,176 @@
+/** @file
+
+ Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "pfdep.h"
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/SynchronizationLib.h>
+
+/**********************************************************************
+ * Variable definitions
+ **********************************************************************/
+pfdep_debug_level_t pfdep_debug_level = PFDEP_DEBUG_LEVEL_NOTICE;
+
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+VOID*
+pfdep_malloc (
+ IN pfdep_uint32 len
+ )
+{
+ return AllocatePool (len);
+}
+
+VOID
+pfdep_free (
+ IN VOID *addr
+ )
+{
+ FreePool (addr);
+}
+
+pfdep_err_t
+pfdep_dma_malloc (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint32 len,
+ OUT VOID **addr_p,
+ OUT pfdep_phys_addr_t *phys_addr_p
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumPages;
+ UINTN NumBytes;
+ VOID **Mapping;
+
+ NumPages = EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof *Mapping);
+ Status = DmaAllocateBuffer (EfiBootServicesData, NumPages, addr_p);
+ if (EFI_ERROR (Status)) {
+ return PFDEP_ERR_ALLOC;
+ }
+
+ //
+ // Stash the address of the MAPINFO struct at the end of the buffer,
+ // but make sure it appears aligned (the memory may be mapped uncached)
+ //
+ Mapping = (VOID **)((UINTN)*addr_p + ALIGN_VARIABLE(len));
+
+ NumBytes = EFI_PAGES_TO_SIZE (NumPages);
+ Status = DmaMap (MapOperationBusMasterCommonBuffer, *addr_p, &NumBytes,
+ phys_addr_p, Mapping);
+
+ if (EFI_ERROR (Status) || NumBytes < len) {
+ DmaFreeBuffer (NumPages, *addr_p);
+ return PFDEP_ERR_ALLOC;
+ }
+
+ return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_dma_free (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint32 len,
+ IN VOID *addr,
+ IN pfdep_phys_addr_t phys_addr
+ )
+{
+ VOID *Mapping;
+
+ Mapping = *(VOID **)((UINTN)addr + ALIGN_VARIABLE(len));
+
+ DmaUnmap (Mapping);
+ DmaFreeBuffer (EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof Mapping),
+ addr);
+}
+
+//
+// On the receive path, we allocate a new packet and link it into the RX ring
+// before returning the received packet to the caller. This means we perform
+// one allocation and one free operation for each buffer received.
+// So let's cache a single packet, and get rid of most of the alloc/free
+// overhead on the RX path.
+//
+STATIC pfdep_pkt_handle_t mSparePacketBuffer;
+STATIC UINT32 mSparePacketBufferSize;
+
+pfdep_err_t
+pfdep_alloc_pkt_buf (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint16 len,
+ OUT VOID **addr_p,
+ OUT pfdep_phys_addr_t *phys_addr_p,
+ OUT pfdep_pkt_handle_t *pkt_handle_p
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumBytes;
+
+ NumBytes = ALIGN_VALUE (len, mCpu->DmaBufferAlignment);
+
+ if (InterlockedCompareExchange32 (&mSparePacketBufferSize, len, 0) == len) {
+ *pkt_handle_p = mSparePacketBuffer;
+ } else {
+ *pkt_handle_p = AllocateZeroPool (NumBytes + sizeof(PACKET_HANDLE) +
+ (mCpu->DmaBufferAlignment - 8));
+ if (*pkt_handle_p == NULL) {
+ return PFDEP_ERR_ALLOC;
+ }
+
+ (*pkt_handle_p)->Buffer = ALIGN_POINTER (*pkt_handle_p,
+ mCpu->DmaBufferAlignment);
+ }
+
+ *addr_p = (*pkt_handle_p)->Buffer;
+ Status = DmaMap (MapOperationBusMasterWrite, *addr_p, &NumBytes, phys_addr_p,
+ &(*pkt_handle_p)->Mapping);
+ if (EFI_ERROR (Status) || NumBytes < len) {
+ FreePool (*pkt_handle_p);
+ return PFDEP_ERR_ALLOC;
+ }
+ return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_free_pkt_buf (
+ IN pfdep_dev_handle_t dev_handle,
+ IN pfdep_uint16 len,
+ IN VOID *addr,
+ IN pfdep_phys_addr_t phys_addr,
+ IN pfdep_bool last_flag,
+ IN pfdep_pkt_handle_t pkt_handle
+ )
+{
+ if (last_flag != PFDEP_TRUE) {
+ return;
+ }
+
+ if (pkt_handle->Mapping != NULL) {
+ DmaUnmap (pkt_handle->Mapping);
+ }
+
+ if (pkt_handle->RecycleForTx) {
+ pkt_handle->Released = TRUE;
+ } else if (!InterlockedCompareExchange32 (&mSparePacketBufferSize, 0, len)) {
+ mSparePacketBuffer = pkt_handle;
+ } else {
+ FreePool (pkt_handle);
+ }
+}
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
2017-09-08 18:23 ` [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller Ard Biesheuvel
@ 2017-09-11 16:12 ` Leif Lindholm
2017-10-28 13:06 ` Ard Biesheuvel
0 siblings, 1 reply; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 16:12 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:09PM +0100, Ard Biesheuvel wrote:
> This adds the NetSecDxe driver provided by Socionext, but reworked
> extensively to improve compliance with the SimpleNetworkProtocol API,
> and to avoid uncached allocations for streaming DMA.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1000 ++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 88 ++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 +
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 265 ++++
> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++
> 21 files changed, 8013 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> new file mode 100644
> index 000000000000..7c3f12362f14
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> @@ -0,0 +1,1000 @@
> +/** @file
> +
> + Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/DmaLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/NetLib.h>
Sorted alphabetically, please?
> +
> +#include "NetsecDxe.h"
> +#include "netsec_for_uefi/pfdep.h"
Hmm, could that be folded into NetsecDxe.h?
> +
> +EFI_CPU_ARCH_PROTOCOL *mCpu;
> +
> +STATIC NETSEC_DEVICE_PATH NetsecPathTemplate = {
> + {
> + {
> + MESSAGING_DEVICE_PATH,
> + MSG_MAC_ADDR_DP,
> + {
> + (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)),
> + (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH) >> 8)
No space after (UINT8), space after sizeof?
> + }
> + },
> + {
> + {
> + 0
> + }
> + },
> + 0
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + sizeof(EFI_DEVICE_PATH_PROTOCOL), 0
Space after sizeof?
> + }
> + }
> +};
> +
> +STATIC
> +VOID
> +GetCurrentMacAddress(
> + OUT UINT8 *Mac)
> +{
> + Mac[0] = MmioRead8(MAC_ADDRESS + 3);
> + Mac[1] = MmioRead8(MAC_ADDRESS + 2);
> + Mac[2] = MmioRead8(MAC_ADDRESS + 1);
> + Mac[3] = MmioRead8(MAC_ADDRESS + 0);
> + Mac[4] = MmioRead8(MAC_ADDRESS + 7);
> + Mac[5] = MmioRead8(MAC_ADDRESS + 6);
Spaces after MmioRead8?
> +}
> +
> +/*
> + * Probe()
> + */
> +STATIC
> +EFI_STATUS
> +Probe (
> + IN EFI_HANDLE Handle,
> + IN NETSEC_DRIVER *LanDriver
> + )
> +{
> + ogma_param_t Param;
> + ogma_err_t ogma_err;
> + UINT64 dmac_hm_cmd_base, dmac_mh_cmd_base, core_cmd_base;
> + UINT32 dmac_hm_cmd_size, dmac_mh_cmd_size, core_cmd_size;
> +
> + SetMem (&Param, sizeof(Param), 0);
Space after sizeof?
> +
> + Param.use_gmac_flag = OGMA_TRUE;
> +
> + Param.use_jumbo_pkt_flag = PcdGet8 (PcdJumboPacket);
> +
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag = OGMA_TRUE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].little_endian_flag = OGMA_TRUE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].tmr_mode_flag = OGMA_FALSE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].entry_num = PcdGet16 (PcdEncTxDescNum);
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag = OGMA_TRUE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].little_endian_flag = OGMA_TRUE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].tmr_mode_flag = OGMA_FALSE;
> + Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].entry_num = PcdGet16 (PcdDecRxDescNum);
> +
> + // phy-interface
> + Param.gmac_config.phy_interface = OGMA_PHY_INTERFACE_RGMII;
> +
> + // Read and save the Permanent MAC Address
> + GetCurrentMacAddress (LanDriver->SnpMode.PermanentAddress.Addr);
> +
> + LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
> + DEBUG ((DEBUG_NET | DEBUG_INFO,
> + "Netsec: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
> + LanDriver->SnpMode.PermanentAddress.Addr[0],
> + LanDriver->SnpMode.PermanentAddress.Addr[1],
> + LanDriver->SnpMode.PermanentAddress.Addr[2],
> + LanDriver->SnpMode.PermanentAddress.Addr[3],
> + LanDriver->SnpMode.PermanentAddress.Addr[4],
> + LanDriver->SnpMode.PermanentAddress.Addr[5]));
> +
> + // Get hm microcode's physical addresses
> + dmac_hm_cmd_base = MmioRead32 (HM_ME_ADDRESS_H);
> + dmac_hm_cmd_base <<= 32;
> + dmac_hm_cmd_base |= MmioRead32 (HM_ME_ADDRESS_L);
> + dmac_hm_cmd_size = MmioRead32 (HM_ME_SIZE);
> +
> + // Get mh microcode's physical addresses
> + dmac_mh_cmd_base = MmioRead32 (MH_ME_ADDRESS_H);
> + dmac_mh_cmd_base <<= 32;
> + dmac_mh_cmd_base |= MmioRead32 (MH_ME_ADDRESS_L);
> + dmac_mh_cmd_size = MmioRead32 (MH_ME_SIZE);
> +
> + // Get core microcode's physical addresses
> + core_cmd_base = MmioRead32 (PACKET_ME_ADDRESS);
> + core_cmd_size = MmioRead32 (PACKET_ME_SIZE);
Could we have some clarifications in comments what hm, mh and core
are? Is their microcode self-contained in the component address space,
or do they need to come from a separate flash device?
> +
> + ogma_err = ogma_init ((VOID *)((UINTN)PcdGet32(PcdNetsecDxeBaseAddress)),
Space after PcdGet32?
I think you mentioned rewriting this to UEFI driver model? Is that
coming later?
> + Handle, &Param,
> + (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
> + (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
> + (VOID *)core_cmd_base, core_cmd_size,
> + &LanDriver->Handle);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
> + ogma_err));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + ogma_enable_top_irq (LanDriver->Handle,
> + OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/*
> + * UEFI Stop() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpStop (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
> + )
> +{
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> +
> + // Check Snp Instance
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
Not a fan of having a device-specific alias for which TPL to switch to
for all critical sections. Could just search and replace and drop the
definition (pointing out only here and at the definition).
> +
> + // Check state of the driver
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkStarted:
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Change the state
> + Snp->Mode->State = EfiSimpleNetworkStopped;
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * UEFI Initialize() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpInitialize (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
> + IN UINTN RxBufferSize OPTIONAL,
> + IN UINTN TxBufferSize OPTIONAL
> + )
> +{
> + NETSEC_DRIVER *LanDriver;
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> +
> + ogma_phy_link_status_t phy_link_status;
> + ogma_err_t ogma_err;
> + ogma_gmac_mode_t ogma_gmac_mode;
> +
> + // Check Snp Instance
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // Check that driver was started but not initialised
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkStarted:
> + break;
> + case EfiSimpleNetworkInitialized:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver already initialized\n"));
> + ReturnUnlock (EFI_SUCCESS);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Find the LanDriver structure
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
Space after _THIS?
> +
> + // ##### open
Hmm? A bit more description please.
> + ogma_err = ogma_clean_rx_desc_ring (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_RX);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_clean_rx_desc_ring() failed with error code %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_clean_tx_desc_ring() failed with error code %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_clear_desc_ring_irq_status (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
> + OGMA_CH_IRQ_REG_EMPTY);
> +
> + // ##### open_sub
A bit more description, please.
> + ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
> + OGMA_DESC_RING_ID_NRM_RX,
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_set_irq_coalesce_param(LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_RX,
> + RXINT_PKTCNT,
> + OGMA_FALSE,
> + RXINT_TMR_CNT_US);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_set_irq_coalesce_param() failed with error code %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
> + OGMA_DESC_RING_ID_NRM_TX,
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
> + OGMA_CH_IRQ_REG_EMPTY);
> +
> + // ##### configure_mac
In general, it feels like each of these comment headers indicate a
good place to break a block out into a helper function.
> + ogma_err = ogma_stop_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
Missing space.
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_stop_gmac() failed with error status %d\n",
> + ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_get_phy_link_status(LanDriver->Handle, PcdGet8(PcdPhyDevAddr), &phy_link_status);
Missing spaces.
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_get_phy_link_status() failed error code %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + SetMem (&ogma_gmac_mode, sizeof(ogma_gmac_mode_t), 0);
Missing space.
> + ogma_gmac_mode.link_speed = phy_link_status.link_speed;
> + ogma_gmac_mode.half_duplex_flag = (ogma_bool)phy_link_status.half_duplex_flag;
> + if ((!phy_link_status.half_duplex_flag) && PcdGet8(PcdFlowCtrl)) {
Missing space.
> + ogma_gmac_mode.flow_ctrl_enable_flag = (ogma_bool)PcdGet8(PcdFlowCtrl);
> + ogma_gmac_mode.flow_ctrl_start_threshold = (ogma_uint16)PcdGet16(PcdFlowCtrlStartThreshold);
> + ogma_gmac_mode.flow_ctrl_stop_threshold = (ogma_uint16)PcdGet16(PcdFlowCtrlStopThreshold);
> + ogma_gmac_mode.pause_time = (ogma_uint16)PcdGet16(PcdPauseTime);
> + }
> +
> + ogma_err = ogma_set_gmac_mode(LanDriver->Handle, &ogma_gmac_mode);
Missing space.
> + if(ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_set_gmac() failed with error status %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_start_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
Missing space.
> + if(ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_start_gmac() failed with error status %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Declare the driver as initialized
> + Snp->Mode->State = EfiSimpleNetworkInitialized;
> + Status = EFI_SUCCESS;
> +
> + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "NETSEC: Driver started\n"));
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * UEFI Shutdown () function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpShutdown (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
> + )
> +{
> + NETSEC_DRIVER *LanDriver;
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> +
> + // Check Snp Instance
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // First check that driver has already been initialized
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStarted:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver in stopped state\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Find the LanDriver structure
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
> +
> + ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
> +
> + ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
> + ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
> +
> + Snp->Mode->State = EfiSimpleNetworkStarted;
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +STATIC
> +VOID
> +EFIAPI
> +NotifyExitBoot (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
> + EFI_STATUS Status;
> +
> + Snp = Context;
> +
> + if (Snp->Mode != EfiSimpleNetworkStopped) {
> + Status = SnpShutdown (Snp);
> + if (!EFI_ERROR (Status)) {
> + SnpStop (Snp);
> + }
> + }
> + gBS->CloseEvent (Event);
> +}
> +
> +/*
> + * UEFI Start() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpStart (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp
> + )
> +{
> + EFI_SIMPLE_NETWORK_MODE *Mode;
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> + NETSEC_DRIVER *LanDriver;
> +
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
Missing space.
> +
> + // Check Snp instance
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> + Mode = Snp->Mode;
> +
> + // Check state of the driver
> + switch (Mode->State) {
> + case EfiSimpleNetworkStopped:
> + break;
> + case EfiSimpleNetworkStarted:
> + case EfiSimpleNetworkInitialized:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver already started\n"));
> + ReturnUnlock (EFI_ALREADY_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, NETSEC_TPL,
> + NotifyExitBoot, Snp, &LanDriver->ExitBootEvent);
> + ASSERT_EFI_ERROR (Status);
> +
> + // Change state
> + Mode->State = EfiSimpleNetworkStarted;
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +
> +}
> +
> +/*
> + * UEFI ReceiveFilters() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpReceiveFilters (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
> + IN UINT32 Enable,
> + IN UINT32 Disable,
> + IN BOOLEAN Reset,
> + IN UINTN NumMfilter OPTIONAL,
> + IN EFI_MAC_ADDRESS *Mfilter OPTIONAL
> + )
> +{
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> +
> + // Check Snp Instance
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // First check that driver has already been initialized
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStarted:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n", (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * UEFI GetStatus () function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpGetStatus (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
> + OUT UINT32 *IrqStat OPTIONAL,
> + OUT VOID **TxBuff OPTIONAL
> + )
> +{
> + NETSEC_DRIVER *LanDriver;
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> + pfdep_pkt_handle_t pkt_handle;
> + LIST_ENTRY *Link;
> +
> + ogma_phy_link_status_t phy_link_status;
> + ogma_err_t ogma_err;
> +
> + // Check preliminaries
> + if (Snp == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // Check that driver was started and initialised
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStarted:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Find the LanDriver structure
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
> +
> + // Update the media status
> + ogma_err = ogma_get_phy_link_status (LanDriver->Handle,
> + PcdGet8(PcdPhyDevAddr),
> + &phy_link_status);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_get_phy_link_status failed with error code: %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + Snp->Mode->MediaPresent = phy_link_status.up_flag;
> +
> + ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX);
> +
> + if (TxBuff != NULL) {
> + *TxBuff = NULL;
> + //
> + // Find a buffer in the list that has been released
> + //
> + for (Link = GetFirstNode (&LanDriver->TxBufferList);
> + !IsNull (&LanDriver->TxBufferList, Link);
> + Link = GetNextNode (&LanDriver->TxBufferList, Link)) {
> +
> + pkt_handle = BASE_CR (Link, PACKET_HANDLE, Link);
> + if (pkt_handle->Released) {
> + *TxBuff = pkt_handle->Buffer;
> + RemoveEntryList (Link);
> + FreePool (pkt_handle);
> + break;
> + }
> + }
> + }
> +
> + if (IrqStat != 0) {
> + *IrqStat = 0;
> + }
> +
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * UEFI Transmit() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpTransmit (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
> + IN UINTN HdrSize,
> + IN UINTN BufSize,
> + IN VOID *BufAddr,
> + IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
> + IN EFI_MAC_ADDRESS *DstAddr OPTIONAL,
> + IN UINT16 *Protocol OPTIONAL
> + )
> +{
> + NETSEC_DRIVER *LanDriver;
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> +
> + ogma_tx_pkt_ctrl_t tx_pkt_ctrl;
> + ogma_frag_info_t scat_info;
> + ogma_uint16 tx_avail_num;
> + ogma_err_t ogma_err;
> + UINT16 Proto;
> + pfdep_pkt_handle_t pkt_handle;
> +
> + // Check preliminaries
> + if ((Snp == NULL) || (BufAddr == NULL)) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", Snp, BufAddr));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + pkt_handle = AllocateZeroPool (sizeof *pkt_handle);
We tend to use () with sizeof, right?
> + if (pkt_handle == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + pkt_handle->Buffer = BufAddr;
> + pkt_handle->RecycleForTx = TRUE;
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // Check that driver was started and initialised
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStarted:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Find the LanDriver structure
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
Missing space.
> +
> + ogma_err = ogma_clear_desc_ring_irq_status (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX,
> + OGMA_CH_IRQ_REG_EMPTY);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_clear_desc_ring_irq_status failed with error code: %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_clean_tx_desc_ring failed with error code: %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Ensure header is correct size if non-zero
> + if (HdrSize) {
> + if (HdrSize != Snp->Mode->MediaHeaderSize) {
> + DEBUG ((DEBUG_ERROR, "NETSEC: SnpTransmit(): Invalid HdrSize %d\n",
> + HdrSize));
> + ReturnUnlock (EFI_INVALID_PARAMETER);
> + }
> +
> + if ((DstAddr == NULL) || (Protocol == NULL)) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
> + DstAddr, Protocol));
> + ReturnUnlock (EFI_INVALID_PARAMETER);
> + }
> +
> + // Copy destination address
> + CopyMem (BufAddr, (VOID *)DstAddr, NET_ETHER_ADDR_LEN);
> + // Copy source address
> + CopyMem (BufAddr + NET_ETHER_ADDR_LEN, (VOID *)SrcAddr, NET_ETHER_ADDR_LEN);
> + // Copy protocol
> + Proto = HTONS(*Protocol);
Missing space.
> + CopyMem (BufAddr + (NET_ETHER_ADDR_LEN * 2), (VOID *)&Proto, sizeof(UINT16));
Missing space (sizeof).
> + }
> +
> + Status = DmaMap (MapOperationBusMasterRead, BufAddr, &BufSize,
> + &scat_info.phys_addr, &pkt_handle->Mapping);
> + if (EFI_ERROR (Status)) {
> + goto ExitUnlock;
> + }
> +
> + scat_info.addr = BufAddr;
> + scat_info.len = BufSize;
> +
> + SetMem (&tx_pkt_ctrl, sizeof (ogma_tx_pkt_ctrl_t), 0);
> +
> + tx_pkt_ctrl.pass_through_flag = OGMA_TRUE;
> + tx_pkt_ctrl.target_desc_ring_id = OGMA_DESC_RING_ID_GMAC;
> +
> + // check empty slot
> + do {
> + tx_avail_num = ogma_get_tx_avail_num (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX);
> + } while (tx_avail_num < SCAT_NUM);
> +
> + // send
> + ogma_err = ogma_set_tx_pkt_data (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX,
> + &tx_pkt_ctrl,
> + SCAT_NUM,
> + &scat_info,
> + pkt_handle);
> +
> + if (ogma_err != OGMA_ERR_OK) {
> + DmaUnmap (pkt_handle->Mapping);
> + FreePool (pkt_handle);
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_set_tx_pkt_data failed with error code: %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + //
> + // Queue the descriptor so we can release the buffer once it has been
> + // consumed by the hardware.
> + //
> + InsertTailList (&LanDriver->TxBufferList, &pkt_handle->Link);
> +
> + gBS->RestoreTPL (SavedTpl);
> + return EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + FreePool (pkt_handle);
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * UEFI Receive() function
> + */
> +EFI_STATUS
> +EFIAPI
> +SnpReceive (
> + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
> + OUT UINTN *HdrSize OPTIONAL,
> + IN OUT UINTN *BuffSize,
> + OUT VOID *Data,
> + OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
> + OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,
> + OUT UINT16 *Protocol OPTIONAL
> + )
> +{
> + EFI_TPL SavedTpl;
> + EFI_STATUS Status;
> + NETSEC_DRIVER *LanDriver;
> +
> + ogma_err_t ogma_err;
> + ogma_rx_pkt_info_t rx_pkt_info;
> + ogma_frag_info_t rx_data;
> + ogma_uint16 len;
> + pfdep_pkt_handle_t pkt_handle;
> +
> + // Check preliminaries
> + if ((Snp == NULL) || (Data == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Serialize access to data and registers
> + SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> + // Check that driver was started and initialised
> + switch (Snp->Mode->State) {
> + case EfiSimpleNetworkInitialized:
> + break;
> + case EfiSimpleNetworkStarted:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + case EfiSimpleNetworkStopped:
> + DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> + ReturnUnlock (EFI_NOT_STARTED);
> + default:
> + DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> + (UINTN)Snp->Mode->State));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + // Find the LanDriver structure
> + LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
Missing space.
> +
> + if (ogma_get_rx_num (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX) > 0) {
> +
> + ogma_err = ogma_get_rx_pkt_data(LanDriver->Handle,
Missing space.
> + OGMA_DESC_RING_ID_NRM_RX,
> + &rx_pkt_info, &rx_data, &len, &pkt_handle);
> + if (ogma_err != OGMA_ERR_OK) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC: ogma_get_rx_pkt_data failed with error code: %d\n",
> + (INT32)ogma_err));
> + ReturnUnlock (EFI_DEVICE_ERROR);
> + }
> +
> + DmaUnmap (pkt_handle->Mapping);
> + pkt_handle->Mapping = NULL;
> +
> + CopyMem (Data, (VOID*)rx_data.addr, len);
> + *BuffSize = len;
> +
> + pfdep_free_pkt_buf (LanDriver->Handle, rx_data.len, rx_data.addr,
> + rx_data.phys_addr, PFDEP_TRUE, pkt_handle);
> + } else {
> + // not received any packets
> + ReturnUnlock (EFI_NOT_READY);
> + }
> +
> + if (HdrSize != NULL) {
> + *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
> + }
> +
> + ogma_clear_desc_ring_irq_status (LanDriver->Handle,
> + OGMA_DESC_RING_ID_NRM_TX,
> + OGMA_CH_IRQ_REG_EMPTY);
> +
> + ogma_clean_tx_desc_ring(LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
Missing space.
> +
> + ogma_enable_top_irq (LanDriver->Handle,
> + OGMA_TOP_IRQ_REG_NRM_TX | OGMA_TOP_IRQ_REG_NRM_RX);
> +
> + Status = EFI_SUCCESS;
> +
> + // Restore TPL and return
> +ExitUnlock:
> + gBS->RestoreTPL (SavedTpl);
> + return Status;
> +}
> +
> +/*
> + * Entry point for the Netxec driver
> + */
> +EFI_STATUS
> +NetsecDxeEntry (
> + IN EFI_HANDLE Handle,
> + IN EFI_SYSTEM_TABLE *SystemTable)
> +{
> + EFI_STATUS Status;
> + NETSEC_DRIVER *LanDriver;
> + EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
> + EFI_SIMPLE_NETWORK_MODE *SnpMode;
> + NETSEC_DEVICE_PATH *NetsecPath;
> +
> + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
> + ASSERT_EFI_ERROR(Status);
> +
> + // Allocate Resources
> + LanDriver = AllocateZeroPool (sizeof(NETSEC_DRIVER));
> + NetsecPath = AllocateCopyPool (sizeof(NETSEC_DEVICE_PATH),
Missing spaces 2 lines above.
(Maybe just a global search/replace in this file. I'll stop pointing
them out.)
> + &NetsecPathTemplate);
> +
> + // Initialize pointers
> + Snp = &(LanDriver->Snp);
> + SnpMode = &(LanDriver->SnpMode);
> + Snp->Mode = SnpMode;
> +
> + // Set the signature of the LAN Driver structure
> + LanDriver->Signature = NETSEC_SIGNATURE;
> +
> + // Probe the device
> + Status = Probe (Handle, LanDriver);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "NETSEC:NetsecDxeEntry(): Probe failed with status %d\n", Status));
> + return Status;
> + }
> +
> + // Assign fields and func pointers
> + Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
> + Snp->WaitForPacket = NULL;
> + Snp->Initialize = SnpInitialize;
> + Snp->Start = SnpStart;
> + Snp->Stop = SnpStop;
> + Snp->Reset = NULL;
> + Snp->Shutdown = SnpShutdown;
> + Snp->ReceiveFilters = SnpReceiveFilters;
> + Snp->StationAddress = NULL;
> + Snp->Statistics = NULL;
> + Snp->MCastIpToMac = NULL;
> + Snp->NvData = NULL;
> + Snp->GetStatus = SnpGetStatus;
> + Snp->Transmit = SnpTransmit;
> + Snp->Receive = SnpReceive;
> +
> + // Fill in simple network mode structure
> + SnpMode->State = EfiSimpleNetworkStopped;
> + SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN; // HW address is 6 bytes
> + SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD); // Size of an Ethernet header
> + SnpMode->MaxPacketSize = EFI_PAGE_SIZE; // Ethernet Frame (with VLAN tag +4 bytes)
> +
> + // Supported receive filters
> + SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
> + EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
> + EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
> + EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
> + EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
> +
> + // Initially-enabled receive filters
> + SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
> + EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
> + EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
> +
> + // Netsec has 64bit hash table. We can filter an infinite MACs, but
> + // higher-level software must filter out any hash collisions.
> + SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
> + SnpMode->MCastFilterCount = 0;
> + ZeroMem (&SnpMode->MCastFilter,
> + MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
> +
> + // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
> + SnpMode->IfType = NET_IFTYPE_ETHERNET;
> +
> + // Mac address is changeable
> + SnpMode->MacAddressChangeable = TRUE;
> +
> + // We can only transmit one packet at a time
> + SnpMode->MultipleTxSupported = FALSE;
> +
> + // MediaPresent checks for cable connection and partner link
> + SnpMode->MediaPresentSupported = TRUE;
> + SnpMode->MediaPresent = FALSE;
> +
> + // Set broadcast address
> + SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
> +
> + // Assign fields for device path
> + NetsecPath->Netsec.MacAddress = SnpMode->PermanentAddress;
> + NetsecPath->Netsec.IfType = SnpMode->IfType;
> +
> + InitializeListHead (&LanDriver->TxBufferList);
> +
> + // Initialise the protocol
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &LanDriver->ControllerHandle,
> + &gEfiSimpleNetworkProtocolGuid, Snp,
> + &gEfiDevicePathProtocolGuid, NetsecPath,
> + NULL);
> +
> + // Say what the status of loading the protocol structure is
> + if (EFI_ERROR(Status)) {
> + ogma_terminate (LanDriver->Handle);
> + FreePool (LanDriver);
> + }
> +
> + return Status;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> new file mode 100644
> index 000000000000..7537d1059b28
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> @@ -0,0 +1,47 @@
> +## @file
> +#
> +# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
Bump.
> + PACKAGE_NAME = OpenPlatformDriversNetNetsecDxePkg
> + PACKAGE_GUID = bd8ddfdd-2e8d-4081-8117-99405df3ffc8
> + PACKAGE_VERSION = 0.1
> +
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +
> +[Guids.common]
> + gNetsecDxeTokenSpaceGuid = { 0x47d6c028, 0x2413, 0x416d, { 0xa8, 0xef, 0xe4, 0x5c, 0x58, 0x83, 0x5e, 0x49 }}
> +
> +[PcdsFixedAtBuild.common]
> + # Netsec Ethernet Driver PCDs
> + gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x0|UINT32|0x00000000
> + gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x0|UINT32|0x00000001
> + gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|0x0|UINT16|0x00000002
> + gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|0x0|UINT16|0x00000003
> + gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0x0|UINT8|0x00000004
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007
> + gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008
> + gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|0x0|UINT8|0x00000009
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
> new file mode 100644
> index 000000000000..f0acdc1448d7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
> @@ -0,0 +1,88 @@
> +/** @file
> +
> + Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NETSEC_DXE_H_
> +#define __NETSEC_DXE_H_
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +
> +// Synchronization TPLs
> +#define NETSEC_TPL TPL_CALLBACK
I'm not sure I like this central redefinition of a specific TPL to use
everywhere in the driver where it needs to be raised.
> +
> +/*--------------- Simple Network Driver entry point functions ----------------*/
> +
> +// Refer to the Simple Network Protocol section (21.1)
> +// in the UEFI 2.3.1 Specification for documentation.
> +
> +#define ReturnUnlock(s) do { Status = (s); goto ExitUnlock; } while (0)
> +
> +/*------------------------------------------------------------------------------
> + NETSEC Information Structure
> +------------------------------------------------------------------------------*/
> +
> +typedef struct {
> + // Driver signature
> + UINT32 Signature;
> + EFI_HANDLE ControllerHandle;
> +
> + // EFI SNP protocol instances
> + EFI_SIMPLE_NETWORK_PROTOCOL Snp;
> + EFI_SIMPLE_NETWORK_MODE SnpMode;
> +
> + // EFI Snp statistics instance
> + EFI_NETWORK_STATISTICS Stats;
> +
> + // ogma handle
> + ogma_handle_t Handle;
> +
> + // List of submitted TX buffers
> + LIST_ENTRY TxBufferList;
> +
> + EFI_EVENT ExitBootEvent;
> +} NETSEC_DRIVER;
> +
> +#define NETSEC_SIGNATURE SIGNATURE_32('n', 't', 's', 'c')
> +#define INSTANCE_FROM_SNP_THIS(a) CR(a, NETSEC_DRIVER, Snp, NETSEC_SIGNATURE)
Parentheses around that 'a', please.
> +
> +typedef struct {
> + MAC_ADDR_DEVICE_PATH Netsec;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NETSEC_DEVICE_PATH;
> +
> +/*------------------------------------------------------------------------------
> +
> +------------------------------------------------------------------------------*/
> +
> +#define EEPROM_BASE ((UINT32)PcdGet32(PcdEepRomBase))
Missing space.
> +
> +#define MAC_ADDRESS (0x00 + EEPROM_BASE)
> +
> +#define HM_ME_ADDRESS_H (0x08 + EEPROM_BASE)
> +#define HM_ME_ADDRESS_L (0x0C + EEPROM_BASE)
> +#define HM_ME_SIZE (0x10 + EEPROM_BASE)
> +
> +#define MH_ME_ADDRESS_H (0x14 + EEPROM_BASE)
> +#define MH_ME_ADDRESS_L (0x18 + EEPROM_BASE)
> +#define MH_ME_SIZE (0x1C + EEPROM_BASE)
> +
> +#define PACKET_ME_ADDRESS (0x20 + EEPROM_BASE)
> +#define PACKET_ME_SIZE (0x24 + EEPROM_BASE)
Not necessary, but you _could_ #undef EEPROM_BASE here.
> +
> +#define SCAT_NUM 1
> +
> +#define RXINT_TMR_CNT_US 0
> +#define RXINT_PKTCNT 1
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> new file mode 100644
> index 000000000000..42de56d89c30
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> @@ -0,0 +1,69 @@
> +## @file
> +#
> +# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = NetsecDxe
> + FILE_GUID = a4eed3af-9837-46b3-9275-c71cb47071f9
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 0.1
> + ENTRY_POINT = NetsecDxeEntry
> +
> +[Sources]
> + NetsecDxe.c
> +
> + netsec_for_uefi/pfdep_uefi.c
> + netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> + netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> + netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> + netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + NetworkPkg/NetworkPkg.dec
> + Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DevicePathLib
> + DmaLib
> + IoLib
> + NetLib
> + SynchronizationLib
> + TimerLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Protocols]
> + gEfiSimpleNetworkProtocolGuid
> + gEfiDevicePathProtocolGuid
Sorted, please.
> +
> +[FixedPcd]
> + gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress
> + gNetsecDxeTokenSpaceGuid.PcdEepRomBase
> + gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum
> + gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum
> + gNetsecDxeTokenSpaceGuid.PcdJumboPacket
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrl
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold
> + gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr
> + gNetsecDxeTokenSpaceGuid.PcdPauseTime
Be nice if these were alphabetically sorted too, unless there is some
other logical order that escapes me.
> +
> +[Depex]
> + gEfiCpuArchProtocolGuid
OK - below is imported code: I will not comment on coding style
compliance.
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
> new file mode 100644
> index 000000000000..336325109e33
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
> @@ -0,0 +1,736 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_API_H
> +#define OGMA_API_H
> +
> +#include "ogma_version.h"
> +#include "netsec_for_uefi/ogma_config.h"
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "netsec_for_uefi/pfdep.h"
> +/**
> + * Check configuration macro settings.
> + */
> +#ifdef OGMA_CONFIG_CLK_HZ
> +#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
> +#error "OGMA_CONFIG_CLK_HZ is not appropriate."
> +#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
> +#else /* ! OGMA_CONFIG_CLK_HZ */
> +#error "OGMA_CONFIG_CLK_HZ is not given."
> +#endif /* OGMA_CONFIG_CLK_HZ */
> +
> +#ifndef OGMA_CONFIG_GMAC_CLK_HZ
> +#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
> +#endif
> +
> +/**
> + * Number of hardware limits
> + */
> +
> +
> +/**
> + * Number of Common Descriptor ring id
> + */
> +#define OGMA_DESC_RING_ID_NRM_TX 0
> +#define OGMA_DESC_RING_ID_NRM_RX 1
> +
> +#define OGMA_DESC_RING_ID_GMAC 15
> +#define OGMA_DESC_RING_ID_MAX 1
> +
> +/**
> + * Numbre of TCP Segmentation length limits
> + */
> +#define OGMA_TCP_SEG_LEN_MAX 1460
> +#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
> +
> +/**
> + * Number of ER check result for received packet
> + */
> +#define OGMA_RX_ER_RESULT_NG 0x1
> +#define OGMA_RX_ER_RESULT_OK 0x0
> +
> +/**
> + * Number of checksum calculation result for received packet
> + */
> +#define OGMA_RX_CKSUM_RESULT_OK 0x1
> +#define OGMA_RX_CKSUM_RESULT_NG 0x2
> +#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
> +
> +/**
> + * Number of ErrorCode for received packet
> + */
> +#define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR 0x2
> +#define OGMA_RX_ERRCODE_IP_HEADER_ERR 0x1
> +#define OGMA_RX_ERRCODE_NONE 0x0
> +
> +/**
> + * Number of top interrupt enable register bit field
> + */
> +#define OGMA_TOP_IRQ_REG_ME_START (1UL << 20)
> +#define OGMA_TOP_IRQ_REG_MAC (1UL << 19)
> +#define OGMA_TOP_IRQ_REG_PKT (1UL << 18)
> +#define OGMA_TOP_IRQ_REG_BOOTCODE_TX (1UL << 5)
> +#define OGMA_TOP_IRQ_REG_NRM_RX (1UL << 1)
> +#define OGMA_TOP_IRQ_REG_NRM_TX (1UL << 0)
> +
> +
> +/**
> + * Number of top channel enable register bit field
> + */
> +#define OGMA_CH_IRQ_REG_EMPTY (1UL << 17)
> +#define OGMA_CH_IRQ_REG_ERR (1UL << 16)
> +#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
> +#define OGMA_CH_IRQ_REG_TIMEUP (1UL << 14)
> +#define OGMA_CH_IRQ_REG_RCV (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
> +
> +/**
> + * Number of top channel enable register bit field for F_NETSEC_C
> + */
> +#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
> +#define OGMA_CH_IRQ_REG_SND (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
> +
> +
> +/**
> + * Number of packet interrupt enable register bit field
> + */
> +#define OGMA_PKT_IRQ_MAC_ER (1UL << 5)
> +#define OGMA_PKT_IRQ_JUMBO_ER (1UL << 4)
> +#define OGMA_PKT_IRQ_CHKSUM_ER (1UL << 3)
> +#define OGMA_PKT_IRQ_HD_INCOMPLETE (1UL << 2)
> +#define OGMA_PKT_IRQ_HD_ER (1UL << 1)
> +#define OGMA_PKT_IRQ_DRP_NO_MATCH (1UL << 0)
> +
> +
> +/**
> + * Number of mac irq enable register bit field
> + */
> +#define OGMA_MAC_IRQ_INT_PMT (1UL << 31)
> +#define OGMA_MAC_IRQ_INT_SBD (1UL << 30)
> +#define OGMA_MAC_IRQ_INT_LPI (1UL << 29)
> +#define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27)
> +#define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26)
> +#define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25)
> +#define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24)
> +#define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23)
> +
> +
> +/**
> + * Number of SR IER register bit field
> + */
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TTI (1U << 29)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GPI (1U << 28)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GMI (1U << 27)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GLI (1U << 26)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_NIS (1U << 16)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_AIS (1U << 15)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ERI (1U << 14)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_FBI (1U << 13)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ETI (1U << 10)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RWT (1U << 9)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RPS (1U << 8)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RU (1U << 7)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RI (1U << 6)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_UNF (1U << 5)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_OVF (1U << 4)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TJT (1U << 3)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TU (1U << 2)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TPS (1U << 1)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TI (1U << 0)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TTI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_GPI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_GMI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_GLI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +#define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_RI | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TU | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
> + OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +/**
> + * Number of ISR IMR register bit field
> + */
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI (1U << 9)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_COI (1U << 7)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_TI (1U << 6)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_RI (1U << 5)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_MI (1U << 4)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_PI (1U << 3)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI (1U << 0)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_TSI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_COI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_TI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_RI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_MI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_PI | \
> + OGMA_GMAC_INT_SBD_IRQ_ISR_RGI)
> +
> +/**
> + * Number of LPICSR register bit field
> + */
> +#define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19)
> +#define OGMA_GMAC_LPICSR_REG_PLSEN (1U << 18)
> +#define OGMA_GMAC_LPICSR_REG_PLS (1U << 17)
> +#define OGMA_GMAC_LPICSR_REG_LPIEN (1U << 16)
> +#define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9)
> +#define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8)
> +#define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3)
> +#define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2)
> +#define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1)
> +#define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0)
> +
> +/**
> + * Number of RGSR register bit field
> + */
> +#define OGMA_GMAC_RGSR_REG_LS (1U << 3)
> +#define OGMA_GMAC_RGSR_REG_LSP (1U << 1)
> +#define OGMA_GMAC_RGSR_REG_LM (1U << 0)
> +
> +/**
> + * Number of various limits
> + */
> +#define OGMA_DESC_ENTRY_NUM_MIN 2
> +#define OGMA_DESC_ENTRY_NUM_MAX 2047
> +#define OGMA_INT_PKTCNT_MAX 2047
> +#define OGMA_L4_MIN_LEN_MAX 64
> +
> +/**
> + * Number of ogma phy interface setting
> + */
> +#define OGMA_PHY_INTERFACE_GMII 0
> +#define OGMA_PHY_INTERFACE_RGMII 1
> +#define OGMA_PHY_INTERFACE_RMII 4
> +
> +/**
> + * Number of ogma link speed setting
> + */
> +#define OGMA_PHY_LINK_SPEED_1G 0
> +#define OGMA_PHY_LINK_SPEED_100M 1U
> +#define OGMA_PHY_LINK_SPEED_10M 2U
> +#define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U
> +
> +/**
> + * Number of flow control limits
> + */
> +#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95
> +#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX 95
> +#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN 5
> +
> +enum ogma_err_e{
> + OGMA_ERR_OK = 0,
> + OGMA_ERR_PARAM,
> + OGMA_ERR_ALLOC,
> + OGMA_ERR_BUSY,
> + OGMA_ERR_RANGE,
> + OGMA_ERR_DATA,
> + OGMA_ERR_NOTAVAIL,
> + OGMA_ERR_INTERRUPT,
> + OGMA_ERR_AGAIN,
> + OGMA_ERR_INVALID,
> +};
> +
> +typedef void *ogma_handle_t;
> +typedef struct ogma_param_s ogma_param_t;
> +typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
> +typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
> +typedef enum ogma_err_e ogma_err_t;
> +typedef ogma_uint8 ogma_desc_ring_id_t;
> +typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
> +typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
> +typedef struct ogma_frag_info_s ogma_frag_info_t;
> +typedef struct ogma_gmac_config_s ogma_gmac_config_t;
> +typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
> +
> +struct ogma_gmac_config_s{
> + ogma_uint8 phy_interface;
> +};
> +
> +struct ogma_pkt_ctrl_param_s{
> + ogma_uint log_chksum_er_flag:1;
> + ogma_uint log_hd_imcomplete_flag:1;
> + ogma_uint log_hd_er_flag:1;
> + ogma_uint drp_no_match_flag:1;
> +};
> +
> +struct ogma_desc_ring_param_s{
> + ogma_uint valid_flag:1;
> + ogma_uint little_endian_flag:1;
> + ogma_uint tmr_mode_flag:1;
> + ogma_uint16 entry_num;
> +};
> +
> +struct ogma_param_s{
> +
> + ogma_uint use_gmac_flag:1;
> + ogma_uint use_jumbo_pkt_flag:1;
> + ogma_pkt_ctrl_param_t pkt_ctrl_param;
> + ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
> + ogma_gmac_config_t gmac_config;
> + ogma_uint8 mac_addr[6];
> +};
> +
> +struct ogma_tx_pkt_ctrl_s{
> + ogma_uint pass_through_flag:1;
> + ogma_uint cksum_offload_flag:1;
> + ogma_uint tcp_seg_offload_flag:1;
> + ogma_desc_ring_id_t target_desc_ring_id;
> + ogma_uint16 tcp_seg_len;
> +};
> +
> +struct ogma_rx_pkt_info_s{
> + ogma_uint fragmented_flag:1;
> + ogma_uint err_flag:1;
> + ogma_uint rx_cksum_result:2;
> + ogma_uint8 err_code;
> +};
> +
> +struct ogma_frag_info_s{
> + pfdep_phys_addr_t phys_addr;
> + void *addr;
> + ogma_uint32 len;
> +};
> +
> +struct ogma_gmac_mode_s{
> + ogma_uint half_duplex_flag:1;
> + ogma_uint flow_ctrl_enable_flag:1;
> + ogma_uint8 link_speed;
> + ogma_uint16 flow_ctrl_start_threshold;
> + ogma_uint16 flow_ctrl_stop_threshold;
> + ogma_uint16 pause_time;
> +};
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +typedef struct ogma_stat_info_s {
> + ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
> + ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
> +} ogma_stat_info_t;
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +typedef struct ogma_gmac_int_sbd_regs_s{
> + ogma_uint32 base;
> + ogma_uint32 extended;
> +} ogma_gmac_int_sbd_regs_t;
> +
> +typedef struct ogma_phy_link_status_s{
> + ogma_uint up_flag:1;
> + ogma_uint auto_nego_enable_flag:1;
> + ogma_uint auto_nego_complete_flag:1;
> + ogma_uint half_duplex_flag:1;
> + ogma_uint latched_link_down_flag:1;
> + ogma_uint lpi_capable_flag:1;
> + ogma_uint8 link_speed;
> +} ogma_phy_link_status_t;
> +
> +/**************************
> +***************************
> +***************************/
> +
> +ogma_err_t ogma_init (
> + void *base_addr,
> + pfdep_dev_handle_t dev_handle,
> + const ogma_param_t *param_p,
> + const void *dma_hm_mc_addr,
> + ogma_uint32 dma_hm_mc_len,
> + const void *dma_mh_mc_addr,
> + ogma_uint32 dma_mh_mc_len,
> + const void *pktc_mc_addr,
> + ogma_uint32 pktc_mc_len,
> + ogma_handle_t *ogma_handle_p
> + );
> +
> +void ogma_terminate (
> + ogma_handle_t ogma_handle
> + );
> +
> +ogma_err_t ogma_start_gmac (
> + ogma_handle_t ogma_handle,
> + ogma_bool rx_flag,
> + ogma_bool tx_flag
> + );
> +
> +ogma_err_t ogma_stop_gmac (
> + ogma_handle_t ogma_handle,
> + ogma_bool rx_flag,
> + ogma_bool tx_flag
> + );
> +
> +ogma_err_t ogma_set_gmac_mode (
> + ogma_handle_t ogma_handle,
> + const ogma_gmac_mode_t *gmac_mode_p
> + );
> +
> +void ogma_set_phy_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr,
> + ogma_uint16 value
> + );
> +
> +ogma_uint16 ogma_get_phy_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr
> + );
> +
> +ogma_err_t ogma_get_gmac_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool *valid_flag_p,
> + ogma_gmac_mode_t *gmac_mode_p,
> + ogma_bool *rx_running_flag_p,
> + ogma_bool *tx_running_flag_p
> + );
> +
> +ogma_uint32 ogma_get_top_irq_enable (
> + ogma_handle_t ogma_handle
> + );
> +
> +ogma_uint32 ogma_get_top_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + );
> +
> +#define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_top_irq_status(ogma_handle,mask_flag)
> +
> +ogma_err_t ogma_clear_top_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + );
> +
> +ogma_uint32 ogma_get_desc_ring_irq_enable (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_uint32 ogma_get_desc_ring_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_bool mask_flag
> + );
> +
> +#define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \
> +ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag)
> +
> +
> +
> +ogma_err_t ogma_clear_desc_ring_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 value
> + );
> +
> +ogma_uint32 ogma_get_pkt_irq_enable (
> + ogma_handle_t ogma_handle
> + );
> +
> +ogma_uint32 ogma_get_pkt_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + );
> +
> +#define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_pkt_irq_status(ogma_handle,mask_flag)
> +
> +
> +ogma_err_t ogma_clear_pkt_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + );
> +
> +/* ogma_desc_ring_access.c */
> +ogma_err_t ogma_start_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_err_t ogma_stop_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_uint16 ogma_get_rx_num (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_uint16 ogma_get_tx_avail_num (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_err_t ogma_clean_tx_desc_ring(
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_err_t ogma_clean_rx_desc_ring(
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + );
> +
> +ogma_err_t ogma_set_tx_pkt_data (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> + ogma_uint8 scat_num,
> + const ogma_frag_info_t *scat_info_p,
> + pfdep_pkt_handle_t pkt_handle
> + );
> +
> +ogma_err_t ogma_get_rx_pkt_data (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_rx_pkt_info_t *rx_pkt_info_p,
> + ogma_frag_info_t *frag_info_p,
> + ogma_uint16 *len_p,
> + pfdep_pkt_handle_t *pkt_handle_p
> + );
> +
> +ogma_err_t ogma_enable_top_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_disable_top_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_enable_desc_ring_irq (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_disable_desc_ring_irq (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_enable_pkt_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_disable_pkt_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_uint32 ogma_get_hw_ver (
> + ogma_handle_t ogma_handle
> + );
> +
> +ogma_uint32 ogma_get_mcr_ver (
> + ogma_handle_t ogma_handle
> + );
> +
> +/**
> + * Set up IRQ coalesce parameters.
> + *
> + * [Note]
> + * - This is a tentative implementation.
> + * Not tested enough. Use with care.
> + *
> + * - Call this function after every invocation of ogma_start_desc_ring()
> + * because ogma_start_desc_ring() resets IRQ coalesce settings.
> + *
> + */
> +ogma_err_t ogma_set_irq_coalesce_param (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint16 int_pktcnt,
> + ogma_bool int_tmr_unit_ms_flag,
> + ogma_uint16 int_tmr_cnt
> + );
> +
> +ogma_uint32 ogma_get_mac_irq_enable (
> + ogma_handle_t ogma_handle
> + );
> +
> +
> +ogma_uint32 ogma_get_mac_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + );
> +
> +#define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_mac_irq_status(ogma_handle,mask_flag)
> +
> +
> +ogma_err_t ogma_clear_mac_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + );
> +
> +ogma_err_t ogma_enable_mac_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +ogma_err_t ogma_disable_mac_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + );
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +/**
> + * Get statistics information.
> + */
> +ogma_err_t ogma_get_stat_info (
> + ogma_handle_t ogma_handle,
> + ogma_stat_info_t *stat_info_p,
> + ogma_bool clear_flag
> + );
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +ogma_err_t ogma_set_gmac_lpictrl_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + );
> +
> +ogma_err_t ogma_get_gmac_lpictrl_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p
> + );
> +
> +ogma_err_t ogma_set_gmac_lpitimer_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint16 ls_timer_ms,
> + ogma_uint16 tw_timer_ms
> + );
> +
> +ogma_err_t ogma_get_gmac_lpitimer_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint16 *ls_timer_ms_p,
> + ogma_uint16 *tw_timer_ms_p
> + );
> +
> +void ogma_set_phy_mmd_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr,
> + ogma_uint16 value
> + );
> +
> +ogma_uint16 ogma_get_phy_mmd_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + );
> +
> +ogma_err_t ogma_get_phy_link_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_phy_link_status_t *phy_link_status_p
> + );
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
> + ogma_handle_t ogma_handle
> + );
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + );
> +
> +#define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag)
> +
> +ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + );
> +
> +ogma_err_t ogma_enable_gmac_int_sbd_irq (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + );
> +
> +ogma_err_t ogma_disable_gmac_int_sbd_irq (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + );
> +
> +ogma_err_t ogma_get_gmac_rgmii_status_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p
> + );
> +
> +#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
> +ogma_err_t ogma_read_gmac_stat (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p,
> + ogma_bool reset_flag
> + );
> +#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
> +
> +ogma_err_t ogma_reset_gmac_stat (
> + ogma_handle_t ogma_handle
> + );
> +
> +/**************************
> +***************************
> +***************************/
> +
> +#endif /* OGMA_API_H*/
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
> new file mode 100644
> index 000000000000..7c39b7c9cdd7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
> @@ -0,0 +1,45 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_BASIC_TYPE_H
> +#define OGMA_BASIC_TYPE_H
> +#include "netsec_for_uefi/pfdep.h"
> +
> +/**
> + *
> + */
> +#define OGMA_TRUE PFDEP_TRUE
> +#define OGMA_FALSE PFDEP_FALSE
> +
> +/**
> + * OGMA SDK BASIC DATA TYPE
> + */
> +typedef pfdep_int8 ogma_int8;
> +typedef pfdep_uint8 ogma_uint8;
> +typedef pfdep_int16 ogma_int16;
> +typedef pfdep_uint16 ogma_uint16;
> +typedef pfdep_int32 ogma_int32;
> +typedef pfdep_uint32 ogma_uint32;
> +typedef int ogma_int;
> +typedef unsigned int ogma_uint;
> +typedef pfdep_bool ogma_bool;
> +typedef pfdep_char ogma_char;
> +
> +#ifdef PFDEP_INT64_AVAILABLE
> +typedef signed long long ogma_int64;
> +typedef unsigned long long ogma_uint64;
> +#endif /* PFDEP_INT64_AVAILABLE*/
> +
> +#endif /* OGMA_BASIC_TYPE_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
> new file mode 100644
> index 000000000000..61335b96db77
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
> @@ -0,0 +1,24 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_VERSION_H
> +#define OGMA_VERSION_H
> +
> +#define OGMA_VER_NETSEC (0x00050050UL)
> +
> +#define OGMA_INVALID_VER 0x0
> +#define OGMA_VER_MAJOR_NUM(x) (x&0xffff0000UL)
*twitch*
Although I will point out that the above macro is buggy.
> +
> +#endif /* OGMA_VERSION_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> new file mode 100644
> index 000000000000..7b399beaedb2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> @@ -0,0 +1,88 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +void ogma_set_mac_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 addr,
> + ogma_uint32 value)
> +{
> +
> + ogma_uint32 cmd;
> +
> + ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> + /*
> + * Argument check is omitted because this function is
> + * of private use only.
> + */
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_DATA,
> + value);
> +
> + cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_CMD,
> + cmd);
> +
> + /*
> + * Waits until BUSY bit is cleared.
> + */
> + while ( ( ogma_read_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_CMD)
> + & OGMA_GMAC_CMD_ST_BUSY)
> + != 0) {
> + ;
> + }
> +}
> +
> +ogma_uint32 ogma_get_mac_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 addr)
> +{
> + ogma_uint32 cmd;
> +
> + ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> + /*
> + * Argument check is omitted because this function is
> + * of private use only.
> + */
> +
> + cmd = addr | OGMA_GMAC_CMD_ST_READ;
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_CMD,
> + cmd);
> +
> + /*
> + * Waits until BUSY bit is cleared.
> + */
> + while ( ( ogma_read_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_CMD)
> + & OGMA_GMAC_CMD_ST_BUSY)
> + != 0) {
> + ;
> + }
> + return ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DATA);
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
> new file mode 100644
> index 000000000000..a81b9249f4a2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
> @@ -0,0 +1,52 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_BASIC_ACCESS_H
> +#define OGMA_BASIC_ACCESS_H
> +
> +#include "ogma_internal.h"
> +
> +static __inline void ogma_write_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 reg_addr,
> + ogma_uint32 value
> + )
> +{
> +
> + pfdep_iomem_write( (void *) ( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
> + ( reg_addr << 2) ),
> + value);
> +}
> +
> +static __inline ogma_uint32 ogma_read_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 reg_addr
> + )
> +{
> +
> + return ( ogma_uint32)pfdep_iomem_read( (void *)( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
> + ( reg_addr << 2) ) );
> +}
> +
> +void ogma_set_mac_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 addr,
> + ogma_uint32 value);
> +
> +ogma_uint32 ogma_get_mac_reg (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 addr);
> +
> +#endif/* OGMA_BASIC_ACCESS_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> new file mode 100644
> index 000000000000..a38aff3ce4a5
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> @@ -0,0 +1,1391 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +#include "ogma_desc_ring_access_internal.h"
> +
> +
> +const ogma_uint32 ogma_desc_start_reg_addr_upper[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_DESC_START_UP,
> + OGMA_REG_ADDR_NRM_RX_DESC_START_UP,
> +};
> +
> +const ogma_uint32 ogma_desc_start_reg_addr_lower[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_DESC_START_LW,
> + OGMA_REG_ADDR_NRM_RX_DESC_START_LW,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> + OGMA_REG_ADDR_NRM_TX_INTEN,
> + OGMA_REG_ADDR_NRM_RX_INTEN,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> + OGMA_REG_ADDR_NRM_TX_INTEN_SET,
> + OGMA_REG_ADDR_NRM_RX_INTEN_SET,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> + OGMA_REG_ADDR_NRM_TX_INTEN_CLR,
> + OGMA_REG_ADDR_NRM_RX_INTEN_CLR,
> +};
> +
> +static const ogma_uint32 int_tmr_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_TXINT_TMR,
> + OGMA_REG_ADDR_NRM_RX_RXINT_TMR,
> +};
> +
> +static const ogma_uint32 rx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> + 0,
> + OGMA_REG_ADDR_NRM_RX_PKTCNT,
> +};
> +
> +static const ogma_uint32 tx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_PKTCNT,
> + 0,
> +
> +};
> +
> +static const ogma_uint32 int_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT,
> + OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT,
> +};
> +
> +static const ogma_uint32 tx_done_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> + OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT,
> + 0,
> +};
> +
> +
> +STATIC void ogma_set_tx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> + ogma_bool first_flag,
> + ogma_bool last_flag,
> + ogma_bool trs_flag,
> + const ogma_frag_info_t *frag_info_p,
> + pfdep_pkt_handle_t pkt_handle);
> +
> +STATIC void ogma_set_rx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + const ogma_frag_info_t *frag_info_p,
> + pfdep_pkt_handle_t pkt_handle);
> +
> +STATIC void ogma_get_rx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + ogma_rx_pkt_info_t *rx_pkt_info_p,
> + ogma_frag_info_t *frag_info_p,
> + ogma_uint16 *len_p,
> + pfdep_pkt_handle_t *pkt_handle_p);
> +
> +STATIC void ogma_clean_tx_desc_ring_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +STATIC void ogma_clean_rx_desc_ring_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +STATIC void ogma_inc_desc_head_idx (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 increment);
> +
> +STATIC void ogma_inc_desc_tail_idx (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 increment);
> +
> +STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
> + ogma_ctrl_t *ctrl_p,
> + const ogma_desc_ring_t *desc_ring_p
> + );
> +
> +STATIC ogma_uint16 ogma_get_tx_done_num_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +static __inline void ogma_desc_ring_cpy_to_mem(
> + void *dst_p,
> + void *src_p,
> + ogma_uint32 len)
> +{
> + pfdep_memcpy(dst_p,src_p,len);
> +}
> +
> +static __inline void ogma_desc_ring_cpy_from_mem(
> + void *dst_p,
> + void *src_p,
> + ogma_uint32 len)
> +{
> + pfdep_memcpy(dst_p,src_p,len);
> +}
> +
> +static __inline void ogma_desc_ring_memclr(
> + void *dst_p,
> + ogma_uint32 len)
> +{
> + pfdep_memset(dst_p,0,len);
> +}
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +ogma_err_t ogma_alloc_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> +
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_desc_ring_t *desc_ring_p = &ctrl_p->desc_ring[ring_id];
> + ogma_desc_ring_param_t *desc_ring_param_p = &ctrl_p->desc_ring[ring_id].param;
> + pfdep_err_t pfdep_err;
> +
> + if ( ( ctrl_p->param.desc_ring_param[ring_id].valid_flag) &&
> + ( ( ctrl_p->param.desc_ring_param[ring_id].entry_num <
> + OGMA_DESC_ENTRY_NUM_MIN) ||
> + ( ctrl_p->param.desc_ring_param[ring_id].entry_num >
> + OGMA_DESC_ENTRY_NUM_MAX) ) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Please set entry_num between %d and %d.\n",
> + OGMA_DESC_ENTRY_NUM_MIN, OGMA_DESC_ENTRY_NUM_MAX);
> + return OGMA_ERR_PARAM;
> + }
> +
> + desc_ring_p->ring_id = ring_id;
> +
> + pfdep_memcpy( desc_ring_param_p,
> + &ctrl_p->param.desc_ring_param[ring_id],
> + sizeof( ogma_desc_ring_param_t) );
> +
> + if ( !desc_ring_param_p->valid_flag) {
> +
> + desc_ring_p->desc_ring_phys_addr = ctrl_p->dummy_desc_entry_phys_addr;
> +
> + ogma_write_reg( ctrl_p,
> + ogma_desc_start_reg_addr_upper[ring_id],
> + (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
> + ogma_write_reg( ctrl_p,
> + ogma_desc_start_reg_addr_lower[ring_id],
> + (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
> +
> + return OGMA_ERR_OK;
> + }
> +
> + switch ( ring_id) {
> + case OGMA_DESC_RING_ID_NRM_TX:
> + desc_ring_p->tx_desc_ring_flag = OGMA_TRUE;
> + desc_ring_p->desc_entry_len = sizeof( ogma_tx_desc_entry_t);
> + break;
> +
> + case OGMA_DESC_RING_ID_NRM_RX:
> + desc_ring_p->rx_desc_ring_flag = OGMA_TRUE;
> + desc_ring_p->desc_entry_len = sizeof( ogma_rx_desc_entry_t);
> + break;
> +
> + default:
> + pfdep_assert(0);
> + }
> +
> + if ( ( pfdep_err = pfdep_init_hard_lock ( &desc_ring_p->inten_reg_hard_lock) )
> + != PFDEP_ERR_OK) {
> + pfdep_memset( desc_ring_param_p,
> + 0,
> + sizeof( ogma_desc_ring_param_t) );
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Failed to inten_reg_hard_lock's initialization.\n");
> + return OGMA_ERR_ALLOC;
> + }
> +
> + if ( ( pfdep_err = pfdep_init_soft_lock ( &desc_ring_p->soft_lock) )
> + != PFDEP_ERR_OK) {
> + pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
> + pfdep_memset( desc_ring_param_p,
> + 0,
> + sizeof( ogma_desc_ring_param_t) );
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Failed to soft_lock's initialization.\n");
> + return OGMA_ERR_ALLOC;
> + }
> +
> + if ( ( pfdep_err = pfdep_dma_malloc (
> + ( pfdep_dev_handle_t) ctrl_p->dev_handle,
> + ( pfdep_uint32) desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num,
> + ( void **) &desc_ring_p->desc_ring_cpu_addr,
> + ( pfdep_phys_addr_t *) &desc_ring_p->desc_ring_phys_addr) )
> + != PFDEP_ERR_OK) {
> + ogma_err = OGMA_ERR_ALLOC;
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Failed to desc_ring entry memory allocation.\n");
> + goto err;
> + }
> +
> + ogma_desc_ring_memclr(
> + desc_ring_p->desc_ring_cpu_addr,
> + ( ogma_uint32)desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num);
> +
> + ogma_write_reg( ctrl_p,
> + ogma_desc_start_reg_addr_upper[ring_id],
> + (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
> + ogma_write_reg( ctrl_p,
> + ogma_desc_start_reg_addr_lower[ring_id],
> + (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
> +
> + if ( ( desc_ring_p->frag_info_p =
> + pfdep_malloc( sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num) )
> + == NULL) {
> + ogma_err = OGMA_ERR_ALLOC;
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Failed to fragment infomation memory allocation.\n");
> + goto err;
> + }
> +
> + pfdep_memset(
> + desc_ring_p->frag_info_p,
> + 0,
> + sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num);
> +
> + if ( ( desc_ring_p->priv_data_p =
> + pfdep_malloc( sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num) )
> + == NULL) {
> + ogma_err = OGMA_ERR_ALLOC;
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_alloc_desc_ring.\n"
> + "Failed to private data memory allocation.\n");
> + goto err;
> + }
> +
> + pfdep_memset(
> + desc_ring_p->priv_data_p,
> + 0,
> + sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num);
> +
> + return OGMA_ERR_OK;
> +
> +err:
> + ogma_free_desc_ring( ctrl_p, desc_ring_p);
> + return ogma_err;
> +}
> +
> +void ogma_free_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> +
> + if ( !desc_ring_p->param.valid_flag) {
> + return ;
> + }
> + if ( ogma_is_pkt_desc_ring ( desc_ring_p) ) {
> + if ( ( desc_ring_p->desc_ring_cpu_addr != NULL) &&
> + ( desc_ring_p->frag_info_p != NULL) &&
> + ( desc_ring_p->priv_data_p != NULL) ) {
> + ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
> + }
> + }
> + if ( desc_ring_p->desc_ring_cpu_addr != NULL) {
> + pfdep_dma_free( ctrl_p->dev_handle,
> + ( ogma_uint32)desc_ring_p->desc_entry_len *
> + desc_ring_p->param.entry_num,
> + desc_ring_p->desc_ring_cpu_addr,
> + desc_ring_p->desc_ring_phys_addr);
> + }
> +
> + if ( desc_ring_p->frag_info_p != NULL) {
> + pfdep_free(desc_ring_p->frag_info_p);
> + }
> +
> + if ( desc_ring_p->priv_data_p != NULL) {
> + pfdep_free( desc_ring_p->priv_data_p);
> + }
> +
> + pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
> +
> + pfdep_uninit_soft_lock ( &desc_ring_p->soft_lock);
> +
> + pfdep_memset( desc_ring_p, 0, sizeof( ogma_desc_ring_t) );
> +}
> +
> +ogma_err_t ogma_setup_rx_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> + ogma_uint16 idx;
> + ogma_frag_info_t frag_info= {0,0,0};
> +
> + pfdep_err_t pfdep_err;
> + pfdep_pkt_handle_t tmp_pkt_handle;
> +
> + frag_info.len = ctrl_p->rx_pkt_buf_len;
> +
> + for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
> + if ( ( pfdep_err = pfdep_alloc_pkt_buf (
> + ( pfdep_dev_handle_t)ctrl_p->dev_handle,
> + ( ogma_uint16)frag_info.len,
> + ( void **)&frag_info.addr,
> + ( pfdep_phys_addr_t *)&frag_info.phys_addr,
> + ( pfdep_pkt_handle_t *)&tmp_pkt_handle) )
> + != PFDEP_ERR_OK) {
> + ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_setup_rx_desc_ring.\n"
> + "Failed to rx packet memory allocation.\n");
> + return OGMA_ERR_ALLOC;
> + }
> + ogma_set_rx_desc_entry( ctrl_p,
> + desc_ring_p,
> + idx,
> + &frag_info,
> + tmp_pkt_handle);
> + }
> + return OGMA_ERR_OK;
> +}
> +
> +void ogma_uninit_pkt_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> + ogma_uint16 idx;
> + ogma_uint32 tmp;
> + ogma_bool last_flag;
> +
> + for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
> + if ( desc_ring_p->frag_info_p[idx].addr == NULL ) {
> + continue;
> + }
> +
> + tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
> +
> + last_flag = ( ( ( tmp >> 8) & 0x1) != 0);
> +
> + pfdep_free_pkt_buf (
> + ctrl_p->dev_handle,
> + desc_ring_p->frag_info_p[idx].len,
> + desc_ring_p->frag_info_p[idx].addr,
> + desc_ring_p->frag_info_p[idx].phys_addr,
> + last_flag,
> + desc_ring_p->priv_data_p[idx].pkt_handle);
> + }
> +
> + /* clear frag_info_p */
> + pfdep_memset( desc_ring_p->frag_info_p,
> + 0,
> + sizeof( ogma_frag_info_t) * desc_ring_p->param.entry_num);
> +
> + /* clear pkt_handle_p */
> + pfdep_memset( desc_ring_p->priv_data_p,
> + 0,
> + sizeof( ogma_desc_entry_priv_t) * desc_ring_p->param.entry_num);
> +
> + /* clear desc ring entry*/
> + ogma_desc_ring_memclr ( desc_ring_p->desc_ring_cpu_addr,
> + ( ogma_uint32)desc_ring_p->desc_entry_len *
> + desc_ring_p->param.entry_num);
> +}
> +
> +STATIC void ogma_set_tx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> + ogma_bool first_flag,
> + ogma_bool last_flag,
> + ogma_bool trs_flag,
> + const ogma_frag_info_t *frag_info_p,
> + pfdep_pkt_handle_t pkt_handle
> + )
> +{
> + ogma_tx_desc_entry_t tx_desc_entry;
> + ogma_uint32 attr, i, *debug_desc_entry_p;
> +
> + ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
> +
> + pfdep_memset( &tx_desc_entry, 0, sizeof( ogma_tx_desc_entry_t) );
> +
> + attr = ( 1UL << OGMA_TX_PKT_DESC_RING_OWN_FIELD) |
> + ( desc_ring_p->ring_id << OGMA_TX_PKT_DESC_RING_DRID_FIELD) |
> + ( tx_pkt_ctrl_p->pass_through_flag <<
> + OGMA_TX_PKT_DESC_RING_PT_FIELD) |
> + ( tx_pkt_ctrl_p->target_desc_ring_id <<
> + OGMA_TX_PKT_DESC_RING_TDRID_FIELD) |
> + ( first_flag << OGMA_TX_PKT_DESC_RING_FS_FIELD) |
> + ( last_flag << OGMA_TX_PKT_DESC_RING_LS_FIELD) |
> + ( tx_pkt_ctrl_p->cksum_offload_flag <<
> + OGMA_TX_PKT_DESC_RING_CO_FIELD) |
> + ( tx_pkt_ctrl_p->tcp_seg_offload_flag <<
> + OGMA_TX_PKT_DESC_RING_SO_FIELD) |
> + ( trs_flag << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
> +
> + if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
> + attr |= ( 0x1U << OGMA_TX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
> + }
> +
> + tx_desc_entry.attr = attr;
> +
> + tx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
> +
> + tx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
> +
> + tx_desc_entry.buf_len_info =
> + ( tx_pkt_ctrl_p->tcp_seg_len << 16) | frag_info_p->len;
> +
> + ogma_desc_ring_cpy_to_mem( ( (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> + desc_ring_p->desc_entry_len * idx) ),
> + ( void *)&tx_desc_entry,
> + desc_ring_p->desc_entry_len);
> +
> + debug_desc_entry_p = ( ogma_uint32 *)&tx_desc_entry;
> +
> + for ( i = 0; i < ( sizeof( ogma_tx_desc_entry_t) >> 2); i++) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "%08x\n", debug_desc_entry_p[i]);
> + }
> +
> + desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
> + desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
> + desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
> + desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
> +
> +}
> +
> +STATIC void ogma_set_rx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + const ogma_frag_info_t *frag_info_p,
> + pfdep_pkt_handle_t pkt_handle
> + )
> +{
> + ogma_rx_desc_entry_t rx_desc_entry;
> +
> + ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
> +
> + pfdep_memset( &rx_desc_entry, 0, sizeof ( ogma_rx_desc_entry_t) );
> +
> + rx_desc_entry.attr = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
> + ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
> + ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
> +
> + rx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
> +
> + rx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
> +
> + rx_desc_entry.buf_len_info = frag_info_p->len;
> +
> + if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
> + rx_desc_entry.attr |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
> + }
> +
> + ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> + desc_ring_p->desc_entry_len * idx + 4) ),
> + ( void *) ( ( pfdep_cpu_addr_t)&rx_desc_entry + 4),
> + ( ogma_uint32)( desc_ring_p->desc_entry_len - 4U) );
> +
> + pfdep_write_mem_barrier();
> +
> + ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> + desc_ring_p->desc_entry_len * idx) ),
> + ( void *)&rx_desc_entry,
> + 4);
> +
> + desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
> + desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
> + desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
> + desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
> +}
> +
> +STATIC void ogma_get_rx_desc_entry (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + ogma_rx_pkt_info_t *rx_pkt_info_p,
> + ogma_frag_info_t *frag_info_p,
> + ogma_uint16 *len_p,
> + pfdep_pkt_handle_t *pkt_handle_p)
> +{
> + ogma_uint32 *debug_desc_entry_p;
> + ogma_rx_desc_entry_t rx_desc_entry;
> +
> + ogma_check_desc_own_sanity( ctrl_p, desc_ring_p, idx, 0);
> +
> + pfdep_memset( &rx_desc_entry, 0, sizeof( ogma_rx_desc_entry_t) );
> + pfdep_memset( rx_pkt_info_p, 0, sizeof( ogma_rx_pkt_info_t) );
> +
> + ogma_desc_ring_cpy_from_mem( &rx_desc_entry,
> + (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> + desc_ring_p->desc_entry_len * idx),
> + desc_ring_p->desc_entry_len);
> +
> + debug_desc_entry_p = (ogma_uint32 *)&rx_desc_entry;
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "%08x\n", *debug_desc_entry_p);
> +
> + *len_p = rx_desc_entry.buf_len_info >> 16;
> +
> + rx_pkt_info_p->fragmented_flag =
> + ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_FR_FIELD) & 0x1; /* FR*/
> +
> + rx_pkt_info_p->err_flag =
> + ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ER_FIELD) & 0x1; /* ER */
> +
> + rx_pkt_info_p->rx_cksum_result =
> + ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_CO_FIELD) & 0x3; /* CO */
> +
> + rx_pkt_info_p->err_code =
> + ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD) &
> + OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK; /* Error Code */
> +
> + pfdep_memcpy( frag_info_p,
> + &desc_ring_p->frag_info_p[idx],
> + sizeof(ogma_frag_info_t) );
> +
> + *pkt_handle_p = desc_ring_p->priv_data_p[idx].pkt_handle;
> +}
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +STATIC __inline ogma_uint16 ogma_calc_busy_entry_num (
> + ogma_uint16 head_idx,
> + ogma_uint16 tail_idx,
> + ogma_uint16 entry_num,
> + ogma_bool full_flag
> + )
> +{
> +
> + ogma_int16 busy_entry_num;
> +
> + if (full_flag) {
> + busy_entry_num = entry_num;
> + } else if (head_idx >= tail_idx) {
> + busy_entry_num = head_idx - tail_idx;
> + } else {
> + busy_entry_num = entry_num + head_idx - tail_idx;
> + }
> +
> + return busy_entry_num;
> +
> +}
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +STATIC void ogma_clean_tx_desc_ring_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> +
> + ogma_uint32 tmp;
> +
> + ogma_get_tx_done_num_sub( ctrl_p, desc_ring_p);
> +
> + while( ( (desc_ring_p->tail_idx != desc_ring_p->head_idx) ||
> + desc_ring_p->full_flag) && ( desc_ring_p->tx_done_num != 0) ) {
> +
> + tmp = ogma_get_desc_ring_attr(desc_ring_p,
> + desc_ring_p->tail_idx);
> +
> + pfdep_free_pkt_buf (
> + ctrl_p->dev_handle,
> + desc_ring_p->frag_info_p[desc_ring_p->tail_idx].len,
> + desc_ring_p->frag_info_p[desc_ring_p->tail_idx].addr,
> + desc_ring_p->frag_info_p[desc_ring_p->tail_idx].phys_addr,
> + ( ( ( tmp >> OGMA_TX_PKT_DESC_RING_LS_FIELD) & 0x1) != 0),
> + desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> +
> + pfdep_memset( &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> + 0,
> + sizeof( ogma_frag_info_t) );
> +
> + ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> +
> + if ( ( tmp & ( 1UL << OGMA_TX_PKT_DESC_RING_LS_FIELD) ) != 0) {
> +
> + pfdep_assert( desc_ring_p->tx_done_num != 0);
> +
> + desc_ring_p->tx_done_num--;
> +
> + }
> + }
> +
> +}
> +
> +STATIC void ogma_clean_rx_desc_ring_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> +
> + while( desc_ring_p->full_flag ||
> + ( desc_ring_p->tail_idx != desc_ring_p->head_idx) ) {
> +
> + ogma_set_rx_desc_entry(
> + ctrl_p,
> + desc_ring_p,
> + desc_ring_p->tail_idx,
> + &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> + desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> +
> + --desc_ring_p->rx_num;
> + ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> + }
> +
> + pfdep_assert( desc_ring_p->rx_num == 0);/* error check*/
> +
> +}
> +
> +STATIC void ogma_inc_desc_head_idx (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 increment)
> +{
> + ogma_uint32 sum;
> +
> + if ( ( desc_ring_p->tail_idx > desc_ring_p->head_idx) ||
> + desc_ring_p->full_flag) {
> + pfdep_assert( increment <=
> + ( desc_ring_p->tail_idx -
> + desc_ring_p->head_idx));
> + } else {
> + pfdep_assert( increment <=
> + ( desc_ring_p->param.entry_num +
> + desc_ring_p->tail_idx -
> + desc_ring_p->head_idx) );
> + }
> +
> + sum = (ogma_uint32) desc_ring_p->head_idx + increment;
> +
> + if ( sum >= desc_ring_p->param.entry_num) {
> + sum -= desc_ring_p->param.entry_num;
> + }
> +
> + desc_ring_p->head_idx = ( ogma_uint16)sum;
> +
> + if ( desc_ring_p->head_idx == desc_ring_p->tail_idx) {
> + desc_ring_p->full_flag = OGMA_TRUE;
> + }
> +
> +}
> +
> +STATIC void ogma_inc_desc_tail_idx (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 increment)
> +{
> + ogma_uint32 sum;
> +
> + if ( ( desc_ring_p->head_idx >= desc_ring_p->tail_idx) &&
> + ( !desc_ring_p->full_flag) ) {
> + pfdep_assert( increment <=
> + ( desc_ring_p->head_idx -
> + desc_ring_p->tail_idx) );
> + } else {
> + pfdep_assert( increment <=
> + ( desc_ring_p->param.entry_num +
> + desc_ring_p->head_idx -
> + desc_ring_p->tail_idx) );
> + }
> +
> + sum = (ogma_uint32) desc_ring_p->tail_idx + increment;
> +
> + if ( sum >= desc_ring_p->param.entry_num) {
> + sum -= desc_ring_p->param.entry_num;
> + }
> +
> + desc_ring_p->tail_idx = ( ogma_uint16)sum;
> +
> + desc_ring_p->full_flag = OGMA_FALSE;
> +}
> +
> +
> +STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
> + ogma_ctrl_t *ctrl_p,
> + const ogma_desc_ring_t *desc_ring_p
> + )
> +{
> + ogma_uint16 tx_avail_num;
> +
> + if ( desc_ring_p->full_flag) {
> +
> + tx_avail_num = 0;
> +
> + } else if ( desc_ring_p->tail_idx > desc_ring_p->head_idx) {
> +
> + tx_avail_num = desc_ring_p->tail_idx - desc_ring_p->head_idx;
> +
> + } else {
> +
> + tx_avail_num =
> + desc_ring_p->param.entry_num +
> + desc_ring_p->tail_idx -
> + desc_ring_p->head_idx;
> + }
> +
> + return tx_avail_num;
> +}
> +
> +STATIC ogma_uint16 ogma_get_tx_done_num_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + )
> +{
> + ogma_uint32 value;
> +
> + value = ogma_read_reg ( ctrl_p,
> + tx_done_pkt_cnt_reg_addr[desc_ring_p->ring_id] );
> +
> + desc_ring_p->tx_done_num += value;
> +
> + return desc_ring_p->tx_done_num;
> +}
> +
> +
> +ogma_err_t ogma_start_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> +
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> + pfdep_err_t pfdep_err;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + if ( desc_ring_p->running_flag) {
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return OGMA_ERR_BUSY;
> + }
> +
> + if ( desc_ring_p->rx_desc_ring_flag) {
> +
> + ogma_write_reg ( ctrl_p,
> + desc_ring_irq_inten_set_reg_addr[ring_id],
> + OGMA_CH_IRQ_REG_RCV);
> +
> + ogma_write_reg ( ctrl_p,
> + int_pkt_cnt_reg_addr[ring_id],
> + 1);
> + }
> +
> + if ( desc_ring_p->tx_desc_ring_flag) {
> +
> +
> + value = OGMA_CH_IRQ_REG_EMPTY;
> +
> +
> + ogma_write_reg ( ctrl_p,
> + desc_ring_irq_inten_set_reg_addr[ring_id],
> + value);
> +
> + ogma_write_reg ( ctrl_p,
> + int_pkt_cnt_reg_addr[ring_id],
> + 1);
> +
> + }
> +
> + desc_ring_p->running_flag = OGMA_TRUE;
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + return ogma_err;
> +}
> +
> +
> +ogma_err_t ogma_stop_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> + pfdep_err_t pfdep_err;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id] ) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + if ( !desc_ring_p->running_flag) {
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return OGMA_ERR_INVALID;
> + }
> +
> + value = ( OGMA_CH_IRQ_REG_RCV |
> + OGMA_CH_IRQ_REG_EMPTY |
> + OGMA_CH_IRQ_REG_SND);
> +
> + ogma_write_reg ( ctrl_p,
> + desc_ring_irq_inten_clr_reg_addr[ring_id],
> + value);
> +
> + desc_ring_p->running_flag = OGMA_FALSE;
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_uint16 ogma_get_rx_num (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> +
> + ogma_uint32 result;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p = NULL;
> + ogma_desc_ring_id_t tmp_ring_id;
> +
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> + pfdep_err_t pfdep_err;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_rx_num.\n"
> + "Please set valid argument.\n");
> + return 0;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_rx_num.\n"
> + "Please set valid argument.\n");
> + return 0;
> + }
> +
> + tmp_ring_id = ring_id;
> +
> + if (! ctrl_p->desc_ring[tmp_ring_id].rx_desc_ring_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_rx_num.\n"
> + "Please select rx packet desc ring or bulk desc ring.\n");
> + return 0;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_rx_num.\n"
> + "Failed to get soft lock.\n");
> + return 0;
> + }
> +
> + result = ogma_read_reg( ctrl_p, rx_pkt_cnt_reg_addr[tmp_ring_id]);
> +
> + desc_ring_p->rx_num += result;
> +
> + if ( desc_ring_p->rx_desc_ring_flag && ( result != 0) ) {
> + ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, ( ogma_uint16)result);
> + }
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + return desc_ring_p->rx_num;
> +}
> +
> +
> +ogma_uint16 ogma_get_tx_avail_num (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> +
> + ogma_uint16 result;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_id_t tmp_ring_id;
> + ogma_desc_ring_t *desc_ring_p = NULL;
> +
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> + pfdep_err_t pfdep_err;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ||
> + ( !ctrl_p->desc_ring[ring_id].param.valid_flag) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_tx_avail_num.\n"
> + "Please select valid argument.\n");
> + return 0;
> + }
> +
> + tmp_ring_id = ring_id;
> +
> + if (! ctrl_p->desc_ring[tmp_ring_id].tx_desc_ring_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_tx_avail_num.\n"
> + "Please select tx packet desc ring or bulk desc ring.\n");
> + return 0;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_tx_avail_num.\n"
> + "Failed to get soft lock.\n");
> + return 0;
> + }
> +
> + if ( !desc_ring_p->running_flag) {
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_tx_avail_num.\n"
> + "Please select running desc ring.\n");
> + return 0;
> + }
> +
> + result = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return result;
> +}
> +
> +ogma_err_t ogma_clean_tx_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> +
> + pfdep_err_t pfdep_err;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + ogma_clean_tx_desc_ring_sub(ctrl_p, desc_ring_p);
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return OGMA_ERR_OK;
> +
> +
> +}
> +
> +ogma_err_t ogma_clean_rx_desc_ring (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> +
> + pfdep_err_t pfdep_err;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + ogma_clean_rx_desc_ring_sub(ctrl_p, desc_ring_p);
> +
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_set_tx_pkt_data (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> + ogma_uint8 scat_num,
> + const ogma_frag_info_t *scat_info_p,
> + pfdep_pkt_handle_t pkt_handle
> + )
> +{
> + ogma_uint i;
> + ogma_uint16 tx_avail_num;
> + ogma_uint32 sum_len = 0;
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> +
> + pfdep_err_t pfdep_err;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
> +
> + if ( ( ctrl_p == NULL) ||
> + ( tx_pkt_ctrl_p == NULL) ||
> + ( scat_info_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + {
> + if ( !ctrl_p->param.use_gmac_flag ||
> + ( tx_pkt_ctrl_p->target_desc_ring_id != OGMA_DESC_RING_ID_GMAC) ) {
> + return OGMA_ERR_DATA;
> + }
> + }
> +
> +
> + if ( tx_pkt_ctrl_p->tcp_seg_offload_flag &&
> + ( !tx_pkt_ctrl_p->cksum_offload_flag) ) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( tx_pkt_ctrl_p->tcp_seg_offload_flag) {
> +
> + if ( tx_pkt_ctrl_p->tcp_seg_len == 0) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( ctrl_p->param.use_jumbo_pkt_flag) {
> + if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_JUMBO_SEG_LEN_MAX) {
> + return OGMA_ERR_DATA;
> + }
> + } else {
> + if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_SEG_LEN_MAX) {
> + return OGMA_ERR_DATA;
> + }
> + }
> +
> + } else {
> + if ( tx_pkt_ctrl_p->tcp_seg_len != 0) {
> + return OGMA_ERR_DATA;
> + }
> + }
> +
> +
> + if ( scat_num == 0) {
> + return OGMA_ERR_RANGE;
> + }
> +
> + for ( i = 0; i < scat_num; i++) {
> + if ( ( scat_info_p[i].len == 0) ||
> + ( scat_info_p[i].len > 0xffffU) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_set_tx_pkt_data.\n"
> + "Pleas check scat_info_p[%u].len.\n",
> + i);
> + return OGMA_ERR_DATA;
> + }
> + sum_len += scat_info_p[i].len;
> + }
> +
> + if ( !tx_pkt_ctrl_p->tcp_seg_offload_flag) {
> +
> + if ( ctrl_p->param.use_jumbo_pkt_flag) {
> + if ( sum_len > OGMA_MAX_TX_JUMBO_PKT_LEN) {
> + return OGMA_ERR_DATA;
> + }
> + } else {
> + if ( sum_len > OGMA_MAX_TX_PKT_LEN) {
> + return OGMA_ERR_DATA;
> + }
> + }
> +
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + if ( !desc_ring_p->running_flag) {
> + ogma_err = OGMA_ERR_NOTAVAIL;
> + goto end;
> + }
> +
> + tx_avail_num = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
> +
> + if ( scat_num > tx_avail_num ) {
> + ogma_err = OGMA_ERR_BUSY;
> + goto end;
> + }
> +
> + for ( i = 0; i < scat_num; i++) {
> +
> +
> + ogma_set_tx_desc_entry(
> + ctrl_p,
> + desc_ring_p,
> + desc_ring_p->head_idx,
> + tx_pkt_ctrl_p,
> + ( i == 0),
> + ( i == ( scat_num - 1U) ),
> + OGMA_TRUE,
> + &scat_info_p[i],
> + pkt_handle);
> + ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, 1);
> + }
> +
> + pfdep_write_mem_barrier();
> +
> + ogma_write_reg( ctrl_p,
> + tx_pkt_cnt_reg_addr[ring_id],
> + (ogma_uint32)1);
> +
> +end:
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_get_rx_pkt_data (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_rx_pkt_info_t *rx_pkt_info_p,
> + ogma_frag_info_t *frag_info_p,
> + ogma_uint16 *len_p,
> + pfdep_pkt_handle_t *pkt_handle_p
> + )
> +{
> +
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> + ogma_frag_info_t tmp_frag_info;
> +
> + pfdep_err_t pfdep_err;
> + pfdep_pkt_handle_t tmp_pkt_handle;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
> +
> + if ( ( ctrl_p == NULL) ||
> + ( rx_pkt_info_p == NULL) ||
> + ( frag_info_p == NULL) ||
> + ( len_p == NULL) ||
> + ( pkt_handle_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + if ( ( pfdep_err = pfdep_acquire_soft_lock(
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + if ( desc_ring_p->rx_num == 0 ) {
> + ogma_err = OGMA_ERR_INVALID;
> + goto end;
> + }
> +
> + tmp_frag_info.len = ctrl_p->rx_pkt_buf_len;
> +
> + pfdep_read_mem_barrier();
> +
> + if ( ( pfdep_err = pfdep_alloc_pkt_buf (
> + ctrl_p->dev_handle,
> + tmp_frag_info.len,
> + &tmp_frag_info.addr,
> + &tmp_frag_info.phys_addr,
> + &tmp_pkt_handle) ) != PFDEP_ERR_OK) {
> + ogma_set_rx_desc_entry( ctrl_p,
> + desc_ring_p,
> + desc_ring_p->tail_idx,
> + &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> + desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> + ogma_err = OGMA_ERR_ALLOC;
> +
> + } else {
> +
> + ogma_get_rx_desc_entry( ctrl_p,
> + desc_ring_p,
> + desc_ring_p->tail_idx,
> + rx_pkt_info_p,
> + frag_info_p,
> + len_p,
> + pkt_handle_p);
> +
> +
> + ogma_set_rx_desc_entry( ctrl_p,
> + desc_ring_p,
> + desc_ring_p->tail_idx,
> + &tmp_frag_info,
> + tmp_pkt_handle);
> + }
> +
> + ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> +
> + --desc_ring_p->rx_num;
> +
> +end:
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_set_irq_coalesce_param (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint16 int_pktcnt,
> + ogma_bool int_tmr_unit_ms_flag,
> + ogma_uint16 int_tmr_cnt
> + )
> +{
> +
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( int_pktcnt > OGMA_INT_PKTCNT_MAX) {
> + return OGMA_ERR_RANGE;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id]) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + ogma_write_reg( ctrl_p,
> + int_pkt_cnt_reg_addr[ring_id],
> + int_pktcnt);
> +
> + ogma_write_reg( ctrl_p,
> + int_tmr_reg_addr[ring_id],
> + ( ( ( ( ogma_uint32)int_tmr_unit_ms_flag) << 31) |
> + int_tmr_cnt) );
> +
> + return ogma_err;
> +
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
> new file mode 100644
> index 000000000000..34490e2d1c78
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
> @@ -0,0 +1,111 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_DESC_RING_ACCESS_INTERNAL_H
> +#define OGMA_DESC_RING_ACCESS_INTERNAL_H
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "ogma_internal.h"
> +
> +#define OGMA_TX_PKT_DESC_RING_OWN_FIELD (31)
> +#define OGMA_TX_PKT_DESC_RING_LD_FIELD (30)
> +#define OGMA_TX_PKT_DESC_RING_DRID_FIELD (24)
> +#define OGMA_TX_PKT_DESC_RING_PT_FIELD (21)
> +#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD (16)
> +#define OGMA_TX_PKT_DESC_RING_FS_FIELD (9)
> +#define OGMA_TX_PKT_DESC_RING_LS_FIELD (8)
> +#define OGMA_TX_PKT_DESC_RING_CO_FIELD (7)
> +#define OGMA_TX_PKT_DESC_RING_SO_FIELD (6)
> +#define OGMA_TX_PKT_DESC_RING_USRKEY_FIELD (5)
> +#define OGMA_TX_PKT_DESC_RING_TRS_FIELD (4)
> +
> +#define OGMA_RX_PKT_DESC_RING_OWN_FIELD (31)
> +#define OGMA_RX_PKT_DESC_RING_LD_FIELD (30)
> +#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD (24)
> +#define OGMA_RX_PKT_DESC_RING_FR_FIELD (23)
> +#define OGMA_RX_PKT_DESC_RING_ER_FIELD (21)
> +#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
> +#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD (12)
> +#define OGMA_RX_PKT_DESC_RING_FS_FIELD (9)
> +#define OGMA_RX_PKT_DESC_RING_LS_FIELD (8)
> +#define OGMA_RX_PKT_DESC_RING_CO_FIELD (6)
> +
> +#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
> +
> +#define OGMA_MAX_TX_PKT_LEN 1518U
> +#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
> +
> +typedef struct ogma_tx_desc_entry_s ogma_tx_desc_entry_t;
> +typedef struct ogma_rx_desc_entry_s ogma_rx_desc_entry_t;
> +
> +struct ogma_tx_desc_entry_s{
> +
> + ogma_uint32 attr;
> +
> + ogma_uint32 data_buf_addr_upper;
> +
> + ogma_uint32 data_buf_addr_lower;
> +
> + ogma_uint32 buf_len_info;
> +};
> +
> +struct ogma_rx_desc_entry_s{
> +
> + ogma_uint32 attr;
> +
> + ogma_uint32 data_buf_addr_upper;
> +
> + ogma_uint32 data_buf_addr_lower;
> +
> + ogma_uint32 buf_len_info;
> +};
> +
> +static __inline ogma_bool ogma_is_pkt_desc_ring (
> + const ogma_desc_ring_t *desc_ring_p
> + )
> +{
> + return ( desc_ring_p->rx_desc_ring_flag ||
> + desc_ring_p->tx_desc_ring_flag);
> +}
> +
> +static __inline ogma_uint32 ogma_get_desc_ring_attr (
> + const ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx
> + )
> +{
> + ogma_uint32 *addr =
> + (ogma_uint32 *)
> + ((pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> + desc_ring_p->desc_entry_len * idx);
> +
> + return *addr;
> +}
> +
> +
> +
> +static __inline void ogma_check_desc_own_sanity (
> + ogma_ctrl_t *ctrl_p,
> + const ogma_desc_ring_t *desc_ring_p,
> + ogma_uint16 idx,
> + ogma_uint expected_own)
> +{
> + ogma_uint32 tmp;
> + ( void)ctrl_p; /* Suppress compiler warning */
> +
> + tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
> + pfdep_assert( ( tmp >> 31) == expected_own);
> +}
> +
> +#endif /* OGMA_DESC_RING_ACCESS_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> new file mode 100644
> index 000000000000..d08bb53a54e8
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> @@ -0,0 +1,1454 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_config.h"
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +
> +
> +/**********************************************************************
> + * Constant definitions
> + **********************************************************************/
> +
> +/**
> + * Clock range index for F_GMAC4MT::GAR::CR field.
> + */
> +#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
> +#else
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
> +#endif
> +
> +
> +/**********************************************************************
> + * Local function declarations
> + **********************************************************************/
> +static void ogma_set_phy_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr,
> + ogma_uint16 value
> + );
> +
> +static ogma_uint16 ogma_get_phy_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr
> + );
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> +void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p);
> +#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +static void ogma_set_phy_target_mmd_reg_addr (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + );
> +
> +static void ogma_set_phy_mmd_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr,
> + ogma_uint16 value
> + );
> +
> +static ogma_uint16 ogma_get_phy_mmd_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + );
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +ogma_err_t ogma_start_gmac (
> + ogma_handle_t ogma_handle,
> + ogma_bool rx_flag,
> + ogma_bool tx_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + pfdep_err_t pfdep_err;
> + ogma_err_t ogma_err;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( !ctrl_p->gmac_mode_valid_flag) {
> + return OGMA_ERR_INVALID;
> + }
> +
> + if ( ( !rx_flag) && ( !tx_flag) ) {
> + return OGMA_ERR_OK;
> + }
> +
> + if ( ctrl_p->gmac_rx_running_flag &&
> + ctrl_p->gmac_tx_running_flag) {
> + return OGMA_ERR_OK;
> + }
> +
> +
> + if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) &&
> + !tx_flag) {
> + return OGMA_ERR_OK;
> + }
> +
> + if ( ( tx_flag && ctrl_p->gmac_tx_running_flag) &&
> + !rx_flag ) {
> + return OGMA_ERR_OK;
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "%s call.\n", __func__);
> +
> + if ( (! ctrl_p->gmac_rx_running_flag) &&
> + (! ctrl_p->gmac_tx_running_flag) ) {
> +
> + /* Initializes F_GMAC4MT */
> + if ( ctrl_p->gmac_mode.link_speed ==
> + OGMA_PHY_LINK_SPEED_1G) {
> + /* Writes 0 to FGMAC4 MCR */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_MCR,
> + 0);
> + } else {
> + /* Writes PS bit to FGMAC4 MCR */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_MCR,
> + OGMA_GMAC_MCR_10M_HALF);/* 10M half Reset */
> + }
> +
> + /* F_GMAC4MT soft reset*/
> + if ( ( ogma_err = ogma_softreset_gmac( ctrl_p)) != OGMA_ERR_OK) {
> + return ogma_err;
> + }
> +
> + /* MAC desc soft reset */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
> + OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
> +
> + /* Wait MAC desc soft reset */
> + pfdep_err = pfdep_msleep( 1);
> +
> + if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_start_gmac.\n");
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "Wait for MAC desc soft reset error.\n");
> +
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + /* Check MAC desc soft reset done */
> + if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_SOFT_RST) &
> + OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "ogma_start_gmac():MAC desc soft reset timeout. Try Again.\n");
> +
> + return OGMA_ERR_AGAIN;
> + }
> +
> + /* MAC desc init */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_DESC_INIT,
> + OGMA_MAC_DESC_INIT_REG_INIT);
> +
> + /* Wait MAC desc init done */
> + pfdep_err = pfdep_msleep( 1);
> +
> + if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_start_gmac().\n");
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "Wait for MAC desc init done error.\n");
> +
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + /* Check MAC desc init done */
> + if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT) &
> + OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "ogma_start_gmac():MAC desc init timeout. Try Again.\n");
> +
> + return OGMA_ERR_AGAIN;
> + }
> +
> + /* set BMR */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_BMR,
> + OGMA_GMAC_BMR_REG_COMMON);
> + /* set RDLAR */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_RDLAR,
> + OGMA_GMAC_RDLAR_REG_COMMON);
> + /* set TDLAR*/
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_TDLAR,
> + OGMA_GMAC_TDLAR_REG_COMMON);
> + /* set MFFR*/
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_MFFR,
> + 0x80000001UL);
> +
> + /* calc MCR setting val */
> + value = ( ctrl_p->gmac_mode.half_duplex_flag ?
> + OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
> + OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
> +
> + if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
> + value |= OGMA_GMAC_MCR_REG_PS;
> + }
> +
> + if ( ( ctrl_p->param.gmac_config.phy_interface !=
> + OGMA_PHY_INTERFACE_GMII ) &&
> + ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
> + value |= OGMA_GMAC_MCR_REG_FES;
> + }
> + /* set CST bit */
> + value |= OGMA_GMAC_MCR_REG_CST;
> +
> + /* set JE bit */
> + value |= OGMA_GMAC_MCR_REG_JE;
> +
> + if ( ctrl_p->param.gmac_config.phy_interface ==
> + OGMA_PHY_INTERFACE_RGMII) {
> + /* set ignore in-band-status watch option. force tx clk out. */
> + value |= 0x40000000U;
> + }
> +
> + /* set MCR */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_MCR,
> + value);
> +
> + if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
> + /* Set Flow Control Threshold */
> + value =
> + ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
> + ctrl_p->gmac_mode.flow_ctrl_start_threshold;
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_FLOW_TH,
> + value);
> + /* Set Flow Control Threshold F_GMAC4MT*/
> + value =
> + ( ctrl_p->gmac_mode.pause_time << 16) |
> + OGMA_GMAC_FCR_REG_RFE |
> + OGMA_GMAC_FCR_REG_TFE;
> +
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_FCR,
> + value);
> + }
> +
> + }
> +
> + if ( ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) ||
> + ( tx_flag && (! ctrl_p->gmac_tx_running_flag) )
> + ) {
> + /* Read F_GMAC4MT OMR*/
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_OMR);
> +
> + if ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) {
> + value |= OGMA_GMAC_OMR_REG_SR;
> + ctrl_p->gmac_rx_running_flag = OGMA_TRUE;
> + }
> +
> + if ( tx_flag && (! ctrl_p->gmac_tx_running_flag) ) {
> + value |= OGMA_GMAC_OMR_REG_ST;
> + ctrl_p->gmac_tx_running_flag = OGMA_TRUE;
> + }
> +
> + /* set OMR*/
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_OMR,
> + value);
> +
> + }
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_stop_gmac (
> + ogma_handle_t ogma_handle,
> + ogma_bool rx_flag,
> + ogma_bool tx_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> +
> + if ( ( !rx_flag) && ( !tx_flag) ) {
> + return OGMA_ERR_OK;
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "%s call.\n", __func__);
> +
> + if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) ||
> + ( tx_flag && ctrl_p->gmac_tx_running_flag) ) {
> + /* Read F_GMAC4MT OMR*/
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_OMR);
> +
> + if ( rx_flag && ctrl_p->gmac_rx_running_flag) {
> + value &= (~OGMA_GMAC_OMR_REG_SR);
> + ctrl_p->gmac_rx_running_flag = OGMA_FALSE;
> + }
> +
> + if ( tx_flag && ctrl_p->gmac_tx_running_flag) {
> + value &= (~OGMA_GMAC_OMR_REG_ST);
> + ctrl_p->gmac_tx_running_flag = OGMA_FALSE;
> + }
> +
> + /* set F_GMAC4MT OMR*/
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_OMR,
> + value);
> + }
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> + ogma_dump_gmac_stat (ctrl_p);
> +#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_set_gmac_mode (
> + ogma_handle_t ogma_handle,
> + const ogma_gmac_mode_t *gmac_mode_p
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( gmac_mode_p == NULL) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + if ( ( ctrl_p->gmac_rx_running_flag) ||
> + ( ctrl_p->gmac_tx_running_flag) ) {
> + return OGMA_ERR_BUSY;
> + }
> +
> + if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G ) &&
> + ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
> + ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
> + ( gmac_mode_p->half_duplex_flag) ) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( gmac_mode_p->half_duplex_flag &&
> + gmac_mode_p->flow_ctrl_enable_flag) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( gmac_mode_p->flow_ctrl_enable_flag) {
> +
> + if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
> + ( gmac_mode_p->flow_ctrl_start_threshold >
> + OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
> + gmac_mode_p->flow_ctrl_start_threshold) ||
> + ( gmac_mode_p->flow_ctrl_stop_threshold >
> + OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
> + return OGMA_ERR_DATA;
> + }
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "%s call.\n", __func__);
> +
> + pfdep_memcpy( ( void *)&ctrl_p->gmac_mode,
> + ( void *)gmac_mode_p,
> + sizeof( ogma_gmac_mode_t) );
> +
> + ctrl_p->gmac_mode_valid_flag = OGMA_TRUE;
> +
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +static void ogma_set_phy_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr,
> + ogma_uint16 value
> + )
> +{
> +
> + ogma_uint32 cmd;
> +
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_GDR,
> + value);
> +
> + cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
> + ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
> + ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
> + OGMA_GMAC_GAR_REG_GW |
> + OGMA_GMAC_GAR_REG_GB);
> +
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_GAR,
> + cmd);
> +
> + while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
> + OGMA_GMAC_GAR_REG_GB)
> + != 0) {
> + ;
> + }
> +}
> +
> +void ogma_set_phy_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr,
> + ogma_uint16 value
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if (( ctrl_p == NULL)
> + || ( !ctrl_p->param.use_gmac_flag)
> + || ( phy_addr >= 32)
> + || ( reg_addr >= 32) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_set_phy_reg.\nPlease set valid argument.\n");
> + return;
> + }
> +
> + ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value);
> +
> +}
> +
> +static ogma_uint16 ogma_get_phy_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr
> + )
> +{
> +
> + ogma_uint32 cmd;
> +
> + cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
> + ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
> + ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
> + OGMA_GMAC_GAR_REG_GB);
> +
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_GAR,
> + cmd);
> +
> + while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
> + OGMA_GMAC_GAR_REG_GB)
> + != 0) {
> + ;
> + }
> + return (ogma_uint16)ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GDR);
> +
> +}
> +
> +ogma_uint16 ogma_get_phy_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 reg_addr
> + )
> +{
> + ogma_uint16 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL)
> + || ( !ctrl_p->param.use_gmac_flag)
> + || ( phy_addr >= 32)
> + || ( reg_addr >= 32) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_phy_reg.\nPlease set valid argument.\n");
> + return 0;
> + }
> +
> + value = ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr);
> +
> +
> + return value;
> +}
> +
> +#if ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) )
> +static const struct {
> + ogma_uint32 addr;
> + ogma_char *name_p;
> +} ogma_gmac_mmc_reg_info[] = {
> + {OGMA_GMAC_REG_ADDR_MMC_INTR_RX , "MMC_INTR_RX"},
> + {OGMA_GMAC_REG_ADDR_MMC_INTR_TX , "MMC_INTR_TX"},
> + {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX , "MMC_INTR_MASK_RX"},
> + {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX , "MMC_INTR_MASK_TX"},
> + {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB , "TXOCTETCOUNT_GB"},
> + {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB , "TXFRAMECOUNT_GB"},
> + {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB , "TX64OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB , "TX65TO127OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB , "TXUNICASTFRAMES_GB"},
> + {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
> + {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
> + {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR , "TXUNDERFLOWERROR"},
> + {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G , "TXSINGLECOL_G"},
> + {OGMA_GMAC_REG_ADDR_TXMULTICOL_G , "TXMULTICOL_G"},
> + {OGMA_GMAC_REG_ADDR_TXDEFERRED , "TXDEFERRED"},
> + {OGMA_GMAC_REG_ADDR_TXLATECOL , "TXLATECOL"},
> + {OGMA_GMAC_REG_ADDR_TXEXESSCOL , "TXEXESSCOL"},
> + {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR , "TXCARRIERERRROR"},
> + {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G , "TXOCTETCOUNT_G"},
> + {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G , "TXFRAMECOUNT_G"},
> + {OGMA_GMAC_REG_ADDR_TXEXECESSDEF , "TXEXECESSDEF"},
> + {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES , "TXPAUSEFRAMES"},
> + {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G , "TXVLANFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB , "RXFRAMECOUNT_GB"},
> + {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB , "RXOCTETCOUNT_GB"},
> + {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G , "RXOCTETCOUNT_G"},
> + {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_RXCRCERROR , "RXCRCERROR"},
> + {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR , "RXALLIGNMENTERROR"},
> + {OGMA_GMAC_REG_ADDR_RXRUNTERROR , "RXRUNTERROR"},
> + {OGMA_GMAC_REG_ADDR_RXJABBERERROR , "RXJABBERERROR"},
> + {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G , "RXUNDERSIZE_G"},
> + {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G , "RXOVERSIZE_G"},
> + {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB , "RX64OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB , "RX65TO127OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
> + {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G , "RXUNICASTFRAMES_G"},
> + {OGMA_GMAC_REG_ADDR_RXLENGTHERROR , "RXLENGTHERROR"},
> + {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE , "RXOUTOFRANGETYPE"},
> + {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES , "RXPAUSEFRAMES"},
> + {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW , "RXFIFOOVERFLOW"},
> + {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB , "RXVLANFRAMES_GB"},
> + {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR , "RXWATCHDOGERROR"},
> + {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
> + {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX , "MMC_IPC_INTR_RX"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS , "RXIPV4_GD_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS , "RXIPV4_HDRERR_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS , "RXIPV4_NOPAY_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS , "RXIPV4_FRAG_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS , "RXIPV4_UDSBL_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS , "RXIPV6_GD_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS , "RXIPV6_HDRERR_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS , "RXIPV6_NOPAY_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS , "RXUDP_GD_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS , "RXUDP_ERR_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS , "RXTCP_GD_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS , "RXTCP_ERR_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS , "RXICMP_GD_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS , "RXICMP_ERR_FRMS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS , "RXIPV4_GD_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS , "RXIPV4_FRAG_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS , "RXIPV6_GD_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS , "RXUDP_GD_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS , "RXUDP_ERR_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS , "RXTCP_GD_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS , "RXTCP_ERR_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS , "RXICMP_GD_OCTETS"},
> + {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS , "RXICMP_ERR_OCTETS"}
> +};
> +#endif /* ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) ) */
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> +void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p)
> +{
> +
> + ogma_uint i;
> +
> + pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> + "Dumping GMAC statistics registers(MMC registers):\n");
> +
> + for (i = 0;
> + i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
> + i++) {
> + pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> + " %s => 0x%08x\n",
> + ogma_gmac_mmc_reg_info[i].name_p,
> + ( unsigned long)ogma_get_mac_reg(ctrl_p,
> + ogma_gmac_mmc_reg_info[i].addr));
> + }
> +
> +
> + /* Reset all counters. */
> + ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> +
> +
> +}
> +
> +#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +
> +ogma_err_t ogma_get_gmac_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool *valid_flag_p,
> + ogma_gmac_mode_t *gmac_mode_p,
> + ogma_bool *rx_running_flag_p,
> + ogma_bool *tx_running_flag_p
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( valid_flag_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ( ctrl_p == NULL) ||
> + ( gmac_mode_p == NULL) ||
> + ( rx_running_flag_p == NULL) ||
> + ( tx_running_flag_p == NULL) ) {
> + *valid_flag_p = OGMA_FALSE;
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + *valid_flag_p = OGMA_FALSE;
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> +
> + *valid_flag_p = ctrl_p->gmac_mode_valid_flag;
> +
> + *rx_running_flag_p = ctrl_p->gmac_rx_running_flag;
> + *tx_running_flag_p = ctrl_p->gmac_tx_running_flag;
> +
> + pfdep_memcpy( ( void *)gmac_mode_p,
> + ( const void *)&ctrl_p->gmac_mode,
> + sizeof( ogma_gmac_mode_t) );
> +
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +static void ogma_set_phy_target_mmd_reg_addr (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + )
> +{
> + ogma_uint32 cmd;
> +
> + /* set MMD ADDR */
> + cmd = ( ogma_uint32)dev_addr;
> +
> + /*set command to MMD access control register */
> + ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
> +
> + /* set MMD access address data register Write reg_addr */
> + ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr);
> +
> + /* write value to MMD ADDR */
> + cmd = ( (1U << 14) | dev_addr);
> +
> + /* set command to MMD access control register */
> + ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
> +}
> +
> +static void ogma_set_phy_mmd_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr,
> + ogma_uint16 value
> + )
> +{
> + /* set target mmd reg_addr */
> + ogma_set_phy_target_mmd_reg_addr( ctrl_p,
> + phy_addr,
> + dev_addr,
> + reg_addr);
> +
> + /* Write value to MMD access address data register */
> + ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, value);
> +
> +}
> +
> +static ogma_uint16 ogma_get_phy_mmd_reg_sub (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + )
> +{
> + /* set target mmd reg_addr */
> + ogma_set_phy_target_mmd_reg_addr( ctrl_p,
> + phy_addr,
> + dev_addr,
> + reg_addr);
> +
> + /* Read value for MMD access address data register */
> + return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD);
> +}
> +
> +ogma_err_t ogma_set_gmac_lpictrl_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* set value tp LSIPCR Register */
> + ogma_set_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_LPICSR, value);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_lpictrl_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( value_p == NULL) ){
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Read LSIPCR Register */
> + *value_p = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_LPICSR);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_set_gmac_lpitimer_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint16 ls_timer_ms,
> + ogma_uint16 tw_timer_ms
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ls_timer_ms > 1024U) {
> + return OGMA_ERR_RANGE;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* make LPICTR value*/
> + value = ( ( ( ogma_uint32)ls_timer_ms << OGMA_GMAC_LPITCR_REG_LIT) |
> + ( tw_timer_ms << OGMA_GMAC_LPITCR_REG_TWT) );
> +
> + /* Write timer value to LSIPCR Register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_LPITCR,
> + value);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_lpitimer_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint16 *ls_timer_ms_p,
> + ogma_uint16 *tw_timer_ms_p
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ls_timer_ms_p == NULL) ||
> + ( tw_timer_ms_p == NULL) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Read timer value for LSIPCR Register */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_LPITCR);
> +
> + /* make ls_timer_ms value*/
> + *ls_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_LIT) &
> + OGMA_GMAC_LPITCR_REG_MASK_LIT);
> +
> + /* make tw_timer_ms value*/
> + *tw_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_TWT) &
> + OGMA_GMAC_LPITCR_REG_MASK_TWT);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +void ogma_set_phy_mmd_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr,
> + ogma_uint16 value
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return;
> + }
> +
> + if ( ( phy_addr > 31U) ||
> + ( dev_addr > 31U) ) {
> + return;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return;
> + }
> +
> + ogma_set_phy_mmd_reg_sub ( ctrl_p,
> + phy_addr,
> + dev_addr,
> + reg_addr,
> + value);
> +
> +
> + return;
> +}
> +
> +ogma_uint16 ogma_get_phy_mmd_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_uint8 dev_addr,
> + ogma_uint16 reg_addr
> + )
> +{
> + ogma_uint16 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return 0;
> + }
> +
> + if ( ( phy_addr > 31U) ||
> + ( dev_addr > 31U) ) {
> + return 0;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return 0;
> + }
> +
> + value = ogma_get_phy_mmd_reg_sub ( ctrl_p,
> + phy_addr,
> + dev_addr,
> + reg_addr);
> +
> +
> + return value;
> +}
> +
> +ogma_err_t ogma_get_phy_link_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint8 phy_addr,
> + ogma_phy_link_status_t *phy_link_status_p
> + )
> +{
> + ogma_uint32 value, tmp, exp;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( phy_link_status_p == NULL) ){
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( phy_addr >= 32) {
> + return OGMA_ERR_RANGE;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) );
> +
> + /* Read PHY CONTROL Register */
> + tmp = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONTROL);
> +
> + /* Read PHY STATUS Register */
> + value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
> +
> + /* check latched_link_down_flag */
> + if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) == 0) {
> + phy_link_status_p->latched_link_down_flag = OGMA_TRUE;
> +
> + /* Read PHY STATUS Register */
> + value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
> +
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "CONTROL Register value %08x\n", tmp);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "PHY STATUS register value %08x\n", value);
> +
> + /* Check Current Link Status */
> + if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) != 0 ) {
> + phy_link_status_p->up_flag = OGMA_TRUE;
> + }
> +
> + /* check Auto-Negotiation Enable */
> + if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE) ) != 0) &&
> + ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY) ) != 0) ) {
> + phy_link_status_p->auto_nego_enable_flag = OGMA_TRUE;
> + }
> +
> + /* Check Current Autonegotiation Complete Status */
> + if ( phy_link_status_p->up_flag &&
> + phy_link_status_p->auto_nego_enable_flag &&
> + ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP) ) != 0) ) {
> + phy_link_status_p->auto_nego_complete_flag = OGMA_TRUE;
> + }
> +
> + /* start Check Current Link Speed */
> + if ( phy_link_status_p->up_flag) {
> +
> + if ( phy_link_status_p->auto_nego_enable_flag == OGMA_FALSE) {
> +
> + /* Speed check */
> + if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) == 0) &&
> + ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) != 0) ) {
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> + } else if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) != 0) &&
> + ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) == 0) ) {
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> + } else {
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> + }
> +
> + /* Duplex check */
> + if ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_DUPLEX_MODE) ) == 0) {
> +
> + phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> + }
> +
> + } else if ( phy_link_status_p->auto_nego_complete_flag == OGMA_TRUE) {
> + /* case auto_nego_enable_flag TRUE && auto_nego_complete_flag TRUE */
> +
> + /* Read MASTER-SLAVE Control Register */
> + value = ogma_get_phy_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL);
> +
> + /* Read MASTER-SLAVE Status Register */
> + tmp = ogma_get_phy_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS);
> +
> + /* Check Current Link Speed */
> + if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_FULL) ) != 0) &&
> + ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_FULL) ) != 0) ) {
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> + } else if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_HALF) ) != 0) &&
> + ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_HALF) ) != 0) ) {
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> + phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +
> + } else {
> +
> + /* Read Auto-Negotiation Advertisement register */
> + value = ogma_get_phy_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY);
> +
> + /* Read Auto-Negotiation Link Partner Base Page Ability register */
> + tmp = ogma_get_phy_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY);
> +
> + value = ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) &
> + OGMA_PHY_ANA_REG_TAF_MASK);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "TAF value %08x\n", value);
> +
> + if ( value & OGMA_PHY_TAF_REG_100BASE_FULL) { /* 100M full */
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> + } else if ( value & OGMA_PHY_TAF_REG_100BASE_HALF) { /* 100M half */
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> + phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +
> + } else if ( value & OGMA_PHY_TAF_REG_10BASE_FULL) { /* 10M full */
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> +
> + } else { /* value = OGMA_PHY_TAF_REG_10BASE_HALF 10M Half */
> +
> + phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> +
> + phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> + }
> +
> + }
> + }
> + } /* End Check Current Link Speed */
> +
> + /* Check LPI Capable */
> + if ( phy_link_status_p->up_flag &&
> + phy_link_status_p->auto_nego_complete_flag &&
> + phy_link_status_p->link_speed != OGMA_PHY_LINK_SPEED_10M &&
> + phy_link_status_p->half_duplex_flag == OGMA_FALSE &&
> + ctrl_p->param.gmac_config.phy_interface != OGMA_PHY_INTERFACE_RMII) {
> +
> + /* Read EEE advertisement register */
> + value = ogma_get_phy_mmd_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_DEV_ADDR_AUTO_NEGO,
> + OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE);
> +
> + /* Read EEE link partner ability register */
> + tmp = ogma_get_phy_mmd_reg_sub( ctrl_p,
> + phy_addr,
> + OGMA_PHY_DEV_ADDR_AUTO_NEGO,
> + OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY);
> +
> + exp = ( ( phy_link_status_p->link_speed == OGMA_PHY_LINK_SPEED_1G) ?
> + OGMA_PHY_AUTO_NEGO_1000BASE_EEE:
> + OGMA_PHY_AUTO_NEGO_100BASE_EEE);
> +
> + /* Check EEE Advertise and EEE LP Ability */
> + if ( ( value & tmp & exp) != 0 ) {
> + phy_link_status_p->lpi_capable_flag = OGMA_TRUE;
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "EEE advertisement register value %08x\n",
> + value);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "EEE link partner ability register value %08x\n",
> + tmp);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "EEE LPI EXP value %08x\n",
> + exp);
> + }
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->latched_link_down_flag %u\n",
> + phy_link_status_p->latched_link_down_flag);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->up_flag %u\n",
> + phy_link_status_p->up_flag);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->auto_nego_enable_flag %u\n",
> + phy_link_status_p->auto_nego_enable_flag);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->auto_nego_complete_flag %u\n",
> + phy_link_status_p->auto_nego_complete_flag);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->link_speed %u\n",
> + phy_link_status_p->link_speed);
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> + "phy_link_status_p->lpi_capable_flag %u\n",
> + phy_link_status_p->lpi_capable_flag);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return gmac_int_sbd_regs;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return gmac_int_sbd_regs;
> + }
> +
> + /* Read IER register */
> + gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER);
> + /* Read IMR register */
> + gmac_int_sbd_regs.extended = ( ( ~( ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR) ) ) &
> + OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
> +
> +
> +
> + return gmac_int_sbd_regs;
> +}
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status_non_clear (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + )
> +{
> + ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return gmac_int_sbd_regs;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return gmac_int_sbd_regs;
> + }
> +
> + /* Read SR register */
> + gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_SR);
> +
> + /* Read ISR register */
> + gmac_int_sbd_regs.extended = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_ISR);
> +
> + if ( mask_flag) {
> +
> + /* Read IER register */
> + gmac_int_sbd_regs.base &= ( ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER) |
> + ( ~OGMA_GMAC_INT_SBD_IRQ_IER_ALL) );
> + /* Read IMR register */
> + gmac_int_sbd_regs.extended &= ( ( ~( ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR) ) ) &
> + OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
> + }
> +
> +
> + return gmac_int_sbd_regs;
> +}
> +
> +ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Write Clear SR register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_SR,
> + ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL) );
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_enable_gmac_int_sbd_irq (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Read IER register for No Change Value Keep */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER);
> + /* Write IER register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER,
> + ( value | ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_IER_ALL) ) );
> +
> + /* Read IMR register for No Change Value Keep */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR);
> + /* Write IMR register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR,
> + ( value & ( ~( int_sbd_regs.extended &
> + OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) ) );
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_disable_gmac_int_sbd_irq (
> + ogma_handle_t ogma_handle,
> + ogma_gmac_int_sbd_regs_t int_sbd_regs
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Read IER register for No Change Value Keep */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER);
> + /* Write IER register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IER,
> + ( value & ( ~(int_sbd_regs.base) ) ) );
> +
> + /* Read IMR register for No Change Value Keep */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR);
> + /* Write IMR register */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_IMR,
> + ( value | ( int_sbd_regs.extended &
> + OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) );
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_rgmii_status_reg (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( value_p == NULL) ){
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->param.use_gmac_flag) {
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Read RGMII Status Register */
> + *value_p = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_RSR);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
> +ogma_err_t ogma_read_gmac_stat (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 *value_p,
> + ogma_bool reset_flag
> + )
> +{
> +
> + ogma_uint i;
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( value_p == NULL) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> +
> + for ( i = 0;
> + i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0] );
> + i++) {
> +
> + value_p[i] = ogma_get_mac_reg(ctrl_p,
> + ogma_gmac_mmc_reg_info[i].addr);
> + }
> +
> + if ( reset_flag) {
> + /* Reset all counters. */
> + ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> + }
> +
> +
> + return OGMA_ERR_OK;
> +}
> +#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
> +
> +ogma_err_t ogma_reset_gmac_stat (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> +
> + /* Reset all counters. */
> + ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_softreset_gmac (
> + ogma_ctrl_t *ctrl_p
> + )
> +{
> + ogma_uint32 value;
> + pfdep_err_t pfdep_err;
> +
> + /* F_GMAC4MT soft reset*/
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_BMR,
> + OGMA_GMAC_BMR_REG_RESET);
> + /* Wait soft reset */
> + pfdep_err = pfdep_msleep( 1);
> +
> + if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "Wait for BMR soft reset error.\n");
> +
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + /* Read F_GMAC4MT BMR */
> + value = ogma_get_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_BMR);
> +
> + /* check software reset result*/
> + if ( value & OGMA_GMAC_BMR_REG_SWR) {
> + return OGMA_ERR_AGAIN;
> + }
> +
> + return OGMA_ERR_OK;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
> new file mode 100644
> index 000000000000..e2e25c71abaa
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
> @@ -0,0 +1,210 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_INTERNAL_H
> +#define OGMA_INTERNAL_H
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +#include "ogma_reg.h"
> +#include "pfdep.h"
> +
> +/* Just a million to prevent typing errors. */
> +#define OGMA_CLK_MHZ (1000000)
> +
> +#define OGMA_INSTANCE_NUM_MAX 1
> +
> +#define OGMA_RX_PKT_BUF_LEN 1522
> +#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
> +#define OGMA_DUMMY_DESC_ENTRY_LEN 48
> +
> +#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
> +
> +extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
> +
> +typedef struct ogma_ctrl_s ogma_ctrl_t;
> +typedef struct ogma_desc_ring_s ogma_desc_ring_t;
> +typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
> +typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
> +
> +struct ogma_clk_ctrl_s{
> + ogma_uint8 mac_req_num;
> +};
> +
> +
> +struct ogma_desc_ring_s{
> +
> + ogma_desc_ring_id_t ring_id;
> +
> + ogma_desc_ring_param_t param;
> +
> + ogma_uint rx_desc_ring_flag:1;
> +
> + ogma_uint tx_desc_ring_flag:1;
> +
> + ogma_uint running_flag:1;
> +
> + ogma_uint full_flag:1;
> +
> + ogma_uint8 desc_entry_len;
> +
> + ogma_uint16 head_idx;
> +
> + ogma_uint16 tail_idx;
> +
> + ogma_uint16 rx_num;
> +
> + ogma_uint16 tx_done_num;
> +
> + pfdep_hard_lock_t inten_reg_hard_lock;
> +
> + pfdep_soft_lock_t soft_lock;
> +
> + void *desc_ring_cpu_addr;
> +
> + pfdep_phys_addr_t desc_ring_phys_addr;
> +
> + ogma_frag_info_t *frag_info_p;
> +
> + ogma_desc_entry_priv_t *priv_data_p;
> +};
> +
> +struct ogma_ctrl_s{
> + ogma_ctrl_t *next_p;
> +
> + ogma_uint core_enabled_flag:1;
> +
> + ogma_uint gmac_rx_running_flag:1;
> +
> + ogma_uint gmac_tx_running_flag:1;
> +
> + ogma_uint gmac_mode_valid_flag:1;
> +
> + ogma_uint normal_desc_ring_valid:1;
> +
> + void *base_addr;
> +
> + pfdep_dev_handle_t dev_handle;
> +
> + ogma_param_t param;
> +
> + ogma_clk_ctrl_t clk_ctrl;
> +
> + ogma_uint32 rx_pkt_buf_len;
> +
> + ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
> +
> + ogma_gmac_mode_t gmac_mode;
> +
> + pfdep_hard_lock_t inten_reg_hard_lock;
> +
> + pfdep_hard_lock_t clk_ctrl_hard_lock;
> +
> + void *dummy_desc_entry_addr;
> +
> + pfdep_phys_addr_t dummy_desc_entry_phys_addr;
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> + /**
> + * Statistics information.
> + *
> + * Note: Since mutual access exclusion is omitted,
> + * these values might be inaccurate.
> + */
> + ogma_stat_info_t stat_info;
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +};
> +
> +union ogma_desc_entry_priv_u{
> + pfdep_pkt_handle_t pkt_handle;
> +};
> +
> +/*****************************************************************
> + *****************************************************************
> + *****************************************************************/
> +
> +/**
> + *
> + */
> +ogma_err_t ogma_alloc_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_id_t ring_idx
> + );
> +/**
> + *
> + */
> +void ogma_free_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +/**
> + *
> + */
> +ogma_err_t ogma_setup_rx_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +/**
> + *
> + */
> +void ogma_uninit_pkt_desc_ring (
> + ogma_ctrl_t *ctrl_p,
> + ogma_desc_ring_t *desc_ring_p
> + );
> +
> +/**
> + *
> + */
> +void ogma_push_clk_req (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 domain
> + );
> +
> +void ogma_pop_clk_req(
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 domain
> + );
> +
> +
> +ogma_err_t ogma_softreset_gmac (
> + ogma_ctrl_t *ctrl_p
> + );
> +
> +#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
> +#include "ogma_basic_access.h"
> +/*include for ogma_read_reg*/
> +static __inline void ogma_check_clk_supply (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 domain
> + )
> +{
> + ogma_uint32 value;
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
> +
> + pfdep_assert( ( ( value & domain ) == domain) );
> +}
> +
> +#else
> +
> +#define ogma_check_clk_supply( ctrl_p, domain)
> +
> +#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
> +
> +#endif /* OGMA_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> new file mode 100644
> index 000000000000..3c54c63126a7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> @@ -0,0 +1,1385 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_config.h"
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +#include "ogma_misc_internal.h"
> +
> +#include <Library/IoLib.h>
> +
> +ogma_global_t ogma_global = {
> + OGMA_FALSE,
> + 0,
> + NULL
> +};
> +
> +
> +static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
> +static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
> +
> +static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> + OGMA_REG_ADDR_NRM_TX_STATUS,
> + OGMA_REG_ADDR_NRM_RX_STATUS,
> +};
> +
> +static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> + OGMA_REG_ADDR_NRM_TX_CONFIG,
> + OGMA_REG_ADDR_NRM_RX_CONFIG,
> +
> +};
> +
> +
> +/* Internal function definition*/
> +#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
> +STATIC void ogma_set_clk_en_reg (
> + ogma_ctrl_t *ctrl_p
> + );
> +#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +STATIC void ogma_global_init ( void);
> +
> +STATIC ogma_err_t ogma_probe_hardware (
> + void *base_addr
> + );
> +
> +STATIC void ogma_reset_hardware (
> + ogma_ctrl_t *ctrl_p
> + );
> +
> +STATIC void ogma_set_microcode(
> + ogma_ctrl_t *ctrl_p,
> + const void *dma_hm_mc_addr,
> + ogma_uint32 dma_hm_mc_len,
> + const void *dma_mh_mc_addr,
> + ogma_uint32 dma_mh_mc_len,
> + const void *pktc_mc_addr,
> + ogma_uint32 pktc_mc_len
> + );
> +
> +STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
> + const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
> + );
> +
> +STATIC void ogma_internal_terminate (
> + ogma_ctrl_t *ctrl_p
> + );
> +
> +#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
> +
> +#define ogma_set_clk_en_reg( ctrl_p)
> +
> +#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +STATIC void ogma_set_clk_en_reg (
> + ogma_ctrl_t *ctrl_p
> + )
> +{
> + ogma_uint32 value = 0;
> +
> + if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
> + value |= OGMA_CLK_EN_REG_DOM_G;
> + }
> +
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
> +}
> +#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +
> +void ogma_push_clk_req (
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 domain
> + )
> +{
> + pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
> +
> + pfdep_acquire_hard_lock (
> + &ctrl_p->clk_ctrl_hard_lock,
> + &clk_ctrl_hard_lock_ctx);
> +
> + if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
> + ++ctrl_p->clk_ctrl.mac_req_num;
> + }
> +
> + ogma_set_clk_en_reg( ctrl_p);
> +
> + pfdep_release_hard_lock(
> + &ctrl_p->clk_ctrl_hard_lock,
> + &clk_ctrl_hard_lock_ctx);
> +}
> +
> +void ogma_pop_clk_req(
> + ogma_ctrl_t *ctrl_p,
> + ogma_uint32 domain
> + )
> +{
> + pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
> +
> + pfdep_acquire_hard_lock(
> + &ctrl_p->clk_ctrl_hard_lock,
> + &clk_ctrl_hard_lock_ctx);
> +
> + if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
> + --ctrl_p->clk_ctrl.mac_req_num;
> + }
> +
> + ogma_set_clk_en_reg( ctrl_p);
> +
> + pfdep_release_hard_lock(
> + &ctrl_p->clk_ctrl_hard_lock,
> + &clk_ctrl_hard_lock_ctx);
> +}
> +
> +/* Internal function */
> +STATIC void ogma_global_init ( void)
> +{
> + ogma_global.valid_flag = OGMA_TRUE;
> +}
> +
> +STATIC ogma_err_t ogma_probe_hardware (
> + void *base_addr
> + )
> +{
> +
> + ogma_uint32 value;
> +
> + /* Read HW_VER Register */
> + value = pfdep_iomem_read((void *)
> + ((pfdep_cpu_addr_t)base_addr +
> + (OGMA_REG_ADDR_HW_VER << 2)));
> +
> + if ( value != OGMA_VER_NETSEC) {
> + pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
> + "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
> + (unsigned int)value,
> + (unsigned int)OGMA_VER_NETSEC);
> + }
> +
> + if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
> + pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
> + "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
> + (unsigned int)OGMA_VER_MAJOR_NUM(value),
> + (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Print hardware version information. */
> + pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> + "NETSEC found. Hardware version: %08x\n",
> + value);
> +
> +
> + return OGMA_ERR_OK;
> +}
> +
> +STATIC void ogma_reset_hardware (
> + ogma_ctrl_t *ctrl_p
> + )
> +{
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_CLK_EN,
> + OGMA_CLK_EN_REG_DOM_ALL);
> +
> +
> + /*
> + * Stop dma engines if cores are enabled
> + */
> + if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_DMA_HM_CTRL,
> + OGMA_DMA_CTRL_REG_STOP);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_DMA_MH_CTRL,
> + OGMA_DMA_CTRL_REG_STOP);
> +
> + while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
> + & OGMA_DMA_CTRL_REG_STOP) != 0) {
> + ;
> + }
> +
> + while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
> + & OGMA_DMA_CTRL_REG_STOP) != 0) {
> + ;
> + }
> + }
> +
> + if ( ctrl_p->param.use_gmac_flag) {
> +
> + /* Reset F_GMAC4MT */
> + ogma_set_mac_reg( ctrl_p,
> + OGMA_GMAC_REG_ADDR_BMR,
> + OGMA_GMAC_BMR_REG_RESET);
> +
> + }
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_SOFT_RST,
> + OGMA_SOFT_RST_REG_RESET);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_SOFT_RST,
> + OGMA_SOFT_RST_REG_RUN);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_COM_INIT,
> + OGMA_COM_INIT_REG_ALL);
> +
> + while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
> + ;
> + }
> +
> + if ( ctrl_p->param.use_gmac_flag) {
> +
> +
> + /* MAC desc init */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_DESC_INIT,
> + OGMA_MAC_DESC_INIT_REG_INIT);
> +
> + /* Wait MAC desc init done */
> + while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
> + & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
> + ;
> + }
> +
> +
> + /* set MAC_INTF_SEL */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_INTF_SEL,
> + ctrl_p->param.gmac_config.phy_interface);
> +
> +
> + }
> +}
> +
> +#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
> +
> +STATIC void ogma_set_microcode (
> + ogma_ctrl_t *ctrl_p,
> + const void *dma_hm_mc_addr,
> + ogma_uint32 dma_hm_mc_len,
> + const void *dma_mh_mc_addr,
> + ogma_uint32 dma_mh_mc_len,
> + const void *pktc_mc_addr,
> + ogma_uint32 pktc_mc_len
> + )
> +{
> + ogma_uint i;
> +
> + const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
> + const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
> + const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
> +
> + /* Loads microcodes to microengines. */
> + for( i = 0; i < dma_hm_mc_len; i++) {
> + UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
> + data );
> + dmac_hm_cmd_data++;
> + }
> +
> + for( i = 0; i < dma_mh_mc_len; i++) {
> + UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
> + data );
> + dmac_mh_cmd_data++;
> + }
> +
> + for( i = 0; i < pktc_mc_len; i++) {
> + UINT32 data = MmioRead32((UINTN)core_cmd_data);
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKTC_CMD_BUF,
> + data );
> + core_cmd_data++;
> + }
> +
> +}
> +
> +STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
> + const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
> + )
> +{
> + ogma_uint32 param = 0;
> +
> + if ( pkt_ctrl_param_p->log_chksum_er_flag) {
> + param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
> + }
> +
> + if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
> + param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
> + }
> +
> + if ( pkt_ctrl_param_p->log_hd_er_flag) {
> + param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
> + }
> +
> + if ( pkt_ctrl_param_p->drp_no_match_flag) {
> + param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
> + }
> +
> + return param;
> +}
> +
> +ogma_err_t ogma_init (
> + void *base_addr,
> + pfdep_dev_handle_t dev_handle,
> + const ogma_param_t *param_p,
> + const void *dma_hm_mc_addr,
> + ogma_uint32 dma_hm_mc_len,
> + const void *dma_mh_mc_addr,
> + ogma_uint32 dma_mh_mc_len,
> + const void *pktc_mc_addr,
> + ogma_uint32 pktc_mc_len,
> + ogma_handle_t *ogma_handle_p
> + )
> +{
> + ogma_int i;
> + ogma_uint32 domain = 0, value;
> + ogma_err_t ogma_err;
> + ogma_ctrl_t *ctrl_p = NULL;
> +
> + ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
> + ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
> +
> + ogma_bool all_lock_init_done_flag = OGMA_FALSE;
> +
> + pfdep_err_t pfdep_err;
> +
> + if ( ( param_p == NULL) ||
> + ( ogma_handle_p == NULL) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
> + return OGMA_ERR_INVALID;
> + }
> +
> + if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
> + (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Please set invalid packet desc_ring_param valid_flag.\n");
> + return OGMA_ERR_DATA;
> + }
> +
> + if ( param_p->use_gmac_flag) {
> + if ( ( param_p->gmac_config.phy_interface !=
> + OGMA_PHY_INTERFACE_GMII) &&
> + ( param_p->gmac_config.phy_interface !=
> + OGMA_PHY_INTERFACE_RGMII) &&
> + ( param_p->gmac_config.phy_interface !=
> + OGMA_PHY_INTERFACE_RMII) ) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Please set phy_interface to valid value.\n");
> + return OGMA_ERR_DATA;
> + }
> + } else {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Please set use_gmac_flag OGMA_TRUE.\n");
> + return OGMA_ERR_DATA;
> + }
> +
> + ogma_err = ogma_probe_hardware( base_addr);
> +
> + if ( ogma_err != OGMA_ERR_OK) {
> + return ogma_err;
> + }
> +
> + if ( !ogma_global.valid_flag) {
> + ogma_global_init();
> + }
> +
> + if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to ogma_handle memory allocation.\n");
> + return OGMA_ERR_ALLOC;
> + }
> +
> + pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
> +
> + ctrl_p->base_addr = base_addr;
> +
> + ctrl_p->dev_handle = dev_handle;
> +
> + pfdep_memcpy( ( void *)&ctrl_p->param,
> + ( void *)param_p,
> + sizeof( ogma_param_t) );
> +
> + /* Initialize hardware lock */
> + pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
> + if ( pfdep_err != PFDEP_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to inten_reg_hard_lock's initialization.\n");
> + ogma_err = OGMA_ERR_ALLOC;
> + goto err;
> + }
> + inten_reg_hard_lock_init_flag = OGMA_TRUE;
> +
> + pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
> + if ( pfdep_err != PFDEP_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to clk_ctrl_hard_lock's initialization.\n");
> + ogma_err = OGMA_ERR_ALLOC;
> + goto err;
> + }
> + clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
> +
> + all_lock_init_done_flag = OGMA_TRUE;
> +
> + pfdep_err = pfdep_dma_malloc( dev_handle,
> + OGMA_DUMMY_DESC_ENTRY_LEN,
> + &ctrl_p->dummy_desc_entry_addr,
> + &ctrl_p->dummy_desc_entry_phys_addr);
> +
> + if ( pfdep_err != PFDEP_ERR_OK) {
> + ogma_err = OGMA_ERR_ALLOC;
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to dummy_desc_entry's memory allocation.\n");
> + goto err;
> + }
> +
> + /* clear dummy desc entry */
> + pfdep_memset( ctrl_p->dummy_desc_entry_addr,
> + 0,
> + OGMA_DUMMY_DESC_ENTRY_LEN);
> +
> + ogma_reset_hardware( ctrl_p);
> +
> + if ( param_p->use_gmac_flag) {
> + domain |= OGMA_CLK_EN_REG_DOM_G;
> + }
> +
> + ogma_push_clk_req( ctrl_p, domain);
> +
> + /* set PKT_CTRL */
> + value = ogma_calc_pkt_ctrl_reg_param( ¶m_p->pkt_ctrl_param);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_CTRL,
> + value);
> +
> + if ( param_p->use_jumbo_pkt_flag) {
> +
> + ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
> +
> + value = ogma_read_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_CTRL);
> +
> + value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_CTRL,
> + value);
> + } else {
> +
> + ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
> +
> + }
> +
> + /* set pkt desc ring config */
> + for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> + if ( ctrl_p->param.desc_ring_param[i].valid_flag) {
> + value =
> + ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
> + OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
> + ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
> + OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
> +
> + ogma_write_reg( ctrl_p,
> + desc_ring_config_reg_addr[i],
> + value);
> +
> + }
> + }
> +
> + /* set microengines */
> + ogma_set_microcode(ctrl_p,
> + dma_hm_mc_addr,
> + dma_hm_mc_len,
> + dma_mh_mc_addr,
> + dma_mh_mc_len,
> + pktc_mc_addr,
> + pktc_mc_len);
> +
> + /* alloc desc_ring*/
> + for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> + ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
> + if ( ogma_err != OGMA_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to ring id NO.%d memory allocation.\n",
> + i);
> + goto err;
> + }
> + }
> +
> + if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
> + if ( ( ogma_err = ogma_setup_rx_desc_ring(
> + ctrl_p,
> + &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
> + != OGMA_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to NRM_RX packet memory allocation.\n");
> + goto err;
> + }
> + }
> +
> + /* microengines need domain G */
> + ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> + /* set DMA tmr ctrl*/
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
> + ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
> +
> + /* start microengines */
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
> +
> + if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to waiting for microcode initialize end.\n");
> + ogma_err = OGMA_ERR_INTERRUPT;
> + goto err;
> + }
> +
> + /* check microcode load end & start core */
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
> +
> + if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_init.\n"
> + "Failed to microcode loading.\n");
> + ogma_err = OGMA_ERR_INVALID;
> + goto err;
> + }
> +
> + /* clear microcode load end status */
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
> + OGMA_TOP_IRQ_REG_ME_START);
> +
> + ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> + ctrl_p->core_enabled_flag = OGMA_TRUE;
> +
> + ctrl_p->next_p = ogma_global.list_head_p;
> +
> + ogma_global.list_head_p = ctrl_p;
> +
> + ++ogma_global.list_entry_num;
> +
> + *ogma_handle_p = ctrl_p;
> +
> +#if 1
> + {
> +
> +#define OGMA_PKT_CTRL_REG_MODE_TAIKI (1UL << 28)
> +#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
> +#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL << 4)
> +#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
> +
> + /* Read Pkt ctrl register */
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
> + value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
> +
> + /* change to noromal mode */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_DMA_MH_CTRL,
> + OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_CTRL,
> + value);
> +
> + while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
> + OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
> + ;
> + }
> +
> + }
> +#endif
> +
> + /* Print microcode version information. */
> + pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> + "Microcode version: %08x\n",
> + ogma_read_reg( ctrl_p,
> + mc_ver_reg_addr) );
> +
> + return OGMA_ERR_OK;
> +
> +err:
> + if ( !all_lock_init_done_flag) {
> +
> +
> + if ( clk_ctrl_hard_lock_init_flag) {
> + pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
> + }
> +
> + if ( inten_reg_hard_lock_init_flag) {
> + pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
> + }
> +
> + } else {
> +
> + ogma_internal_terminate( ctrl_p);
> +
> + }
> +
> + pfdep_free( ctrl_p);
> +
> + return ogma_err;
> +}
> +
> +STATIC void ogma_internal_terminate (
> + ogma_ctrl_t *ctrl_p
> + )
> +{
> + ogma_int i;
> +
> + ogma_reset_hardware( ctrl_p);
> +
> + /* free desc_ring */
> + for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> + ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
> + }
> +
> + if ( ctrl_p->dummy_desc_entry_addr != NULL) {
> + pfdep_dma_free( ctrl_p->dev_handle,
> + OGMA_DUMMY_DESC_ENTRY_LEN,
> + ctrl_p->dummy_desc_entry_addr,
> + ctrl_p->dummy_desc_entry_phys_addr);
> + }
> +
> + pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
> +
> +
> + pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
> +
> +}
> +
> +void ogma_terminate (
> + ogma_handle_t ogma_handle
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
> + ogma_uint32 domain = 0;
> +
> + if ( ( ctrl_p == NULL) ||
> + ( ogma_global.list_entry_num == 0) ) {
> + return;
> + }
> +
> + pfdep_assert( ogma_global.list_head_p != NULL);
> +
> + if ( ctrl_p->param.use_gmac_flag) {
> + domain |= OGMA_CLK_EN_REG_DOM_G;
> + }
> +
> + /* pop domain clock */
> + ogma_pop_clk_req( ctrl_p, domain);
> +
> + tmp_ctrl_p = ogma_global.list_head_p;
> +
> + while(1) {
> + if ( tmp_ctrl_p == NULL) {
> + /* Could not found ctrl_p specified from the list */
> + return;
> + }
> + if ( ctrl_p == tmp_ctrl_p) {
> + if ( old_tmp_ctrl_p != NULL) {
> + old_tmp_ctrl_p->next_p = ctrl_p->next_p;
> + } else {
> + ogma_global.list_head_p = ctrl_p->next_p;
> + }
> + break;
> + }
> + old_tmp_ctrl_p = tmp_ctrl_p;
> + tmp_ctrl_p = tmp_ctrl_p->next_p;
> + }
> +
> + ogma_internal_terminate( ctrl_p);
> +
> + --ogma_global.list_entry_num;
> +
> + pfdep_free( ctrl_p);
> + return;
> +}
> +
> +ogma_err_t ogma_enable_top_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* set irq_factor*/
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_disable_top_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* clear irq_factor*/
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_enable_desc_ring_irq (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + ogma_desc_ring_t *desc_ring_p;
> +
> + pfdep_err_t pfdep_err;
> + pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_enable_desc_ring_irq.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_enable_desc_ring_irq.\n"
> + "Please select ring id number between 0 and %d.\n",
> + OGMA_DESC_RING_ID_MAX);
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_enable_desc_ring_irq.\n"
> + "Please select valid desc ring.\n");
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> + /* get soft lock */
> + pfdep_err = pfdep_acquire_soft_lock (
> + &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> +
> + if ( pfdep_err != PFDEP_ERR_OK) {
> + return OGMA_ERR_INTERRUPT;
> + }
> +
> + if ( !desc_ring_p->running_flag) {
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_enable_desc_ring_irq.\n"
> + "Please select running desc ring.\n");
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* set irq_factor*/
> + ogma_write_reg( ctrl_p,
> + desc_ring_irq_inten_set_reg_addr[ring_id],
> + irq_factor);
> +
> + /* free soft_lock*/
> + pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> + &soft_lock_ctx);
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_desc_ring_irq (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_disable_desc_ring_irq.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_disable_desc_ring_irq.\n"
> + "Please select ring id number between 0 and %d.\n",
> + OGMA_DESC_RING_ID_MAX);
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_disable_desc_ring_irq.\n"
> + "Please select valid desc ring.\n");
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Clear irq factor*/
> + ogma_write_reg( ctrl_p,
> + desc_ring_irq_inten_clr_reg_addr[ring_id],
> + irq_factor);
> +
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_enable_pkt_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* set irq_factor*/
> + ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
> + ( irq_factor & OGMA_PKT_IRQ_ALL) );
> +
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_pkt_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* clear irq_factor*/
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_INTEN_CLR,
> + ( irq_factor & OGMA_PKT_IRQ_ALL) );
> +
> + return ogma_err;
> +}
> +
> +
> +ogma_uint32 ogma_get_top_irq_enable (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_top_irq_enable.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
> +
> + return value;
> +
> +}
> +
> +
> +ogma_uint32 ogma_get_top_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_top_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
> +
> + if ( mask_flag) {
> + value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
> + }
> +
> + return value;
> +}
> +
> +ogma_err_t ogma_clear_top_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_top_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* Write clear irq top status */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_TOP_STATUS,
> +
> + ( value & OGMA_TOP_IRQ_REG_ME_START) );
> +
> + return OGMA_ERR_OK;
> +}
> +
> +ogma_uint32 ogma_get_desc_ring_irq_enable (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> + "Please select ring id number between 0 and %d.\n",
> + OGMA_DESC_RING_ID_MAX);
> + return 0;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> + "Please select valid desc ring.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p,
> + desc_ring_irq_inten_reg_addr[ring_id] );
> +
> + return value;
> +}
> +
> +
> +ogma_uint32 ogma_get_desc_ring_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_bool mask_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_status.\n"
> + "Please select ring id number between 0 and %d.\n",
> + OGMA_DESC_RING_ID_MAX);
> + return 0;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_desc_ring_irq_status.\n"
> + "Please select valid desc ring.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p,
> + desc_ring_irq_status_reg_addr[ring_id] );
> +
> + if ( mask_flag) {
> + value &= ogma_read_reg( ctrl_p,
> + desc_ring_irq_inten_reg_addr[ring_id] );
> + }
> +
> + return value;
> +}
> +
> +
> +
> +ogma_err_t ogma_clear_desc_ring_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_desc_ring_id_t ring_id,
> + ogma_uint32 value
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> + "Please select ring id number between 0 and %d.\n",
> + OGMA_DESC_RING_ID_MAX);
> + return OGMA_ERR_PARAM;
> + }
> +
> + if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> + "Please select valid desc ring.\n");
> + return OGMA_ERR_NOTAVAIL;
> + }
> +
> + /* Write clear descring irq status */
> + ogma_write_reg( ctrl_p,
> + desc_ring_irq_status_reg_addr[ring_id],
> + ( value & ( OGMA_CH_IRQ_REG_EMPTY |
> + OGMA_CH_IRQ_REG_ERR) ) );
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +
> +ogma_uint32 ogma_get_pkt_irq_enable (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_pkt_irq_enable.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
> +
> + value &= OGMA_PKT_IRQ_ALL;
> +
> + return value;
> +
> +}
> +
> +ogma_uint32 ogma_get_pkt_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
> +
> + if ( mask_flag) {
> + value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
> + }
> +
> + return value;
> +}
> +
> +ogma_err_t ogma_clear_pkt_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_pkt_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* Write clear irq pkt status */
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_PKT_STATUS,
> + ( value & ( ( OGMA_PKT_IRQ_MAC_ER |
> + OGMA_PKT_IRQ_JUMBO_ER |
> + OGMA_PKT_IRQ_CHKSUM_ER |
> + OGMA_PKT_IRQ_HD_INCOMPLETE |
> + OGMA_PKT_IRQ_HD_ER |
> + OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
> +
> + return OGMA_ERR_OK;
> +}
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +ogma_err_t ogma_get_stat_info (
> + ogma_handle_t ogma_handle,
> + ogma_stat_info_t *stat_info_p,
> + ogma_bool clear_flag
> + )
> +{
> +
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
> + return OGMA_ERR_PARAM;
> + }
> +
> + pfdep_memcpy( stat_info_p,
> + &ctrl_p->stat_info,
> + sizeof( ogma_stat_info_t) );
> +
> +
> + if ( clear_flag) {
> + pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
> + }
> +
> + return OGMA_ERR_OK;
> +
> +}
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +ogma_uint32 ogma_get_hw_ver (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p,
> + hw_ver_reg_addr);
> +
> + return value;
> +}
> +
> +
> +ogma_uint32 ogma_get_mcr_ver (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p,
> + mc_ver_reg_addr);
> +
> + return value;
> +}
> +
> +ogma_uint32 ogma_get_mac_irq_enable (
> + ogma_handle_t ogma_handle
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
> +
> +
> + return value;
> +}
> +
> +ogma_uint32 ogma_get_mac_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_bool mask_flag
> + )
> +{
> + ogma_uint32 value;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_get_mac_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return 0;
> + }
> +
> +
> + value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
> +
> + if ( mask_flag) {
> + value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
> + }
> +
> +
> + return value;
> +}
> +
> +ogma_err_t ogma_clear_mac_irq_status (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 value
> + )
> +{
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_clear_mac_irq_status.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> +
> + /* Commented out because no write-clear bit exists now. */
> +#if 0
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_STATUS,
> + ( value & /* T.B.D. */) );
> +#endif
> +
> +
> + return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_enable_mac_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_uint32 value;
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> + pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_enable_mac_irq.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* get inten_reg_hard_lock */
> + pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
> + &inten_reg_hard_lock_ctx);
> +
> + value = ogma_read_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_INTEN);
> +
> + value |= irq_factor;
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_INTEN,
> + value);
> +
> +
> + /* free inten_reg_hard_lock*/
> + pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
> + &inten_reg_hard_lock_ctx);
> + return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_mac_irq (
> + ogma_handle_t ogma_handle,
> + ogma_uint32 irq_factor
> + )
> +{
> + ogma_uint32 value;
> + ogma_err_t ogma_err = OGMA_ERR_OK;
> + ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> + pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
> +
> +
> + if ( ctrl_p == NULL) {
> + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> + "An error occurred at ogma_disable_mac_irq.\n"
> + "Please set valid ogma_handle.\n");
> + return OGMA_ERR_PARAM;
> + }
> +
> + /* get inten_reg_hard_lock */
> + pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
> + &inten_reg_hard_lock_ctx);
> +
> + value = ogma_read_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_INTEN);
> +
> + value &= (~irq_factor);
> +
> + ogma_write_reg( ctrl_p,
> + OGMA_REG_ADDR_MAC_INTEN,
> + value);
> +
> +
> + /* free inten_reg_hard_lock*/
> + pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
> + &inten_reg_hard_lock_ctx);
> + return ogma_err;
> +
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
> new file mode 100644
> index 000000000000..3bbf8de57a8b
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
> @@ -0,0 +1,38 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_MISC_INTERNAL_H
> +#define OGMA_MISC_INTERNAL_H
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +
> +#define OGMA_CLK_EN_REG_DOM_ALL 0x24
> +
> +#define OGMA_PKT_IRQ_ALL ( OGMA_PKT_IRQ_MAC_ER | OGMA_PKT_IRQ_JUMBO_ER | \
> + OGMA_PKT_IRQ_CHKSUM_ER | OGMA_PKT_IRQ_HD_INCOMPLETE | \
> + OGMA_PKT_IRQ_HD_ER | OGMA_PKT_IRQ_DRP_NO_MATCH)
> +
> +typedef struct ogma_global_s ogma_global_t;
> +
> +struct ogma_global_s{
> + ogma_uint valid_flag:1;
> +
> + ogma_uint8 list_entry_num;
> +
> + ogma_ctrl_t *list_head_p;
> +};
> +
> +#endif /* OGMA_MISC_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
> new file mode 100644
> index 000000000000..910b37a25f14
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
> @@ -0,0 +1,219 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_H
> +#define OGMA_REG_H
> +
> +#include "ogma_reg_netsec.h"
> +#include "ogma_reg_f_gmac_4mt.h"
> +
> +/* aliases */
> +#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
> +#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
> +#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
> +/* aliases end here */
> +
> +/* need fixing */
> +#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF (0x87)
> +
> +
> +/*bit fields for PKT_CTRL*/
> +#define OGMA_PKT_CTRL_REG_EN_JUMBO (1UL << 27)
> +#define OGMA_PKT_CTRL_REG_EN_BITPATF (1UL << 4 )
> +#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER (1UL << 3 )
> +#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
> +#define OGMA_PKT_CTRL_REG_LOG_HD_ER (1UL << 1 )
> +#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH (1UL << 0 )
> +
> +#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
> +
> +/************************************************************
> + * Bit fields
> + ************************************************************/
> +/* bit fields for com_init */
> +#define OGMA_COM_INIT_REG_DB (1UL << 2)
> +#define OGMA_COM_INIT_REG_CLS (1UL << 1)
> +#define OGMA_COM_INIT_REG_ALL ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
> +
> +/* bit fields for soft_rst */
> +#define OGMA_SOFT_RST_REG_RESET (0)
> +#define OGMA_SOFT_RST_REG_RUN (1UL << 31)
> +
> +/* bit fields for dma_hm_ctrl */
> +#define OGMA_DMA_CTRL_REG_STOP 1UL
> +
> +/* bit fields for gmac_cmd */
> +#define OGMA_GMAC_CMD_ST_READ (0)
> +#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
> +#define OGMA_GMAC_CMD_ST_BUSY (1UL << 31)
> +
> +/* bit fields for F_GMAC4MT BMR*/
> +#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
> +#define OGMA_GMAC_BMR_REG_RESET (0x00020181)
> +#define OGMA_GMAC_BMR_REG_SWR (0x00000001)
> +
> +/* bit fields for F_GMAC4MT OMR*/
> +#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
> +#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
> +
> +/* bit fields for F_GMAC4MT MCR*/
> +#define OGMA_GMAC_MCR_REG_CST (1UL << 25)
> +#define OGMA_GMAC_MCR_REG_JE (1UL << 20)
> +#define OGMA_GMAC_MCR_REG_PS (1UL << 15)
> +#define OGMA_GMAC_MCR_REG_FES (1UL << 14)
> +#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
> +#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
> +
> +#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
> + OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
> + OGMA_GMAC_MCR_REG_PS | \
> + OGMA_GMAC_MCR_REG_FES | \
> + OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
> + OGMA_GMAC_MCR_REG_FES | \
> + OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
> + OGMA_GMAC_MCR_REG_PS | \
> + OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
> + OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
> +
> +/*bit fields for F_GMAC4MT FCR*/
> +#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
> +#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
> +
> +/* bit fields for F_GMAC4MT GAR */
> +#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
> +#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
> +
> +/* bit fields for F_GMAC4MT RDLAR*/
> +#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
> +
> +/* bit fields for F_GMAC4MT TDLAR*/
> +#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
> +
> +
> +#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
> +#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
> +#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
> +
> +#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ (2)
> +#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ (3)
> +#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ (0)
> +#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
> +#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
> +#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
> +
> +/* bit fields for F_GMAC4MT LPITCR */
> +#define OGMA_GMAC_LPITCR_REG_LIT (16)
> +#define OGMA_GMAC_LPITCR_REG_TWT (0)
> +
> +/* bit fileds mask for F_GMAC4MT LPITCR */
> +#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
> +#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
> +
> +/**
> + * PHY regtister Address
> + */
> +#define OGMA_PHY_REG_ADDR_CONTROL 0
> +#define OGMA_PHY_REG_ADDR_STATUS 1U
> +#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY 4U
> +#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
> +#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL 9U
> +#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS 10U
> +#define OGMA_PHY_REG_ADDR_MMD_AC 13U
> +#define OGMA_PHY_REG_ADDR_MMD_AAD 14U
> +
> +/* bit fields for PHY CONTROL Register */
> +#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
> +#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8)
> +#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12)
> +#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
> +
> +/* bit fields for PHY STATUS Register */
> +#define OGMA_PHY_STATUS_REG_LINK_STATUS (2)
> +#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
> +#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP (5)
> +
> +/* bit fields for PHY MASTER-SLAVE Control Register */
> +#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
> +#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
> +
> +/* bit fields for PHY MASTER-SLAVE Status Register */
> +#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
> +#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
> +
> +/* bit fields for PHY Auto-Negotiation Advertisement Register */
> +#define OGMA_PHY_ANA_REG_TAF (5)
> +
> +/* bit fileds mask for F_GMAC4MT LPITCR */
> +#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
> +
> +/* bit fields for PHY Technology Ability Field */
> +#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
> +#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
> +#define OGMA_PHY_TAF_REG_10BASE_FULL (1U << 1)
> +#define OGMA_PHY_TAF_REG_10BASE_HALF (1U << 0)
> +
> +/**
> + * PHY Device Address
> + */
> +#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
> +
> +/**
> + * PHY Register Address for Device Address 7
> + */
> +#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE (60U)
> +#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
> +
> +/* bit fields for PHY AutoNegotiation Field */
> +#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
> +#define OGMA_PHY_AUTO_NEGO_100BASE_EEE (1U << 1)
> +
> +/* bit fields for DESC RING CONFIG */
> +#define OGMA_REG_DESC_RING_CONFIG_CFG_UP (31)
> +#define OGMA_REG_DESC_RING_CONFIG_CH_RST (30)
> +#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE (4)
> +#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
> +
> +
> +/* bit fields for mac_desc_soft_rst */
> +#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
> +
> +/* bit fields for mac_desc_init */
> +#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
> +
> +/* bit fields for dis_core */
> +#define OGMA_DIS_CORE_REG_DIS_PCORE (1UL << 2)
> +#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
> +#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
> +
> +#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
> + OGMA_DIS_CORE_REG_DIS_MHCORE | \
> + OGMA_DIS_CORE_REG_DIS_PCORE)
> +
> +/* bit fields for dma_info */
> +#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
> +#define OGMA_DMA_INFO_REG_AXI_READ_BUSY (1UL << 2)
> +
> +#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
> + OGMA_DMA_INFO_REG_AXI_READ_BUSY)
> +
> +#endif /*OGMA_REG_H*/
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
> new file mode 100644
> index 000000000000..e12b317218fb
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
> @@ -0,0 +1,222 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_F_GMAC_4MT_H
> +#define OGMA_REG_F_GMAC_4MT_H
> +
> +/**
> + * GMAC register
> + */
> +#define OGMA_GMAC_REG_ADDR_MCR (0x0000)
> +#define OGMA_GMAC_REG_ADDR_MFFR (0x0004)
> +#define OGMA_GMAC_REG_ADDR_MHTRH (0x0008)
> +#define OGMA_GMAC_REG_ADDR_MHTRL (0x000c)
> +#define OGMA_GMAC_REG_ADDR_GAR (0x0010)
> +#define OGMA_GMAC_REG_ADDR_GDR (0x0014)
> +#define OGMA_GMAC_REG_ADDR_FCR (0x0018)
> +#define OGMA_GMAC_REG_ADDR_VTR (0x001c)
> +#define OGMA_GMAC_REG_ADDR_RWFFR (0x0028)
> +#define OGMA_GMAC_REG_ADDR_PMTR (0x002c)
> +#define OGMA_GMAC_REG_ADDR_LPICSR (0x0030)
> +#define OGMA_GMAC_REG_ADDR_LPITCR (0x0034)
> +#define OGMA_GMAC_REG_ADDR_ISR (0x0038)
> +#define OGMA_GMAC_REG_ADDR_IMR (0x003c)
> +#define OGMA_GMAC_REG_ADDR_MAR0H (0x0040)
> +#define OGMA_GMAC_REG_ADDR_MAR0L (0x0044)
> +#define OGMA_GMAC_REG_ADDR_MAR1H (0x0048)
> +#define OGMA_GMAC_REG_ADDR_MAR1L (0x004c)
> +#define OGMA_GMAC_REG_ADDR_MAR2H (0x0050)
> +#define OGMA_GMAC_REG_ADDR_MAR2L (0x0054)
> +#define OGMA_GMAC_REG_ADDR_MAR3H (0x0058)
> +#define OGMA_GMAC_REG_ADDR_MAR3L (0x005c)
> +#define OGMA_GMAC_REG_ADDR_MAR4H (0x0060)
> +#define OGMA_GMAC_REG_ADDR_MAR4L (0x0064)
> +#define OGMA_GMAC_REG_ADDR_MAR5H (0x0068)
> +#define OGMA_GMAC_REG_ADDR_MAR5L (0x006c)
> +#define OGMA_GMAC_REG_ADDR_MAR6H (0x0070)
> +#define OGMA_GMAC_REG_ADDR_MAR6L (0x0074)
> +#define OGMA_GMAC_REG_ADDR_MAR7H (0x0078)
> +#define OGMA_GMAC_REG_ADDR_MAR7L (0x007c)
> +#define OGMA_GMAC_REG_ADDR_MAR8H (0x0080)
> +#define OGMA_GMAC_REG_ADDR_MAR8L (0x0084)
> +#define OGMA_GMAC_REG_ADDR_MAR9H (0x0088)
> +#define OGMA_GMAC_REG_ADDR_MAR9L (0x008c)
> +#define OGMA_GMAC_REG_ADDR_MAR10H (0x0090)
> +#define OGMA_GMAC_REG_ADDR_MAR10L (0x0094)
> +#define OGMA_GMAC_REG_ADDR_MAR11H (0x0098)
> +#define OGMA_GMAC_REG_ADDR_MAR11L (0x009c)
> +#define OGMA_GMAC_REG_ADDR_MAR12H (0x00a0)
> +#define OGMA_GMAC_REG_ADDR_MAR12L (0x00a4)
> +#define OGMA_GMAC_REG_ADDR_MAR13H (0x00a8)
> +#define OGMA_GMAC_REG_ADDR_MAR13L (0x00ac)
> +#define OGMA_GMAC_REG_ADDR_MAR14H (0x00b0)
> +#define OGMA_GMAC_REG_ADDR_MAR14L (0x00b4)
> +#define OGMA_GMAC_REG_ADDR_MAR15H (0x00b8)
> +#define OGMA_GMAC_REG_ADDR_MAR15L (0x00bc)
> +#define OGMA_GMAC_REG_ADDR_RSR (0x00d8)
> +#define OGMA_GMAC_REG_ADDR_TSCR (0x0700)
> +#define OGMA_GMAC_REG_ADDR_SSIR (0x0704)
> +#define OGMA_GMAC_REG_ADDR_STSR (0x0708)
> +#define OGMA_GMAC_REG_ADDR_STNR (0x070c)
> +#define OGMA_GMAC_REG_ADDR_STSUR (0x0710)
> +#define OGMA_GMAC_REG_ADDR_STNUR (0x0714)
> +#define OGMA_GMAC_REG_ADDR_TSAR (0x0718)
> +#define OGMA_GMAC_REG_ADDR_TTSR (0x071c)
> +#define OGMA_GMAC_REG_ADDR_TTNR (0x0720)
> +#define OGMA_GMAC_REG_ADDR_STHWSR (0x0724)
> +#define OGMA_GMAC_REG_ADDR_TSR (0x0728)
> +#define OGMA_GMAC_REG_ADDR_PPSCR (0x072c)
> +#define OGMA_GMAC_REG_ADDR_ANTR (0x0730)
> +#define OGMA_GMAC_REG_ADDR_ATSR (0x0734)
> +#define OGMA_GMAC_REG_ADDR_MAR16H (0x0800)
> +#define OGMA_GMAC_REG_ADDR_MAR16L (0x0804)
> +#define OGMA_GMAC_REG_ADDR_MAR17H (0x0808)
> +#define OGMA_GMAC_REG_ADDR_MAR17L (0x080c)
> +#define OGMA_GMAC_REG_ADDR_MAR18H (0x0810)
> +#define OGMA_GMAC_REG_ADDR_MAR18L (0x0814)
> +#define OGMA_GMAC_REG_ADDR_MAR19H (0x0818)
> +#define OGMA_GMAC_REG_ADDR_MAR19L (0x081c)
> +#define OGMA_GMAC_REG_ADDR_MAR20H (0x0820)
> +#define OGMA_GMAC_REG_ADDR_MAR20L (0x0824)
> +#define OGMA_GMAC_REG_ADDR_MAR21H (0x0828)
> +#define OGMA_GMAC_REG_ADDR_MAR21L (0x082c)
> +#define OGMA_GMAC_REG_ADDR_MAR22H (0x0830)
> +#define OGMA_GMAC_REG_ADDR_MAR22L (0x0834)
> +#define OGMA_GMAC_REG_ADDR_MAR23H (0x0838)
> +#define OGMA_GMAC_REG_ADDR_MAR23L (0x083c)
> +#define OGMA_GMAC_REG_ADDR_MAR24H (0x0840)
> +#define OGMA_GMAC_REG_ADDR_MAR24L (0x0844)
> +#define OGMA_GMAC_REG_ADDR_MAR25H (0x0848)
> +#define OGMA_GMAC_REG_ADDR_MAR25L (0x084c)
> +#define OGMA_GMAC_REG_ADDR_MAR26H (0x0850)
> +#define OGMA_GMAC_REG_ADDR_MAR26L (0x0854)
> +#define OGMA_GMAC_REG_ADDR_MAR27H (0x0858)
> +#define OGMA_GMAC_REG_ADDR_MAR27L (0x085c)
> +#define OGMA_GMAC_REG_ADDR_MAR28H (0x0860)
> +#define OGMA_GMAC_REG_ADDR_MAR28L (0x0864)
> +#define OGMA_GMAC_REG_ADDR_MAR29H (0x0868)
> +#define OGMA_GMAC_REG_ADDR_MAR29L (0x086c)
> +#define OGMA_GMAC_REG_ADDR_MAR30H (0x0870)
> +#define OGMA_GMAC_REG_ADDR_MAR30L (0x0874)
> +#define OGMA_GMAC_REG_ADDR_MAR31H (0x0878)
> +#define OGMA_GMAC_REG_ADDR_MAR31L (0x087c)
> +
> +/**
> + * GMAC MAC Management Counters(Option) register
> + */
> +#define OGMA_GMAC_REG_ADDR_MMC_CNTL (0x0100)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX (0x0104)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX (0x0108)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX (0x010c)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX (0x0110)
> +#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB (0x0114)
> +#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB (0x0118)
> +#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G (0x011c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G (0x0120)
> +#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB (0x0124)
> +#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB (0x0128)
> +#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB (0x012c)
> +#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB (0x0130)
> +#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB (0x0134)
> +#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB (0x0138)
> +#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB (0x013c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB (0x0140)
> +#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB (0x0144)
> +#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR (0x0148)
> +#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G (0x014c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G (0x0150)
> +#define OGMA_GMAC_REG_ADDR_TXDEFERRED (0x0154)
> +#define OGMA_GMAC_REG_ADDR_TXLATECOL (0x0158)
> +#define OGMA_GMAC_REG_ADDR_TXEXESSCOL (0x015c)
> +#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR (0x0160)
> +#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G (0x0164)
> +#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G (0x0168)
> +#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF (0x016c)
> +#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES (0x0170)
> +#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G (0x0174)
> +#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB (0x0180)
> +#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB (0x0184)
> +#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G (0x0188)
> +#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G (0x018c)
> +#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G (0x0190)
> +#define OGMA_GMAC_REG_ADDR_RXCRCERROR (0x0194)
> +#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR (0x0198)
> +#define OGMA_GMAC_REG_ADDR_RXRUNTERROR (0x019c)
> +#define OGMA_GMAC_REG_ADDR_RXJABBERERROR (0x01a0)
> +#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G (0x01a4)
> +#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G (0x01a8)
> +#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB (0x01ac)
> +#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB (0x01b0)
> +#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB (0x01b4)
> +#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB (0x01b8)
> +#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB (0x01bc)
> +#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB (0x01c0)
> +#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G (0x01c4)
> +#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR (0x01c8)
> +#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE (0x01cc)
> +#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES (0x01d0)
> +#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW (0x01d4)
> +#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB (0x01d8)
> +#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR (0x01dc)
> +#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX (0x0200)
> +#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX (0x0208)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS (0x0210)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS (0x0214)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS (0x0218)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS (0x021c)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS (0x0220)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS (0x0224)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS (0x0228)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS (0x022c)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS (0x0230)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS (0x0234)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS (0x0238)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS (0x023c)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS (0x0240)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS (0x0244)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS (0x0250)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS (0x0254)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS (0x0258)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS (0x025c)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS (0x0260)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS (0x0264)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS (0x0268)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS (0x026c)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS (0x0270)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS (0x0274)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS (0x0278)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS (0x027c)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS (0x0280)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS (0x0284)
> +/**
> + * GMAC DMA register
> + */
> +#define OGMA_GMAC_REG_ADDR_BMR (0x1000)
> +#define OGMA_GMAC_REG_ADDR_TPDR (0x1004)
> +#define OGMA_GMAC_REG_ADDR_RPDR (0x1008)
> +#define OGMA_GMAC_REG_ADDR_RDLAR (0x100c)
> +#define OGMA_GMAC_REG_ADDR_TDLAR (0x1010)
> +#define OGMA_GMAC_REG_ADDR_SR (0x1014)
> +#define OGMA_GMAC_REG_ADDR_OMR (0x1018)
> +#define OGMA_GMAC_REG_ADDR_IER (0x101c)
> +#define OGMA_GMAC_REG_ADDR_MFOCR (0x1020)
> +#define OGMA_GMAC_REG_ADDR_RIWTR (0x1024)
> +#define OGMA_GMAC_REG_ADDR_AHBSR (0x102c)
> +#define OGMA_GMAC_REG_ADDR_CHTDR (0x1048)
> +#define OGMA_GMAC_REG_ADDR_CHRDR (0x104c)
> +#define OGMA_GMAC_REG_ADDR_CHTBAR (0x1050)
> +#define OGMA_GMAC_REG_ADDR_CHRBAR (0x1054)
> +
> +#endif /* OGMA_REG_F_GMAC_4MT_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
> new file mode 100644
> index 000000000000..457be2aa0cba
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
> @@ -0,0 +1,368 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_NETSEC_H
> +#define OGMA_REG_NETSEC_H
> +
> +#define OGMA_REG_ADDR_SOFT_RST (0x41)
> +#define OGMA_REG_ADDR_COM_INIT (0x48)
> +#define OGMA_REG_ADDR_MC_BASE_ADDR (0x97)
> +#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
> +#define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89)
> +#define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A)
> +#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
> +#define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C)
> +#define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D)
> +#define OGMA_REG_ADDR_DIS_CORE (0x86)
> +#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
> +#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
> +#define OGMA_REG_ADDR_CLK_EN_0 (0x40)
> +#define OGMA_REG_ADDR_CLK_EN_1 (0x64)
> +#define OGMA_REG_ADDR_PKT_CTRL (0x50)
> +#define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D)
> +#define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102)
> +#define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D)
> +#define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112)
> +#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D)
> +#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122)
> +#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D)
> +#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132)
> +#define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D)
> +#define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152)
> +#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D)
> +#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292)
> +#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C)
> +#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C)
> +#define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C)
> +#define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C)
> +#define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C)
> +#define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C)
> +#define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C)
> +#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
> +#define OGMA_REG_ADDR_TOP_STATUS (0x80)
> +#define OGMA_REG_ADDR_TOP_INTEN_A (0x81)
> +#define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D)
> +#define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E)
> +#define OGMA_REG_ADDR_TOP_INTEN_B (0x8F)
> +#define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90)
> +#define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91)
> +#define OGMA_REG_ADDR_PKT_STATUS (0x3)
> +#define OGMA_REG_ADDR_PKT_INTEN (0x4)
> +#define OGMA_REG_ADDR_PKT_INTEN_SET (0x7)
> +#define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8)
> +#define OGMA_REG_ADDR_TLS_STATUS (0x5)
> +#define OGMA_REG_ADDR_TLS_INTEN (0x6)
> +#define OGMA_REG_ADDR_TLS_INTEN_SET (0x9)
> +#define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA)
> +#define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE)
> +#define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12)
> +#define OGMA_REG_ADDR_MAC_STATUS (0x409)
> +#define OGMA_REG_ADDR_MAC_INTEN (0x40A)
> +#define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486)
> +#define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487)
> +#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B)
> +#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B)
> +#define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B)
> +#define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B)
> +#define OGMA_REG_ADDR_MISC_RX_STATUS (0x140)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN (0x141)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B)
> +#define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B)
> +#define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB)
> +#define OGMA_REG_ADDR_DEC_TX_STATUS (0x200)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN (0x201)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B)
> +#define OGMA_REG_ADDR_ENC_RX_STATUS (0x210)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN (0x211)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B)
> +#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
> +#define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134)
> +#define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274)
> +#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
> +#define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275)
> +#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
> +#define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276)
> +#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
> +#define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137)
> +#define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7)
> +#define OGMA_REG_ADDR_DEC_TX_TMR (0x207)
> +#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
> +#define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138)
> +#define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8)
> +#define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208)
> +#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
> +#define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125)
> +#define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145)
> +#define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295)
> +#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
> +#define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126)
> +#define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146)
> +#define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196)
> +#define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6)
> +#define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216)
> +#define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246)
> +#define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256)
> +#define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286)
> +#define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296)
> +#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
> +#define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127)
> +#define OGMA_REG_ADDR_MISC_RX_TMR (0x147)
> +#define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7)
> +#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
> +#define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128)
> +#define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148)
> +#define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8)
> +#define OGMA_REG_ADDR_PODB_CMD_ST (0x20)
> +#define OGMA_REG_ADDR_PODB_DATA (0x21)
> +#define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A)
> +#define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B)
> +#define OGMA_REG_ADDR_CLS_CMD_ST (0x2C)
> +#define OGMA_REG_ADDR_CLS_DATA (0x2D)
> +#define OGMA_REG_ADDR_SADB_CMD_ST (0x2E)
> +#define OGMA_REG_ADDR_SADB_DATA (0x2F)
> +#define OGMA_REG_ADDR_MAC_CMD (0x471)
> +#define OGMA_REG_ADDR_MAC_DATA (0x470)
> +#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
> +#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
> +#define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476)
> +#define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477)
> +#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478)
> +#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479)
> +#define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A)
> +#define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B)
> +#define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C)
> +#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F)
> +#define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480)
> +#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
> +#define OGMA_REG_ADDR_IV_INIT_VAL (0x45)
> +#define OGMA_REG_ADDR_MAC_ADD_UP (0x43)
> +#define OGMA_REG_ADDR_MAC_ADD_LW (0x44)
> +#define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65)
> +#define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66)
> +#define OGMA_REG_ADDR_ST_INFO_SIZE (0x67)
> +#define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68)
> +#define OGMA_REG_ADDR_LOGIC_GR_ID (0x69)
> +#define OGMA_REG_ADDR_ST_FOR_PBC (0x6A)
> +#define OGMA_REG_ADDR_ALARM_INFO (0x6B)
> +#define OGMA_REG_ADDR_MC_VER (0x8B)
> +#define OGMA_REG_ADDR_HW_VER (0x8C)
> +
> +#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
> +
> +#endif /* OGMA_REG_F_TAIKI_H */
> +
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
> new file mode 100644
> index 000000000000..1caf64e30623
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
> @@ -0,0 +1,25 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_CONFIG_H
> +#define OGMA_CONFIG_H
> +
> +#define OGMA_CONFIG_CLK_HZ 125000000UL
> +#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
> +#define OGMA_CONFIG_CHECK_CLK_SUPPLY
> +
> +#define OGMA_CONFIG_USE_READ_GMAC_STAT
> +
> +#endif /* OGMA_CONFIG_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
> new file mode 100644
> index 000000000000..f617f1c70183
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
> @@ -0,0 +1,265 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef PFDEP_H
> +#define PFDEP_H
> +
> +#include <stdio.h>
> +#include <stdint.h>
> +#include <string.h>
Whut?
Can we get rid of these?
/
Leif
> +#include <Library/BaseLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <Protocol/Cpu.h>
> +
> +extern EFI_CPU_ARCH_PROTOCOL *mCpu;
> +
> +/**********************************************************************
> + * Constant definitions
> + **********************************************************************/
> +#define PFDEP_INT64_AVAILABLE
> +
> +/**********************************************************************
> + * Elementary type definitions
> + **********************************************************************/
> +typedef int8_t pfdep_int8;
> +typedef uint8_t pfdep_uint8;
> +typedef int16_t pfdep_int16;
> +typedef uint16_t pfdep_uint16;
> +typedef int pfdep_int32;
> +typedef unsigned int pfdep_uint32;
> +typedef int64_t pfdep_int64;
> +typedef uint64_t pfdep_uint64;
> +typedef int pfdep_bool;
> +typedef char pfdep_char;
> +
> +#define PFDEP_TRUE ((pfdep_bool)1)
> +#define PFDEP_FALSE ((pfdep_bool)0)
> +
> +
> +/**********************************************************************
> + * Complex type definitions
> + **********************************************************************/
> +
> +typedef enum pfdep_err_e {
> + PFDEP_ERR_OK = 0,
> + PFDEP_ERR_PARAM,
> + PFDEP_ERR_ALLOC,
> + PFDEP_ERR_INTERRUPT
> +} pfdep_err_t;
> +
> +
> +typedef struct {
> + LIST_ENTRY Link;
> + VOID *Buffer;
> + VOID *Mapping;
> + BOOLEAN RecycleForTx;
> + BOOLEAN Released;
> +} PACKET_HANDLE;
> +
> +typedef VOID *pfdep_dev_handle_t;
> +typedef PACKET_HANDLE *pfdep_pkt_handle_t;
> +typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
> +typedef UINT64 pfdep_cpu_addr_t;
> +
> +typedef int pfdep_hard_lock_t;
> +typedef int pfdep_soft_lock_t;
> +
> +typedef BOOLEAN pfdep_hard_lock_ctx_t;
> +typedef int pfdep_soft_lock_ctx_t;
> +
> +typedef unsigned int pfdep_debug_level_t;
> +
> +#define PFDEP_DEBUG_LEVEL_FATAL ((pfdep_debug_level_t)1)
> +#define PFDEP_DEBUG_LEVEL_WARNING ((pfdep_debug_level_t)2)
> +#define PFDEP_DEBUG_LEVEL_NOTICE ((pfdep_debug_level_t)3)
> +#define PFDEP_DEBUG_LEVEL_DEBUG ((pfdep_debug_level_t)4)
> +#define PFDEP_DEBUG_LEVEL_DEBUG_DETAILED ((pfdep_debug_level_t)5)
> +#define PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED ((pfdep_debug_level_t)6)
> +
> +/**********************************************************************
> + * Variable declarations
> + **********************************************************************/
> +extern pfdep_debug_level_t pfdep_debug_level; /* defined in pfdep_uefi.c */
> +
> +
> +/**********************************************************************
> + * Function declarations
> + **********************************************************************/
> +
> +static __inline pfdep_uint32 pfdep_iomem_read(void *addr)
> +{
> + return *((volatile pfdep_uint32 *)(addr));
> +}
> +
> +static __inline void pfdep_iomem_write(void *addr, pfdep_uint32 val)
> +{
> + *((volatile pfdep_uint32 *)(addr)) = val;
> +
> +
> +}
> +
> +#define pfdep_read_mem_barrier() MemoryFence()
> +#define pfdep_write_mem_barrier() MemoryFence()
> +#define pfdep_mem_barrier() MemoryFence()
> +
> +void *pfdep_malloc(pfdep_uint32 len);
> +
> +void pfdep_free(void *addr);
> +
> +pfdep_err_t pfdep_dma_malloc (
> + pfdep_dev_handle_t dev_handle,
> + pfdep_uint32 len,
> + void **addr_p,
> + pfdep_phys_addr_t *phys_addr_p
> + );
> +
> +void pfdep_dma_free (
> + pfdep_dev_handle_t dev_handle,
> + pfdep_uint32 len,
> + void *addr,
> + pfdep_phys_addr_t phys_addr
> + );
> +
> +pfdep_err_t pfdep_alloc_pkt_buf (
> + pfdep_dev_handle_t dev_handle,
> + pfdep_uint16 len,
> + void **addr_p,
> + pfdep_phys_addr_t *phys_addr_p,
> + pfdep_pkt_handle_t *pkt_handle_p
> + );
> +
> +void pfdep_free_pkt_buf (
> + pfdep_dev_handle_t dev_handle,
> + pfdep_uint16 len,
> + void *addr,
> + pfdep_phys_addr_t phys_addr,
> + pfdep_bool last_flag,
> + pfdep_pkt_handle_t pkt_handle
> + );
> +
> +static __inline pfdep_err_t pfdep_init_hard_lock(pfdep_hard_lock_t *hard_lock_p)
> +{
> + (void)hard_lock_p; /* suppress compiler warning */
> + return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_uninit_hard_lock(pfdep_hard_lock_t *hard_lock_p)
> +{
> + (void)hard_lock_p; /* suppress compiler warning */
> + return;
> +}
> +
> +static __inline void pfdep_acquire_hard_lock (
> + pfdep_hard_lock_t *hard_lock_p, /* not used */
> + pfdep_hard_lock_ctx_t *ctx_p
> + )
> +{
> + (void)hard_lock_p; /* suppress compiler warning */
> +
> + *ctx_p = SaveAndDisableInterrupts();
> +}
> +
> +
> +static __inline void pfdep_release_hard_lock (
> + pfdep_hard_lock_t *hard_lock_p, /* not used */
> + pfdep_hard_lock_ctx_t *ctx_p
> + )
> +{
> + (void)hard_lock_p; /* suppress compiler warning */
> +
> + SetInterruptState(*ctx_p);
> +}
> +
> +static __inline pfdep_err_t pfdep_init_soft_lock (
> + pfdep_soft_lock_t *soft_lock_p
> + )
> +{
> + *soft_lock_p = 0; /* suppress compiler warning */
> +
> + return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_uninit_soft_lock (
> + pfdep_soft_lock_t *soft_lock_p
> + )
> +{
> + (void)soft_lock_p; /* suppress compiler warning */
> +
> + return;
> +}
> +
> +static __inline pfdep_err_t pfdep_acquire_soft_lock (
> + pfdep_soft_lock_t *soft_lock_p,
> + pfdep_soft_lock_ctx_t *ctx_p
> + )
> +{
> + (void)soft_lock_p; /* suppress compiler warning */
> + (void)ctx_p; /* suppress compiler warning */
> +
> + return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_release_soft_lock (
> + pfdep_soft_lock_t *soft_lock_p,
> + pfdep_soft_lock_ctx_t *ctx_p
> + )
> +{
> + (void)soft_lock_p; /* suppress compiler warning */
> + (void)ctx_p; /* suppress compiler warning */
> +}
> +
> +
> +static __inline void pfdep_memcpy(void *dst_p, const void *src_p, pfdep_uint32 len)
> +{
> + memcpy(dst_p, src_p, (size_t)len);
> +}
> +
> +static __inline void pfdep_memset(void *dst_p, pfdep_uint8 c, pfdep_uint32 len)
> +{
> + memset(dst_p, c, (size_t)len);
> +}
> +
> +static __inline pfdep_err_t pfdep_msleep(pfdep_uint32 wait_ms)
> +{
> +
> + MicroSecondDelay ((UINTN)wait_ms * 1000);
> +
> + return PFDEP_ERR_OK;
> +}
> +
> +#define pfdep_print(level,...) \
> +do { \
> + if (level <= pfdep_debug_level) { \
> + DEBUG ((DEBUG_INFO, "[NETSEC] " __VA_ARGS__)); \
> + } \
> +} while (0)
> +
> +
> +static __inline pfdep_debug_level_t pfdep_get_debug_level(void)
> +{
> + return pfdep_debug_level;
> +}
> +
> +static __inline void pfdep_set_debug_level(pfdep_debug_level_t level)
> +{
> + pfdep_debug_level = level;
> +}
> +
> +
> +#define pfdep_assert(cond) ASSERT(cond)
> +
> +#endif /* PFDEP_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
> new file mode 100644
> index 000000000000..b43d1aaff037
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
> @@ -0,0 +1,176 @@
> +/** @file
> +
> + Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "pfdep.h"
> +
> +#include <Library/DebugLib.h>
> +#include <Library/DmaLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/NetLib.h>
> +#include <Library/SynchronizationLib.h>
> +
> +/**********************************************************************
> + * Variable definitions
> + **********************************************************************/
> +pfdep_debug_level_t pfdep_debug_level = PFDEP_DEBUG_LEVEL_NOTICE;
> +
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +VOID*
> +pfdep_malloc (
> + IN pfdep_uint32 len
> + )
> +{
> + return AllocatePool (len);
> +}
> +
> +VOID
> +pfdep_free (
> + IN VOID *addr
> + )
> +{
> + FreePool (addr);
> +}
> +
> +pfdep_err_t
> +pfdep_dma_malloc (
> + IN pfdep_dev_handle_t dev_handle,
> + IN pfdep_uint32 len,
> + OUT VOID **addr_p,
> + OUT pfdep_phys_addr_t *phys_addr_p
> + )
> +{
> + EFI_STATUS Status;
> + UINTN NumPages;
> + UINTN NumBytes;
> + VOID **Mapping;
> +
> + NumPages = EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof *Mapping);
> + Status = DmaAllocateBuffer (EfiBootServicesData, NumPages, addr_p);
> + if (EFI_ERROR (Status)) {
> + return PFDEP_ERR_ALLOC;
> + }
> +
> + //
> + // Stash the address of the MAPINFO struct at the end of the buffer,
> + // but make sure it appears aligned (the memory may be mapped uncached)
> + //
> + Mapping = (VOID **)((UINTN)*addr_p + ALIGN_VARIABLE(len));
> +
> + NumBytes = EFI_PAGES_TO_SIZE (NumPages);
> + Status = DmaMap (MapOperationBusMasterCommonBuffer, *addr_p, &NumBytes,
> + phys_addr_p, Mapping);
> +
> + if (EFI_ERROR (Status) || NumBytes < len) {
> + DmaFreeBuffer (NumPages, *addr_p);
> + return PFDEP_ERR_ALLOC;
> + }
> +
> + return PFDEP_ERR_OK;
> +}
> +
> +VOID
> +pfdep_dma_free (
> + IN pfdep_dev_handle_t dev_handle,
> + IN pfdep_uint32 len,
> + IN VOID *addr,
> + IN pfdep_phys_addr_t phys_addr
> + )
> +{
> + VOID *Mapping;
> +
> + Mapping = *(VOID **)((UINTN)addr + ALIGN_VARIABLE(len));
> +
> + DmaUnmap (Mapping);
> + DmaFreeBuffer (EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof Mapping),
> + addr);
> +}
> +
> +//
> +// On the receive path, we allocate a new packet and link it into the RX ring
> +// before returning the received packet to the caller. This means we perform
> +// one allocation and one free operation for each buffer received.
> +// So let's cache a single packet, and get rid of most of the alloc/free
> +// overhead on the RX path.
> +//
> +STATIC pfdep_pkt_handle_t mSparePacketBuffer;
> +STATIC UINT32 mSparePacketBufferSize;
> +
> +pfdep_err_t
> +pfdep_alloc_pkt_buf (
> + IN pfdep_dev_handle_t dev_handle,
> + IN pfdep_uint16 len,
> + OUT VOID **addr_p,
> + OUT pfdep_phys_addr_t *phys_addr_p,
> + OUT pfdep_pkt_handle_t *pkt_handle_p
> + )
> +{
> + EFI_STATUS Status;
> + UINTN NumBytes;
> +
> + NumBytes = ALIGN_VALUE (len, mCpu->DmaBufferAlignment);
> +
> + if (InterlockedCompareExchange32 (&mSparePacketBufferSize, len, 0) == len) {
> + *pkt_handle_p = mSparePacketBuffer;
> + } else {
> + *pkt_handle_p = AllocateZeroPool (NumBytes + sizeof(PACKET_HANDLE) +
> + (mCpu->DmaBufferAlignment - 8));
> + if (*pkt_handle_p == NULL) {
> + return PFDEP_ERR_ALLOC;
> + }
> +
> + (*pkt_handle_p)->Buffer = ALIGN_POINTER (*pkt_handle_p,
> + mCpu->DmaBufferAlignment);
> + }
> +
> + *addr_p = (*pkt_handle_p)->Buffer;
> + Status = DmaMap (MapOperationBusMasterWrite, *addr_p, &NumBytes, phys_addr_p,
> + &(*pkt_handle_p)->Mapping);
> + if (EFI_ERROR (Status) || NumBytes < len) {
> + FreePool (*pkt_handle_p);
> + return PFDEP_ERR_ALLOC;
> + }
> + return PFDEP_ERR_OK;
> +}
> +
> +VOID
> +pfdep_free_pkt_buf (
> + IN pfdep_dev_handle_t dev_handle,
> + IN pfdep_uint16 len,
> + IN VOID *addr,
> + IN pfdep_phys_addr_t phys_addr,
> + IN pfdep_bool last_flag,
> + IN pfdep_pkt_handle_t pkt_handle
> + )
> +{
> + if (last_flag != PFDEP_TRUE) {
> + return;
> + }
> +
> + if (pkt_handle->Mapping != NULL) {
> + DmaUnmap (pkt_handle->Mapping);
> + }
> +
> + if (pkt_handle->RecycleForTx) {
> + pkt_handle->Released = TRUE;
> + } else if (!InterlockedCompareExchange32 (&mSparePacketBufferSize, 0, len)) {
> + mSparePacketBuffer = pkt_handle;
> + } else {
> + FreePool (pkt_handle);
> + }
> +}
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
2017-09-11 16:12 ` Leif Lindholm
@ 2017-10-28 13:06 ` Ard Biesheuvel
2017-10-28 21:25 ` Leif Lindholm
0 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-10-28 13:06 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel@lists.01.org,
Pipat/メタワニットポン ピパット,
Masahisa Kojima, Masami Hiramatsu
On 11 September 2017 at 17:12, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Fri, Sep 08, 2017 at 07:23:09PM +0100, Ard Biesheuvel wrote:
>> This adds the NetSecDxe driver provided by Socionext, but reworked
>> extensively to improve compliance with the SimpleNetworkProtocol API,
>> and to avoid uncached allocations for streaming DMA.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1000 ++++++++++++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 88 ++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 +
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 265 ++++
>> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++
>> 21 files changed, 8013 insertions(+)
>>
>> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
>> new file mode 100644
>> index 000000000000..7c3f12362f14
>> --- /dev/null
>> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
>> @@ -0,0 +1,1000 @@
>> +/** @file
>> +
>> + Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
>> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <Library/DebugLib.h>
>> +#include <Library/DmaLib.h>
>> +#include <Library/UefiBootServicesTableLib.h>
>> +#include <Library/MemoryAllocationLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/NetLib.h>
>
> Sorted alphabetically, please?
>
>> +
>> +#include "NetsecDxe.h"
>> +#include "netsec_for_uefi/pfdep.h"
>
> Hmm, could that be folded into NetsecDxe.h?
>
Yes, but I would have to modify all the 'platform independent' source
files, and not having to modify them is kind of the point.
...
>> +
>> + ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
>> + OGMA_CH_IRQ_REG_EMPTY);
>> +
>> + // ##### configure_mac
>
> In general, it feels like each of these comment headers indicate a
> good place to break a block out into a helper function.
>
Meh. This function is not complex at all, it just does a bunch of
steps in sequence. Don't see the point really.
...
Apologies for snipping the context - my edit window became intolerably
slow due to the size of the email. I /think/ I incorporated all other
feedback you gave to this patch.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
2017-10-28 13:06 ` Ard Biesheuvel
@ 2017-10-28 21:25 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-10-28 21:25 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel@lists.01.org,
Pipat/メタワニットポン ピパット,
Masahisa Kojima, Masami Hiramatsu
On Sat, Oct 28, 2017 at 02:06:42PM +0100, Ard Biesheuvel wrote:
> On 11 September 2017 at 17:12, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > On Fri, Sep 08, 2017 at 07:23:09PM +0100, Ard Biesheuvel wrote:
> >> This adds the NetSecDxe driver provided by Socionext, but reworked
> >> extensively to improve compliance with the SimpleNetworkProtocol API,
> >> and to avoid uncached allocations for streaming DMA.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> ---
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 1000 ++++++++++++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 47 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h | 88 ++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 69 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h | 736 ++++++++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h | 45 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h | 24 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c | 88 ++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h | 52 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c | 1391 +++++++++++++++++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h | 111 ++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c | 1454 ++++++++++++++++++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h | 210 +++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c | 1385 +++++++++++++++++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h | 38 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h | 219 +++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h | 222 +++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h | 368 +++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 25 +
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h | 265 ++++
> >> Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c | 176 +++
> >> 21 files changed, 8013 insertions(+)
> >>
> >> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> >> new file mode 100644
> >> index 000000000000..7c3f12362f14
> >> --- /dev/null
> >> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> >> @@ -0,0 +1,1000 @@
> >> +/** @file
> >> +
> >> + Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
> >> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> >> +
> >> + This program and the accompanying materials
> >> + are licensed and made available under the terms and conditions of the BSD License
> >> + which accompanies this distribution. The full text of the license may be found at
> >> + http://opensource.org/licenses/bsd-license.php
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> +
> >> +**/
> >> +
> >> +#include <Library/DebugLib.h>
> >> +#include <Library/DmaLib.h>
> >> +#include <Library/UefiBootServicesTableLib.h>
> >> +#include <Library/MemoryAllocationLib.h>
> >> +#include <Library/IoLib.h>
> >> +#include <Library/NetLib.h>
> >
> > Sorted alphabetically, please?
> >
> >> +
> >> +#include "NetsecDxe.h"
> >> +#include "netsec_for_uefi/pfdep.h"
> >
> > Hmm, could that be folded into NetsecDxe.h?
> >
>
> Yes, but I would have to modify all the 'platform independent' source
> files, and not having to modify them is kind of the point.
> ...
I was actually referring to just the #include statement.
But part of the reason I suggested that was that I was hoping to
reduce the amount on non-conforming style.
Further reading though the rest of the file showed this to be a drop
in the ocean really.
> >> +
> >> + ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
> >> + OGMA_CH_IRQ_REG_EMPTY);
> >> +
> >> + // ##### configure_mac
> >
> > In general, it feels like each of these comment headers indicate a
> > good place to break a block out into a helper function.
> >
>
> Meh. This function is not complex at all, it just does a bunch of
> steps in sequence. Don't see the point really.
> ...
It's more a question of overviewability without familiarity with the
underlying implementation. But it's a preference rather than anything
stronger.
> Apologies for snipping the context - my edit window became intolerably
> slow due to the size of the email. I /think/ I incorporated all other
> feedback you gave to this patch.
Yes, I think so.
/
Leif
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (7 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 16:23 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support Ard Biesheuvel
` (4 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Add the NETSEC driver to the SynquacerEvalBoard platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 34 ++++++++++++++++++++
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 17 ++++++++++
2 files changed, 51 insertions(+)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index aea39b46d91b..3d4fbc87e2fa 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -217,6 +217,20 @@
gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
+ #
+ # NETSEC Info
+ #
+ gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x522D0000
+ gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x10000000
+ gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128
+ gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128
+ gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36
+ gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48
+ gNetsecDxeTokenSpaceGuid.PcdPauseTime|256
+ gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|1
+
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
@@ -441,3 +455,23 @@
# RNG
#
Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+ Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
+ <LibraryClasses>
+ DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ }
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index befad354918e..bd06adf93b3c 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -166,6 +166,23 @@ READ_LOCK_STATUS = TRUE
#
INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+ INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
+
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver
2017-09-08 18:23 ` [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver Ard Biesheuvel
@ 2017-09-11 16:23 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 16:23 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:10PM +0100, Ard Biesheuvel wrote:
> Add the NETSEC driver to the SynquacerEvalBoard platform.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 34 ++++++++++++++++++++
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 17 ++++++++++
> 2 files changed, 51 insertions(+)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index aea39b46d91b..3d4fbc87e2fa 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -217,6 +217,20 @@
> gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
> gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
>
> + #
> + # NETSEC Info
> + #
> + gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x522D0000
> + gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x10000000
> + gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128
> + gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128
> + gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36
> + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48
> + gNetsecDxeTokenSpaceGuid.PcdPauseTime|256
> + gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|1
> +
> gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> @@ -441,3 +455,23 @@
> # RNG
> #
> Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> +
> + #
> + # Networking stack
> + #
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
So, I'm going to take my couple of days to hack on config fragments
from tomorrow, so you may just want to wait on that - but otherwise,
IPv6 and HTTP boot would be nice.
/
Leif
> + Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
> + <LibraryClasses>
> + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> + }
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index befad354918e..bd06adf93b3c 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -166,6 +166,23 @@ READ_LOCK_STATUS = TRUE
> #
> INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
>
> + #
> + # Networking stack
> + #
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> + INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> +
> [FV.FVMAIN_COMPACT]
> FvAlignment = 8
> ERASE_POLARITY = 1
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (8 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 16:33 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board Ard Biesheuvel
` (3 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Enable ACPI support for the SynquacerEvalBoard platform: add descriptions
of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
including the MSI routing via the GICv3 ITS.
Note that PCIe support is limited to a single bus per RC. Anything beyond
that is unsupported due to a limitation in the hardware that makes it
impossible to expose the PCIe RCs in a fully ECAM compliant manner.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 14 +
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 13 +
Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl | 292 ++++++++++++++++++++
Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h | 58 ++++
Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf | 58 ++++
Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl | 168 +++++++++++
Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc | 88 ++++++
Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc | 98 +++++++
Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc | 164 +++++++++++
Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc | 152 ++++++++++
Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc | 63 +++++
Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc | 127 +++++++++
12 files changed, 1295 insertions(+)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 3d4fbc87e2fa..b2befd2480c4 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -475,3 +475,17 @@
<LibraryClasses>
DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
}
+
+ #
+ # ACPI support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <LibraryClasses>
+ #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+ <PcdsFixedAtBuild>
+ # support ACPI v5.0 or later
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+ }
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index bd06adf93b3c..35742ad5a347 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -183,6 +183,13 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
+ #
+ # ACPI support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
+
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
@@ -329,3 +336,9 @@ READ_LOCK_STATUS = TRUE
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index 000000000000..f8d503d65ead
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,292 @@
+/** @file
+ Secondary System Description Table (SSDT) for Synquacer PCIe RCs
+
+ Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Platform/Pcie.h>
+
+#include "AcpiTables.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+ Scope(_SB) {
+ //
+ // PCI Root Complex
+ //
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 1) // Cache Coherency Attribute
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package () { 0xFFFF, 0, Zero, 222 }, // INTA
+ Package () { 0xFFFF, 1, Zero, 222 }, // INTB
+ Package () { 0xFFFF, 2, Zero, 222 }, // INTC
+ Package () { 0xFFFF, 3, Zero, 222 }, // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMinimum - Minimum Bus Number
+ SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 1 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address
+ 0x00000000, // Translate
+ SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address
+ 0x00000000, // Translate
+ SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Address
+ SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate
+ SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ SYNQUACER_PCI_SEG0_CONFIG_BASE,
+ SYNQUACER_PCI_SEG0_CONFIG_SIZE)
+ })
+ }
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ See [1] 6.2.10, [2] 4.5
+ */
+ Method(_OSC,4) {
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+
+ Device(PCI1)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, 1) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 1) // Cache Coherency Attribute
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package () { 0xFFFF, 0, Zero, 214 }, // INTA
+ Package () { 0xFFFF, 1, Zero, 214 }, // INTB
+ Package () { 0xFFFF, 2, Zero, 214 }, // INTC
+ Package () { 0xFFFF, 3, Zero, 214 }, // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMinimum - Minimum Bus Number
+ SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 1 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address
+ 0x00000000, // Translate
+ SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG1_MMIO64_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG1_MMIO64_MAX, // Max Base Address
+ 0x00000000, // Translate
+ SYNQUACER_PCI_SEG1_MMIO64_SIZE // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ SYNQUACER_PCI_SEG1_PORTIO_MIN, // Min Base Address
+ SYNQUACER_PCI_SEG1_PORTIO_MAX, // Max Base Address
+ SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, // Translate
+ SYNQUACER_PCI_SEG1_PORTIO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ SYNQUACER_PCI_SEG1_CONFIG_BASE,
+ SYNQUACER_PCI_SEG1_CONFIG_SIZE)
+ })
+ }
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ See [1] 6.2.10, [2] 4.5
+ */
+ Method(_OSC,4) {
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ }
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
new file mode 100644
index 000000000000..73fe4f5caa3e
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
@@ -0,0 +1,58 @@
+/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ACPITABLES_H__
+#define __ACPITABLES_H__
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID 'L','I','N','A','R','O' // OEMID 6 bytes long
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('S','Y','N','Q','U','A','C','R') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION 0x20170802
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
+#define EFI_ACPI_CREATOR_REVISION 0x00000001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define __ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+ { \
+ EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisRegionAddr, RedisDiscLength \
+ }
+
+#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \
+ { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id, PhysAddress, 0 }
+
+#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress, \
+ ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags) \
+ { \
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \
+ EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \
+ WatchdogTimerGSIV, WatchdogTimerFlags \
+ }
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..f390797b9d4f
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SynquacerAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ AcpiTables.h
+ AcpiSsdtRootPci.asl
+ Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Madt.aslc
+ Mcfg.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
new file mode 100644
index 000000000000..dc32a34ccfa2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
@@ -0,0 +1,168 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "AcpiTables.h"
+
+#include <Platform/MemoryMap.h>
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+ Scope(_SB) {
+ //
+ // A53x4 Processor declaration
+ //
+ Device(CP00) { // A53-0: Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CP01) { // A53-0: Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+
+ Device(CP04) { // A53-0: Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CP05) { // A53-0: Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+
+ Device(CP08) { // A53-0: Cluster 2, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CP09) { // A53-0: Cluster 2, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+
+ Device(CP12) { // A53-0: Cluster 3, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CP13) { // A53-0: Cluster 3, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+
+ Device(CP16) { // A53-0: Cluster 4, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CP17) { // A53-0: Cluster 4, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+
+ Device(CP20) { // A53-0: Cluster 5, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP21) { // A53-0: Cluster 5, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+
+ Device(CP24) { // A53-0: Cluster 6, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP25) { // A53-0: Cluster 6, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+
+ Device(CP28) { // A53-0: Cluster 7, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP29) { // A53-0: Cluster 7, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+
+ Device(CP32) { // A53-0: Cluster 8, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 16)
+ }
+ Device(CP33) { // A53-0: Cluster 8, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 17)
+ }
+
+ Device(CP36) { // A53-0: Cluster 9, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 18)
+ }
+ Device(CP37) { // A53-0: Cluster 9, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 19)
+ }
+
+ Device(CP40) { // A53-0: Cluster 10, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 20)
+ }
+ Device(CP41) { // A53-0: Cluster 10, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 21)
+ }
+
+ Device(CP44) { // A53-0: Cluster 11, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 22)
+ }
+ Device(CP45) { // A53-0: Cluster 11, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 23)
+ }
+
+ // UART PL011
+ Device(COM0) {
+ Name(_HID, "ARMH0011")
+ Name(_CID, "PL011")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 }
+ })
+ }
+
+ Device(NET0) {
+ Name(_HID, "SCX0001")
+ Name(_UID, Zero)
+ Name(_CCA, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE,
+ SYNQUACER_NETSEC_BASE_SZ)
+ Memory32Fixed(ReadWrite, SYNQUACER_EEPROM_BASE,
+ SYNQUACER_EEPROM_BASE_SZ)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 }
+ })
+
+ Name (_DSD, Package () // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package (2) { "phy-mode", "rgmii" },
+ Package (2) { "phy-channel", 0x1 },
+ Package (2) { "max-speed", 1000 },
+ Package (2) { "max-frame-size", 9000 },
+ Package (2) { "socionext,phy-clock-frequency", 125000000 },
+ }
+ })
+ }
+ } // Scope(_SB)
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..26e4e0fc8964
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
@@ -0,0 +1,88 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+ 0 // UINT64 HypervisorVendorIdentity;
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..f22c27f05454
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
@@ -0,0 +1,98 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE TimerBase;
+ EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE TimerFrame;
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdog;
+} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ __ACPI_HEADER(
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES,
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ 2, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ },
+ {
+ EFI_ACPI_6_0_GTDT_GT_BLOCK, // UINT8 Type
+ sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) +
+ sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE), // UINT16 Length
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved
+ 0x2A810000, // UINT64 CntCtlBase
+ 1, // UINT32 GTBlockTimerCount
+ sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset
+ },
+ {
+ 0, // UINT8 GTFrameNumber
+ {0, 0, 0}, // UINT8 Reserved[3]
+ 0x2A830000, // UINT64 CntBaseX
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX
+ 92, // UINT32 GTxPhysicalTimerGSIV
+ GTDT_TIMER_LEVEL_TRIGGERED | GTDT_TIMER_ACTIVE_HIGH, // UINT32 GTxPhysicalTimerFlags
+ 0, // UINT32 GTxVirtualTimerGSIV
+ 0, // UINT32 GTxVirtualTimerFlags
+ EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY // UINT32 GTxCommonFlags
+ },
+ EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+ FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, 0),
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
new file mode 100644
index 000000000000..bbb425f1f808
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
@@ -0,0 +1,164 @@
+/** @file
+
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/IoRemappingTable.h>
+
+#include "AcpiTables.h"
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node;
+ UINT32 Identifiers[1];
+} SYNQUACER_ITS_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[2];
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
+} SYNQUACER_SMMU_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
+} SYNQUACER_RC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
+ SYNQUACER_ITS_NODE ItsNode;
+ //SYNQUACER_SMMU_NODE Smmu;
+ SYNQUACER_RC_NODE RcNode[2];
+} SYNQUACER_IO_REMAPPING_STRUCTURE;
+
+#define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds) \
+ { \
+ { \
+ EFI_ACPI_IORT_TYPE_SMMUv1v2, \
+ sizeof(SYNQUACER_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ NumIds, \
+ FIELD_OFFSET(SYNQUACER_SMMU_NODE, RcIdMapping), \
+ }, \
+ Base, \
+ Size, \
+ EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, \
+ 0, \
+ FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
+ SMMU_NSgIrpt), \
+ 0x2, \
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
+ 0x0, \
+ 0x0, \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ 0x0, \
+ 0x0, \
+ }, { \
+ { \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ }, \
+ { \
+ Irq, \
+ EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
+ }, \
+ }
+
+#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \
+ { \
+ In, \
+ Num, \
+ Out, \
+ FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref), \
+ Flags \
+ }
+
+STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
+ {
+ __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+ SYNQUACER_IO_REMAPPING_STRUCTURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+ 3, // NumNodes
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0 // Reserved
+ }, {
+ // ItsNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
+ sizeof(SYNQUACER_ITS_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x0, // NumIdMappings
+ 0x0, // IdReference
+ },
+ 1,
+ }, {
+ 0x0
+ },
+ }, {
+// __SYNQUACER_SMMU_NODE(0x582C0000, 0x10000, 234, 1),
+// { __SYNQUACER_ID_MAPPING(0x200, 0x0, 0x0, ItsNode, 0x0), }
+// }, {
+ // PciRcNode
+ {
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof(SYNQUACER_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x0, // PciSegmentNumber
+ }, {
+ __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
+ },
+ }, {
+ // PciRcNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof(SYNQUACER_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x1, // PciSegmentNumber
+ }, {
+ __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
+ }
+ }
+ }
+};
+
+#pragma pack()
+
+VOID* CONST ReferenceAcpiTable = &Iort;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
new file mode 100644
index 000000000000..a8c27dcf8923
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
@@ -0,0 +1,152 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)];
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts;
+} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ __ACPI_HEADER (
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+ // ACPI v6.0).
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
+ 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1
+ 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2
+ 0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3
+ 0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4
+ 0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5
+ 0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6
+ 0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7
+ 0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8
+ 0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9
+ 0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10
+ 0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11
+ 0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12
+ 0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13
+ 0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14
+ 0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15
+ 0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16
+ 0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17
+ 0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18
+ 0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19
+ 0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20
+ 0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21
+ 0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22
+ 0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23
+ 0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3),
+ // GIC Redistributor
+ EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x300000),
+ // GIC ITS
+ EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
new file mode 100644
index 000000000000..00df5f181de3
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
@@ -0,0 +1,63 @@
+/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <Platform/Pcie.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
+ {
+ __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ },
+ {
+ {
+ SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,
+ 0,
+ SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+ SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+ EFI_ACPI_RESERVED_DWORD
+ }, {
+ SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000,
+ 1,
+ SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+ SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+ EFI_ACPI_RESERVED_DWORD
+ }
+ }
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
new file mode 100644
index 000000000000..f51475e5c6a2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
@@ -0,0 +1,127 @@
+/** @file
+
+ Serial Port Console Redirection Table
+ (c) 2000 - 2014 Microsoft Corporation. All rights reserved.
+ http://go.microsoft.com/fwlink/?linkid=403368
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#include "AcpiTables.h"
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ //
+ // Header
+ //
+ __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ //
+ // InterfaceType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ //
+ // Reserved[3]
+ //
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ //
+ // BaseAddress
+ //
+ {
+ EFI_ACPI_5_1_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_5_1_DWORD,
+ FixedPcdGet32 (PcdSerialRegisterBase)
+ },
+ //
+ // InterruptType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ //
+ // Irq
+ //
+ 0,
+ //
+ // GlobalSystemInterrupt
+ //
+ 95,
+ //
+ // BaudRate
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ //
+ // Parity
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ //
+ // StopBits
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ //
+ // FlowControl
+ //
+ 0,
+ //
+ // TerminalType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ //
+ // Language
+ //
+ EFI_ACPI_RESERVED_BYTE,
+ //
+ // PciDeviceId
+ //
+ 0xFFFF,
+ //
+ // PciVendorId
+ //
+ 0xFFFF,
+ //
+ // PciBusNumber
+ //
+ 0x00,
+ //
+ // PciDeviceNumber
+ //
+ 0x00,
+ //
+ // PciFunctionNumber
+ //
+ 0x00,
+ //
+ // PciFlags
+ //
+ 0,
+ //
+ // PciSegment
+ //
+ 0,
+ //
+ // Reserved2
+ //
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support
2017-09-08 18:23 ` [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support Ard Biesheuvel
@ 2017-09-11 16:33 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 16:33 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:11PM +0100, Ard Biesheuvel wrote:
> Enable ACPI support for the SynquacerEvalBoard platform: add descriptions
> of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
> including the MSI routing via the GICv3 ITS.
>
> Note that PCIe support is limited to a single bus per RC. Anything beyond
> that is unsupported due to a limitation in the hardware that makes it
> impossible to expose the PCIe RCs in a fully ECAM compliant manner.
>
Very few comments here (could we get someone else in to review?).
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 14 +
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 13 +
> Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl | 292 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h | 58 ++++
> Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf | 58 ++++
> Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl | 168 +++++++++++
> Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc | 88 ++++++
> Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc | 98 +++++++
> Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc | 164 +++++++++++
> Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc | 152 ++++++++++
> Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc | 63 +++++
> Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc | 127 +++++++++
> 12 files changed, 1295 insertions(+)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index 3d4fbc87e2fa..b2befd2480c4 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -475,3 +475,17 @@
> <LibraryClasses>
> DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> }
> +
> + #
> + # ACPI support
> + #
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
> + <LibraryClasses>
> + #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
> +
> + <PcdsFixedAtBuild>
> + # support ACPI v5.0 or later
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
> + }
> + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index bd06adf93b3c..35742ad5a347 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -183,6 +183,13 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
>
> + #
> + # ACPI support
> + #
> + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
> +
> [FV.FVMAIN_COMPACT]
> FvAlignment = 8
> ERASE_POLARITY = 1
> @@ -329,3 +336,9 @@ READ_LOCK_STATUS = TRUE
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI |.acpi
> + RAW ASL |.aml
> + }
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
> new file mode 100644
> index 000000000000..f8d503d65ead
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
> @@ -0,0 +1,292 @@
> +/** @file
> + Secondary System Description Table (SSDT) for Synquacer PCIe RCs
> +
> + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Platform/Pcie.h>
> +
> +#include "AcpiTables.h"
> +
> +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
> + Scope(_SB) {
> + //
> + // PCI Root Complex
> + //
> + Device(PCI0)
> + {
> + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> + Name(_SEG, Zero) // PCI Segment Group number
> + Name(_BBN, Zero) // PCI Base Bus Number
> + Name(_CCA, 1) // Cache Coherency Attribute
> +
> + // PCI Routing Table
> + Name(_PRT, Package() {
> + Package () { 0xFFFF, 0, Zero, 222 }, // INTA
> + Package () { 0xFFFF, 1, Zero, 222 }, // INTB
> + Package () { 0xFFFF, 2, Zero, 222 }, // INTC
> + Package () { 0xFFFF, 3, Zero, 222 }, // INTD
> + })
> + // Root complex resources
> + Method (_CRS, 0, Serialized) {
> + Name (RBUF, ResourceTemplate () {
> + WordBusNumber ( // Bus numbers assigned to this root
> + ResourceProducer,
> + MinFixed, MaxFixed, PosDecode,
> + 0, // AddressGranularity
> + SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMinimum - Minimum Bus Number
> + SYNQUACER_PCI_SEG0_BUSNUM_MIN, // AddressMaximum - Maximum Bus Number
> + 0, // AddressTranslation - Set to 0
> + 1 // RangeLength - Number of Busses
> + )
> +
> + DWordMemory ( // 32-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address
> + 0x00000000, // Translate
> + SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length
> + )
> +
> + QWordMemory ( // 64-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address
> + 0x00000000, // Translate
> + SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length
> + )
> +
> + DWordIo ( // IO window
> + ResourceProducer,
> + MinFixed,
> + MaxFixed,
> + PosDecode,
> + EntireRange,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG0_PORTIO_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG0_PORTIO_MAX, // Max Base Address
> + SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate
> + SYNQUACER_PCI_SEG0_PORTIO_SIZE, // Length
> + ,
> + ,
> + ,
> + TypeTranslation
> + )
> + }) // Name(RBUF)
> +
> + Return (RBUF)
> + } // Method(_CRS)
> +
> + Device (RES0)
> + {
> + Name (_HID, "PNP0C02")
> + Name (_CRS, ResourceTemplate ()
> + {
> + Memory32Fixed (ReadWrite,
> + SYNQUACER_PCI_SEG0_CONFIG_BASE,
> + SYNQUACER_PCI_SEG0_CONFIG_SIZE)
> + })
> + }
> +
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> +
> + /*
> + See [1] 6.2.10, [2] 4.5
> + */
> + Method(_OSC,4) {
> + // Check for proper UUID
> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + // Create DWord-adressable fields from the Capabilities Buffer
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + CreateDWordField(Arg3,8,CDW3)
> +
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + // Only allow native hot plug control if OS supports:
> + // * ASPM
> + // * Clock PM
> + // * MSI/MSI-X
> + If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> + }
> +
> + // Always allow native PME, AER (no dependencies)
> +
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> +
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return(Arg3)
> + } Else {
> + Or(CDW1,4,CDW1) // Unrecognized UUID
> + Return(Arg3)
> + }
> + } // End _OSC
> + } // PCI0
> +
> + Device(PCI1)
> + {
> + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> + Name(_SEG, 1) // PCI Segment Group number
> + Name(_BBN, Zero) // PCI Base Bus Number
> + Name(_CCA, 1) // Cache Coherency Attribute
> +
> + // PCI Routing Table
> + Name(_PRT, Package() {
> + Package () { 0xFFFF, 0, Zero, 214 }, // INTA
> + Package () { 0xFFFF, 1, Zero, 214 }, // INTB
> + Package () { 0xFFFF, 2, Zero, 214 }, // INTC
> + Package () { 0xFFFF, 3, Zero, 214 }, // INTD
> + })
> + // Root complex resources
> + Method (_CRS, 0, Serialized) {
> + Name (RBUF, ResourceTemplate () {
> + WordBusNumber ( // Bus numbers assigned to this root
> + ResourceProducer,
> + MinFixed, MaxFixed, PosDecode,
> + 0, // AddressGranularity
> + SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMinimum - Minimum Bus Number
> + SYNQUACER_PCI_SEG1_BUSNUM_MIN, // AddressMaximum - Maximum Bus Number
> + 0, // AddressTranslation - Set to 0
> + 1 // RangeLength - Number of Busses
> + )
> +
> + DWordMemory ( // 32-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address
> + 0x00000000, // Translate
> + SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length
> + )
> +
> + QWordMemory ( // 64-bit BAR Windows
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + Cacheable, ReadWrite,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG1_MMIO64_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG1_MMIO64_MAX, // Max Base Address
> + 0x00000000, // Translate
> + SYNQUACER_PCI_SEG1_MMIO64_SIZE // Length
> + )
> +
> + DWordIo ( // IO window
> + ResourceProducer,
> + MinFixed,
> + MaxFixed,
> + PosDecode,
> + EntireRange,
> + 0x00000000, // Granularity
> + SYNQUACER_PCI_SEG1_PORTIO_MIN, // Min Base Address
> + SYNQUACER_PCI_SEG1_PORTIO_MAX, // Max Base Address
> + SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, // Translate
> + SYNQUACER_PCI_SEG1_PORTIO_SIZE, // Length
> + ,
> + ,
> + ,
> + TypeTranslation
> + )
> + }) // Name(RBUF)
> +
> + Return (RBUF)
> + } // Method(_CRS)
> +
> + Device (RES0)
> + {
> + Name (_HID, "PNP0C02")
> + Name (_CRS, ResourceTemplate ()
> + {
> + Memory32Fixed (ReadWrite,
> + SYNQUACER_PCI_SEG1_CONFIG_BASE,
> + SYNQUACER_PCI_SEG1_CONFIG_SIZE)
> + })
> + }
> +
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> +
> + /*
> + See [1] 6.2.10, [2] 4.5
> + */
> + Method(_OSC,4) {
> + // Check for proper UUID
> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + // Create DWord-adressable fields from the Capabilities Buffer
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + CreateDWordField(Arg3,8,CDW3)
> +
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + // Only allow native hot plug control if OS supports:
> + // * ASPM
> + // * Clock PM
> + // * MSI/MSI-X
> + If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> + }
> +
> + // Always allow native PME, AER (no dependencies)
> +
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> +
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return(Arg3)
> + } Else {
> + Or(CDW1,4,CDW1) // Unrecognized UUID
> + Return(Arg3)
> + }
> + } // End _OSC
> + } // PCI0
> + }
> +}
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
> new file mode 100644
> index 000000000000..73fe4f5caa3e
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
> @@ -0,0 +1,58 @@
> +/** @file
> +*
> +* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __ACPITABLES_H__
> +#define __ACPITABLES_H__
> +
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_OEM_ID 'L','I','N','A','R','O' // OEMID 6 bytes long
> +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('S','Y','N','Q','U','A','C','R') // OEM table id 8 bytes long
> +#define EFI_ACPI_OEM_REVISION 0x20170802
> +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
The Linaro IDs here - are they to be considered temporary until
Socionext get their own?
> +#define EFI_ACPI_CREATOR_REVISION 0x00000001
> +
> +// A macro to initialise the common header part of EFI ACPI tables as defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define __ACPI_HEADER(Signature, Type, Revision) { \
> + Signature, /* UINT32 Signature */ \
> + sizeof (Type), /* UINT32 Length */ \
> + Revision, /* UINT8 Revision */ \
> + 0, /* UINT8 Checksum */ \
> + { EFI_ACPI_OEM_ID }, /* UINT8 OemId[6] */ \
> + EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
> + EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
> + EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
> + EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
> + }
> +
> +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
> + { \
> + EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisRegionAddr, RedisDiscLength \
> + }
> +
> +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \
> + { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id, PhysAddress, 0 }
> +
> +#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress, \
> + ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags) \
> + { \
> + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \
> + EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \
> + WatchdogTimerGSIV, WatchdogTimerFlags \
> + }
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
> new file mode 100644
> index 000000000000..f390797b9d4f
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
> @@ -0,0 +1,58 @@
> +## @file
> +#
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Bump.
> + BASE_NAME = SynquacerAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + AcpiTables.h
> + AcpiSsdtRootPci.asl
> + Dsdt.asl
> + Fadt.aslc
> + Gtdt.aslc
> + Iort.aslc
> + Madt.aslc
> + Mcfg.aslc
> + Spcr.aslc
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + ArmPkg/ArmPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[FixedPcd]
> + gArmPlatformTokenSpaceGuid.PcdClusterCount
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> +
> + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
> + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
> new file mode 100644
> index 000000000000..dc32a34ccfa2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
> @@ -0,0 +1,168 @@
> +/** @file
> + Differentiated System Description Table Fields (DSDT)
> +
> + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "AcpiTables.h"
> +
> +#include <Platform/MemoryMap.h>
> +
> +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
> + Scope(_SB) {
> + //
> + // A53x4 Processor declaration
> + //
> + Device(CP00) { // A53-0: Cluster 0, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 0)
> + }
> + Device(CP01) { // A53-0: Cluster 0, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 1)
> + }
> +
> + Device(CP04) { // A53-0: Cluster 1, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 2)
> + }
> + Device(CP05) { // A53-0: Cluster 1, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 3)
> + }
Is keeping 4 device names per cluster (so giving holes here) mandated
by ACPI?
> +
> + Device(CP08) { // A53-0: Cluster 2, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 4)
> + }
> + Device(CP09) { // A53-0: Cluster 2, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 5)
> + }
> +
> + Device(CP12) { // A53-0: Cluster 3, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 6)
> + }
> + Device(CP13) { // A53-0: Cluster 3, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 7)
> + }
> +
> + Device(CP16) { // A53-0: Cluster 4, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 8)
> + }
> + Device(CP17) { // A53-0: Cluster 4, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 9)
> + }
> +
> + Device(CP20) { // A53-0: Cluster 5, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 10)
> + }
> + Device(CP21) { // A53-0: Cluster 5, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 11)
> + }
> +
> + Device(CP24) { // A53-0: Cluster 6, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 12)
> + }
> + Device(CP25) { // A53-0: Cluster 6, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 13)
> + }
> +
> + Device(CP28) { // A53-0: Cluster 7, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 14)
> + }
> + Device(CP29) { // A53-0: Cluster 7, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 15)
> + }
> +
> + Device(CP32) { // A53-0: Cluster 8, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 16)
> + }
> + Device(CP33) { // A53-0: Cluster 8, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 17)
> + }
> +
> + Device(CP36) { // A53-0: Cluster 9, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 18)
> + }
> + Device(CP37) { // A53-0: Cluster 9, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 19)
> + }
> +
> + Device(CP40) { // A53-0: Cluster 10, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 20)
> + }
> + Device(CP41) { // A53-0: Cluster 10, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 21)
> + }
> +
> + Device(CP44) { // A53-0: Cluster 11, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 22)
> + }
> + Device(CP45) { // A53-0: Cluster 11, Cpu 1
> + Name(_HID, "ACPI0007")
> + Name(_UID, 23)
> + }
> +
> + // UART PL011
> + Device(COM0) {
> + Name(_HID, "ARMH0011")
> + Name(_CID, "PL011")
> + Name(_UID, Zero)
> + Name(_CRS, ResourceTemplate() {
> + Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000)
> + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 }
> + })
> + }
> +
> + Device(NET0) {
> + Name(_HID, "SCX0001")
> + Name(_UID, Zero)
> + Name(_CCA, Zero)
> + Name(_CRS, ResourceTemplate() {
> + Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE,
> + SYNQUACER_NETSEC_BASE_SZ)
> + Memory32Fixed(ReadWrite, SYNQUACER_EEPROM_BASE,
> + SYNQUACER_EEPROM_BASE_SZ)
> + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 }
> + })
> +
> + Name (_DSD, Package () // _DSD: Device-Specific Data
> + {
> + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
> + Package () {
> + Package (2) { "phy-mode", "rgmii" },
> + Package (2) { "phy-channel", 0x1 },
> + Package (2) { "max-speed", 1000 },
> + Package (2) { "max-frame-size", 9000 },
> + Package (2) { "socionext,phy-clock-frequency", 125000000 },
> + }
> + })
> + }
> + } // Scope(_SB)
> +}
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
> new file mode 100644
> index 000000000000..26e4e0fc8964
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
> @@ -0,0 +1,88 @@
> +/** @file
> +* Fixed ACPI Description Table (FADT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "AcpiTables.h"
> +
> +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> + __ACPI_HEADER (
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
> + ),
> + 0, // UINT32 FirmwareCtrl
> + 0, // UINT32 Dsdt
> + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
> + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
> + 0, // UINT16 SciInt
> + 0, // UINT32 SmiCmd
> + 0, // UINT8 AcpiEnable
> + 0, // UINT8 AcpiDisable
> + 0, // UINT8 S4BiosReq
> + 0, // UINT8 PstateCnt
> + 0, // UINT32 Pm1aEvtBlk
> + 0, // UINT32 Pm1bEvtBlk
> + 0, // UINT32 Pm1aCntBlk
> + 0, // UINT32 Pm1bCntBlk
> + 0, // UINT32 Pm2CntBlk
> + 0, // UINT32 PmTmrBlk
> + 0, // UINT32 Gpe0Blk
> + 0, // UINT32 Gpe1Blk
> + 0, // UINT8 Pm1EvtLen
> + 0, // UINT8 Pm1CntLen
> + 0, // UINT8 Pm2CntLen
> + 0, // UINT8 PmTmrLen
> + 0, // UINT8 Gpe0BlkLen
> + 0, // UINT8 Gpe1BlkLen
> + 0, // UINT8 Gpe1Base
> + 0, // UINT8 CstCnt
> + 0, // UINT16 PLvl2Lat
> + 0, // UINT16 PLvl3Lat
> + 0, // UINT16 FlushSize
> + 0, // UINT16 FlushStride
> + 0, // UINT8 DutyOffset
> + 0, // UINT8 DutyWidth
> + 0, // UINT8 DayAlrm
> + 0, // UINT8 MonAlrm
> + 0, // UINT8 Century
> + 0, // UINT16 IaPcBootArch
> + 0, // UINT8 Reserved1
> + EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg
> + 0, // UINT8 ResetValue
> + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
> + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
> + 0, // UINT64 XFirmwareCtrl
> + 0, // UINT64 XDsdt
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
> + NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
> + 0 // UINT64 HypervisorVendorIdentity;
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Fadt;
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
> new file mode 100644
> index 000000000000..f22c27f05454
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
> @@ -0,0 +1,98 @@
> +/** @file
> +* Generic Timer Description Table (GTDT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "AcpiTables.h"
> +
> +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
> +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
> +#define GTDT_GLOBAL_FLAGS_LEVEL 0
> +
> +#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
> +
> +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
> +#define GTDT_TIMER_LEVEL_TRIGGERED 0
> +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
> +#define GTDT_TIMER_ACTIVE_HIGH 0
> +
> +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
> +
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
> + EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE TimerBase;
> + EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE TimerFrame;
> + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdog;
> +} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES;
> +
> +#pragma pack ()
> +
> +EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
> + {
> + __ACPI_HEADER(
> + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES,
> + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
> + ),
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
> + 0, // UINT32 Reserved
> + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
> + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
> + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
> + 2, // UINT32 PlatformTimerCount
> + sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
> + },
> + {
> + EFI_ACPI_6_0_GTDT_GT_BLOCK, // UINT8 Type
> + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) +
> + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE), // UINT16 Length
> + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved
> + 0x2A810000, // UINT64 CntCtlBase
> + 1, // UINT32 GTBlockTimerCount
> + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset
> + },
> + {
> + 0, // UINT8 GTFrameNumber
> + {0, 0, 0}, // UINT8 Reserved[3]
> + 0x2A830000, // UINT64 CntBaseX
> + 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX
> + 92, // UINT32 GTxPhysicalTimerGSIV
> + GTDT_TIMER_LEVEL_TRIGGERED | GTDT_TIMER_ACTIVE_HIGH, // UINT32 GTxPhysicalTimerFlags
> + 0, // UINT32 GTxVirtualTimerGSIV
> + 0, // UINT32 GTxVirtualTimerFlags
> + EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY // UINT32 GTxCommonFlags
> + },
> + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
> + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, 0),
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Gtdt;
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
> new file mode 100644
> index 000000000000..bbb425f1f808
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
> @@ -0,0 +1,164 @@
> +/** @file
> +
> + Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IndustryStandard/IoRemappingTable.h>
> +
> +#include "AcpiTables.h"
> +
> +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node;
> + UINT32 Identifiers[1];
> +} SYNQUACER_ITS_NODE;
> +
> +typedef struct {
> + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node;
> + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[2];
> + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
> +} SYNQUACER_SMMU_NODE;
> +
> +typedef struct {
> + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
> + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping[1];
> +} SYNQUACER_RC_NODE;
> +
> +typedef struct {
> + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
> + SYNQUACER_ITS_NODE ItsNode;
> + //SYNQUACER_SMMU_NODE Smmu;
> + SYNQUACER_RC_NODE RcNode[2];
> +} SYNQUACER_IO_REMAPPING_STRUCTURE;
> +
> +#define __SYNQUACER_SMMU_NODE(Base, Size, Irq, NumIds) \
> + { \
> + { \
> + EFI_ACPI_IORT_TYPE_SMMUv1v2, \
> + sizeof(SYNQUACER_SMMU_NODE), \
> + 0x0, \
> + 0x0, \
> + NumIds, \
> + FIELD_OFFSET(SYNQUACER_SMMU_NODE, RcIdMapping), \
> + }, \
> + Base, \
> + Size, \
> + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, \
> + 0, \
> + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \
> + SMMU_NSgIrpt), \
> + 0x2, \
> + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), \
> + 0x0, \
> + 0x0, \
> + Irq, \
> + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
> + 0x0, \
> + 0x0, \
> + }, { \
> + { \
> + Irq, \
> + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
> + }, \
> + { \
> + Irq, \
> + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, \
> + }, \
> + }
> +
> +#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \
> + { \
> + In, \
> + Num, \
> + Out, \
> + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref), \
> + Flags \
> + }
> +
> +STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
> + {
> + __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
> + SYNQUACER_IO_REMAPPING_STRUCTURE,
> + EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
> + 3, // NumNodes
> + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
> + 0 // Reserved
> + }, {
> + // ItsNode
> + {
> + {
> + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
> + sizeof(SYNQUACER_ITS_NODE), // Length
> + 0x0, // Revision
> + 0x0, // Reserved
> + 0x0, // NumIdMappings
> + 0x0, // IdReference
> + },
> + 1,
> + }, {
> + 0x0
> + },
> + }, {
> +// __SYNQUACER_SMMU_NODE(0x582C0000, 0x10000, 234, 1),
> +// { __SYNQUACER_ID_MAPPING(0x200, 0x0, 0x0, ItsNode, 0x0), }
> +// }, {
> + // PciRcNode
> + {
> + {
> + {
> + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
> + sizeof(SYNQUACER_RC_NODE), // Length
> + 0x0, // Revision
> + 0x0, // Reserved
> + 0x1, // NumIdMappings
> + FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference
> + },
> + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
> + 0x0, // AllocationHints
> + 0x0, // Reserved
> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
> + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
> + 0x0, // PciSegmentNumber
> + }, {
> + __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
> + },
> + }, {
> + // PciRcNode
> + {
> + {
> + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
> + sizeof(SYNQUACER_RC_NODE), // Length
> + 0x0, // Revision
> + 0x0, // Reserved
> + 0x1, // NumIdMappings
> + FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference
> + },
> + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
> + 0x0, // AllocationHints
> + 0x0, // Reserved
> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags
> + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
> + 0x1, // PciSegmentNumber
> + }, {
> + __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
> + }
> + }
> + }
> +};
> +
> +#pragma pack()
> +
> +VOID* CONST ReferenceAcpiTable = &Iort;
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
> new file mode 100644
> index 000000000000..a8c27dcf8923
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
> @@ -0,0 +1,152 @@
> +/** @file
> +* Multiple APIC Description Table (MADT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#include "AcpiTables.h"
> +
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdClusterCount) * FixedPcdGet32 (PcdCoreCount)];
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor;
> + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts;
> +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> + {
> + __ACPI_HEADER (
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
> + ),
> + //
> + // MADT specific fields
> + //
> + 0, // LocalApicAddress
> + 0, // Flags
> + },
> + {
> + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, GicBase, GicVBase,
> + // GicHBase, GsivId, GicRBase)
> + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
> + // ACPI v6.0).
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0
> + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1
> + 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2
> + 0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3
> + 0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4
> + 0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5
> + 0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6
> + 0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7
> + 0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8
> + 0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9
> + 0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10
> + 0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11
> + 0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12
> + 0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13
> + 0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14
> + 0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15
> + 0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16
> + 0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17
> + 0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18
> + 0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19
> + 0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20
> + 0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21
> + 0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> +
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22
> + 0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23
> + 0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase),
> + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
> + },
> + // GIC Distributor Entry
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3),
> + // GIC Redistributor
> + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), 0x300000),
> + // GIC ITS
> + EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000)
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Madt;
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
> new file mode 100644
> index 000000000000..00df5f181de3
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
> @@ -0,0 +1,63 @@
> +/** @file
> +
> + ACPI Memory mapped configuration space base address Description Table (MCFG).
> + Implementation based on PCI Firmware Specification Revision 3.0 final draft,
> + downloadable at http://www.pcisig.com/home
> +
> + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
> + Copyright (c) 2017, Linaro Limited. All rights reserved.
> +
> + This program and the accompanying materials are licensed and
> + made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the
> + license may be found at http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
> +#include <Platform/Pcie.h>
> +
> +#include "AcpiTables.h"
> +
> +#pragma pack(push, 1)
> +
> +typedef struct {
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
> + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2];
> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
> +
> +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
> + {
> + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
> + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
> + EFI_ACPI_RESERVED_QWORD
> + },
> + {
> + {
> + SYNQUACER_PCI_SEG0_CONFIG_BASE | 0x8000,
> + 0,
> + SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> + SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> + EFI_ACPI_RESERVED_DWORD
> + }, {
> + SYNQUACER_PCI_SEG1_CONFIG_BASE | 0x8000,
> + 1,
> + SYNQUACER_PCI_SEG1_BUSNUM_MIN,
> + SYNQUACER_PCI_SEG1_BUSNUM_MIN,
> + EFI_ACPI_RESERVED_DWORD
> + }
> + }
> +};
> +
> +#pragma pack(pop)
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Mcfg;
> diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
> new file mode 100644
> index 000000000000..f51475e5c6a2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
> @@ -0,0 +1,127 @@
> +/** @file
> +
> + Serial Port Console Redirection Table
> + (c) 2000 - 2014 Microsoft Corporation. All rights reserved.
> + http://go.microsoft.com/fwlink/?linkid=403368
> +
> + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IndustryStandard/Acpi61.h>
> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> +
> +#include "AcpiTables.h"
> +
> +#pragma pack(push, 1)
> +
> +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> + //
> + // Header
> + //
> + __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> + 2), /* New MS definition for PL011 support */
Umm, PL011 is defined as 0x0003 in my DBG2 version.
2 is ("reserved").
32-bit only SBSA UART and SBSA UART are 0x000d and 0x000e respectively.
/
Leif
> + //
> + // InterfaceType
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
> + //
> + // Reserved[3]
> + //
> + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
> + //
> + // BaseAddress
> + //
> + {
> + EFI_ACPI_5_1_SYSTEM_MEMORY,
> + 32,
> + 0,
> + EFI_ACPI_5_1_DWORD,
> + FixedPcdGet32 (PcdSerialRegisterBase)
> + },
> + //
> + // InterruptType
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> + //
> + // Irq
> + //
> + 0,
> + //
> + // GlobalSystemInterrupt
> + //
> + 95,
> + //
> + // BaudRate
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> + //
> + // Parity
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> + //
> + // StopBits
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> + //
> + // FlowControl
> + //
> + 0,
> + //
> + // TerminalType
> + //
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> + //
> + // Language
> + //
> + EFI_ACPI_RESERVED_BYTE,
> + //
> + // PciDeviceId
> + //
> + 0xFFFF,
> + //
> + // PciVendorId
> + //
> + 0xFFFF,
> + //
> + // PciBusNumber
> + //
> + 0x00,
> + //
> + // PciDeviceNumber
> + //
> + 0x00,
> + //
> + // PciFunctionNumber
> + //
> + 0x00,
> + //
> + // PciFlags
> + //
> + 0,
> + //
> + // PciSegment
> + //
> + 0,
> + //
> + // Reserved2
> + //
> + EFI_ACPI_RESERVED_DWORD
> +};
> +
> +#pragma pack(pop)
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing
> +// the data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Spcr;
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (9 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 16:37 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 12/14] Silicon/Synquacer: add NorFlashPlatformLib implementation Ard Biesheuvel
` (2 subsequent siblings)
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Add a device tree description of the Synquacer SoC, and expose it for
the SynquacerEvalBoard platforms. This includes the menu option in the
UEFI boot menu to switch between ACPI and DT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 9 +
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 12 +
Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi | 517 ++++++++++++++++++++
Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts | 21 +
Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf | 28 ++
5 files changed, 587 insertions(+)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index b2befd2480c4..92c1d3eb8283 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -489,3 +489,12 @@
}
MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
+
+ #
+ # DT support
+ #
+ Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
+ EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
+ <LibraryClasses>
+ DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
+ }
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index 35742ad5a347..de97d3e56ded 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -1,3 +1,4 @@
+
#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
# Copyright (c) 2017, Linaro Limited. All rights reserved.
@@ -190,6 +191,12 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
+ #
+ # DT support
+ #
+ INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
+ INF RuleOverride = DTB Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
+
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
@@ -342,3 +349,8 @@ READ_LOCK_STATUS = TRUE
RAW ACPI |.acpi
RAW ASL |.aml
}
+
+[Rule.Common.USER_DEFINED.DTB]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN |.dtb
+ }
diff --git a/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
new file mode 100644
index 000000000000..8142bcc6adc8
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
@@ -0,0 +1,517 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution. The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+ aliases {
+ serial0 = &soc_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU4: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU5: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x201>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU6: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU7: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x301>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU8: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU9: cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x401>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU10: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU11: cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x501>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU12: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU13: cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x601>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU14: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU15: cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x701>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU16: cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU17: cpu@801 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x801>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU18: cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU19: cpu@901 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x901>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU20: cpu@a00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU21: cpu@a01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU22: cpu@b00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU23: cpu@b01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+ core1 {
+ cpu = <&CPU5>;
+ };
+ };
+ cluster3 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+ cluster4 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+ core1 {
+ cpu = <&CPU9>;
+ };
+ };
+ cluster5 {
+ core0 {
+ cpu = <&CPU10>;
+ };
+ core1 {
+ cpu = <&CPU11>;
+ };
+ };
+ cluster6 {
+ core0 {
+ cpu = <&CPU12>;
+ };
+ core1 {
+ cpu = <&CPU13>;
+ };
+ };
+ cluster7 {
+ core0 {
+ cpu = <&CPU14>;
+ };
+ core1 {
+ cpu = <&CPU15>;
+ };
+ };
+ cluster8 {
+ core0 {
+ cpu = <&CPU16>;
+ };
+ core1 {
+ cpu = <&CPU17>;
+ };
+ };
+ cluster9 {
+ core0 {
+ cpu = <&CPU18>;
+ };
+ core1 {
+ cpu = <&CPU19>;
+ };
+ };
+ cluster10 {
+ core0 {
+ cpu = <&CPU20>;
+ };
+ core1 {
+ cpu = <&CPU21>;
+ };
+ };
+ cluster11 {
+ core0 {
+ cpu = <&CPU22>;
+ };
+ core1 {
+ cpu = <&CPU23>;
+ };
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2000>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2500>;
+ local-timer-stop;
+ };
+ };
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0x0 0x10000>, // GICD
+ <0x0 0x30400000 0x0 0x300000>, // GICR
+ <0x0 0x2c000000 0x0 0x2000>, // GICC
+ <0x0 0x2c010000 0x0 0x1000>, // GICH
+ <0x0 0x2c020000 0x0 0x2000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ its: gic-its@30020000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30020000 0x0 0x20000>;
+ #msi-cells = <1>;
+ msi-controller;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
+ };
+
+ mmio-timer@2a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x2a810000 0x0 0x10000>;
+ clock-frequency = <100000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ frame@2a830000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x2a830000 0x0 0x10000>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ mailbox: mhu@45000000 {
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0x0 0x45000000 0x0 0x1000>;
+ interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; /* Non-Sec */
+ interrupt-names = "mhu_lpri_rx", "mhu_hpri_rx";
+ #mbox-cells = <1>;
+ clocks = <&clk_apb>;
+ clock-names = "apb_pclk";
+ };
+
+ sram: sram@45200000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x45200000 0x0 0x200>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x45200000 0x200>;
+
+ cpu_scp_hpri: scp-shmem@0 {
+ reg = <0x0 0x200>;
+ };
+ };
+
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 1>;
+ shmem = <&cpu_scp_hpri>;
+ };
+
+ clk_uart: refclk62500khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ clock-output-names = "uartclk";
+ };
+
+ clk_apb: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_uart0: uart@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart &clk_apb>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ clk_netsec: refclk125mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ #clock-cells = <0>;
+ };
+
+ eth0: netsec@522D0000 {
+ compatible = "socionext,netsecv5";
+ reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_netsec>;
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ max-frame-size = <9000>;
+ phy-handle = <ðphy0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+ smmu: iommu@582c0000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0x0 0x582c0000 0x0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie0: pcie@60000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x60000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
+ <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Synquacer SoC supports ITS device ID 0 only */
+ msi-map-mask = <0x0>;
+ msi-map = <0x0 &its 0x0 0x1>;
+ dma-coherent;
+ };
+
+ pcie1: pcie@70000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x70000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
+ <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Synquacer SoC supports ITS device ID 0 only */
+ msi-map-mask = <0x0>;
+ msi-map = <0x0 &its 0x0 0x1>;
+ dma-coherent;
+ };
+};
diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
new file mode 100644
index 000000000000..0e46d2979128
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
@@ -0,0 +1,21 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution. The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+/dts-v1/;
+
+#include "Synquacer.dtsi"
+
+/ {
+ model = "Synquacer Evaluation Board";
+ compatible = "socionext,synquacer-eval-board", "socionext,synquacer";
+};
diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
new file mode 100644
index 000000000000..4ca35c5f1d78
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
@@ -0,0 +1,28 @@
+## @file
+#
+# Device tree description of the Synquacer platform
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SynquacerDeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ SynquacerEvalBoard.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board
2017-09-08 18:23 ` [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board Ard Biesheuvel
@ 2017-09-11 16:37 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 16:37 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:12PM +0100, Ard Biesheuvel wrote:
> Add a device tree description of the Synquacer SoC, and expose it for
> the SynquacerEvalBoard platforms. This includes the menu option in the
> UEFI boot menu to switch between ACPI and DT.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 9 +
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 12 +
> Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi | 517 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts | 21 +
> Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf | 28 ++
> 5 files changed, 587 insertions(+)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index b2befd2480c4..92c1d3eb8283 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -489,3 +489,12 @@
> }
> MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
> +
> + #
> + # DT support
> + #
> + Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
> + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
> + <LibraryClasses>
> + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
> + }
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index 35742ad5a347..de97d3e56ded 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -1,3 +1,4 @@
> +
> #
> # Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> # Copyright (c) 2017, Linaro Limited. All rights reserved.
> @@ -190,6 +191,12 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
>
> + #
> + # DT support
> + #
> + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
> + INF RuleOverride = DTB Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
> +
> [FV.FVMAIN_COMPACT]
> FvAlignment = 8
> ERASE_POLARITY = 1
> @@ -342,3 +349,8 @@ READ_LOCK_STATUS = TRUE
> RAW ACPI |.acpi
> RAW ASL |.aml
> }
> +
> +[Rule.Common.USER_DEFINED.DTB]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW BIN |.dtb
> + }
> diff --git a/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
> new file mode 100644
> index 000000000000..8142bcc6adc8
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
> @@ -0,0 +1,517 @@
> +/** @file
> + * Copyright (c) 2017, Linaro Limited. All rights reserved.
> + *
> + * This program and the accompanying materials are licensed and made
> + * available under the terms and conditions of the BSD License which
> + * accompanies this distribution. The full text of the license may be
> + * found at http://opensource.org/licenses/bsd-license.php
> + *
> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> + * IMPLIED.
> + */
> +
> +#define GIC_SPI 0
> +#define GIC_PPI 1
> +
> +#define IRQ_TYPE_NONE 0
> +#define IRQ_TYPE_EDGE_RISING 1
> +#define IRQ_TYPE_EDGE_FALLING 2
> +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
> +#define IRQ_TYPE_LEVEL_HIGH 4
> +#define IRQ_TYPE_LEVEL_LOW 8
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
> +
> + aliases {
> + serial0 = &soc_uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU2: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU3: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU4: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x200>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU5: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x201>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU6: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x300>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU7: cpu@301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x301>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU8: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x400>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU9: cpu@401 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x401>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU10: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x500>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU11: cpu@501 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x501>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU12: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x600>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU13: cpu@601 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x601>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU14: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x700>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU15: cpu@701 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x701>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU16: cpu@800 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x800>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU17: cpu@801 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x801>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU18: cpu@900 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x900>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU19: cpu@901 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x901>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU20: cpu@a00 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0xa00>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU21: cpu@a01 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0xa01>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU22: cpu@b00 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0xb00>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> + CPU23: cpu@b01 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0xb01>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + core1 {
> + cpu = <&CPU1>;
> + };
> + };
> + cluster1 {
> + core0 {
> + cpu = <&CPU2>;
> + };
> + core1 {
> + cpu = <&CPU3>;
> + };
> + };
> + cluster2 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> + core1 {
> + cpu = <&CPU5>;
> + };
> + };
> + cluster3 {
> + core0 {
> + cpu = <&CPU6>;
> + };
> + core1 {
> + cpu = <&CPU7>;
> + };
> + };
> + cluster4 {
> + core0 {
> + cpu = <&CPU8>;
> + };
> + core1 {
> + cpu = <&CPU9>;
> + };
> + };
> + cluster5 {
> + core0 {
> + cpu = <&CPU10>;
> + };
> + core1 {
> + cpu = <&CPU11>;
> + };
> + };
> + cluster6 {
> + core0 {
> + cpu = <&CPU12>;
> + };
> + core1 {
> + cpu = <&CPU13>;
> + };
> + };
> + cluster7 {
> + core0 {
> + cpu = <&CPU14>;
> + };
> + core1 {
> + cpu = <&CPU15>;
> + };
> + };
> + cluster8 {
> + core0 {
> + cpu = <&CPU16>;
> + };
> + core1 {
> + cpu = <&CPU17>;
> + };
> + };
> + cluster9 {
> + core0 {
> + cpu = <&CPU18>;
> + };
> + core1 {
> + cpu = <&CPU19>;
> + };
> + };
> + cluster10 {
> + core0 {
> + cpu = <&CPU20>;
> + };
> + core1 {
> + cpu = <&CPU21>;
> + };
> + };
> + cluster11 {
> + core0 {
> + cpu = <&CPU22>;
> + };
> + core1 {
> + cpu = <&CPU23>;
> + };
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_SLEEP_0: cpu-sleep-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <300>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2000>;
> + local-timer-stop;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <400>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2500>;
> + local-timer-stop;
> + };
> + };
> +
> + gic: interrupt-controller@30000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x30000000 0x0 0x10000>, // GICD
> + <0x0 0x30400000 0x0 0x300000>, // GICR
> + <0x0 0x2c000000 0x0 0x2000>, // GICC
> + <0x0 0x2c010000 0x0 0x1000>, // GICH
> + <0x0 0x2c020000 0x0 0x2000>; // GICV
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +
> + its: gic-its@30020000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30020000 0x0 0x20000>;
> + #msi-cells = <1>;
> + msi-controller;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
> + };
> +
> + mmio-timer@2a810000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0 0x2a810000 0x0 0x10000>;
> + clock-frequency = <100000000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + frame@2a830000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x2a830000 0x0 0x10000>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + mailbox: mhu@45000000 {
> + compatible = "arm,mhu", "arm,primecell";
> + reg = <0x0 0x45000000 0x0 0x1000>;
> + interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; /* Non-Sec */
> + interrupt-names = "mhu_lpri_rx", "mhu_hpri_rx";
> + #mbox-cells = <1>;
> + clocks = <&clk_apb>;
> + clock-names = "apb_pclk";
> + };
> +
> + sram: sram@45200000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x45200000 0x0 0x200>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x45200000 0x200>;
> +
> + cpu_scp_hpri: scp-shmem@0 {
> + reg = <0x0 0x200>;
> + };
> + };
> +
> + scpi {
> + compatible = "arm,scpi";
> + mboxes = <&mailbox 1>;
> + shmem = <&cpu_scp_hpri>;
> + };
> +
> + clk_uart: refclk62500khz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <62500000>;
> + clock-output-names = "uartclk";
> + };
> +
> + clk_apb: refclk100mhz {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "apb_pclk";
> + };
> +
> + soc_uart0: uart@2a400000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0 0x2a400000 0x0 0x1000>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_uart &clk_apb>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + clk_netsec: refclk125mhz {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
> +
> + eth0: netsec@522D0000 {
> + compatible = "socionext,netsecv5";
> + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_netsec>;
> + phy-mode = "rgmii";
> + max-speed = <1000>;
> + max-frame-size = <9000>;
> + phy-handle = <ðphy0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + device_type = "ethernet-phy";
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> + };
> +
> + smmu: iommu@582c0000 {
> + compatible = "arm,mmu-500", "arm,smmu-v2";
> + reg = <0x0 0x582c0000 0x0 0x10000>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
> + #iommu-cells = <1>;
> + status = "disabled";
> + };
> +
> + pcie0: pcie@60000000 {
> + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> + device_type = "pci";
> + reg = <0x0 0x60000000 0x0 0x7f00000>;
> + bus-range = <0x0 0x7e>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
> + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
> + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
> +
> + #interrupt-cells = <0x1>;
> + interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +
> + /* Synquacer SoC supports ITS device ID 0 only */
> + msi-map-mask = <0x0>;
> + msi-map = <0x0 &its 0x0 0x1>;
> + dma-coherent;
> + };
> +
> + pcie1: pcie@70000000 {
> + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> + device_type = "pci";
> + reg = <0x0 0x70000000 0x0 0x7f00000>;
> + bus-range = <0x0 0x7e>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>,
> + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
> + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> +
> + #interrupt-cells = <0x1>;
> + interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
> +
> + /* Synquacer SoC supports ITS device ID 0 only */
> + msi-map-mask = <0x0>;
> + msi-map = <0x0 &its 0x0 0x1>;
> + dma-coherent;
> + };
> +};
> diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
> new file mode 100644
> index 000000000000..0e46d2979128
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
> @@ -0,0 +1,21 @@
> +/** @file
> + * Copyright (c) 2017, Linaro Limited. All rights reserved.
> + *
> + * This program and the accompanying materials are licensed and made
> + * available under the terms and conditions of the BSD License which
> + * accompanies this distribution. The full text of the license may be
> + * found at http://opensource.org/licenses/bsd-license.php
> + *
> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> + * IMPLIED.
> + */
> +
> +/dts-v1/;
> +
> +#include "Synquacer.dtsi"
> +
> +/ {
> + model = "Synquacer Evaluation Board";
> + compatible = "socionext,synquacer-eval-board", "socionext,synquacer";
> +};
> diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
> new file mode 100644
> index 000000000000..4ca35c5f1d78
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
> @@ -0,0 +1,28 @@
> +## @file
> +#
> +# Device tree description of the Synquacer platform
> +#
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = SynquacerDeviceTree
> + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + SynquacerEvalBoard.dts
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 12/14] Silicon/Synquacer: add NorFlashPlatformLib implementation
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (10 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 16:38 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 13/14] Silicon/Socionext: add driver for SPI NOR flash Ard Biesheuvel
2017-09-08 18:23 ` [PATCH edk2-platforms 14/14] Platform/Synquacer: incorporate NOR flash and variable drivers Ard Biesheuvel
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Add the platform glue for the NOR flash driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c | 60 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf | 38 +++++++++++++
2 files changed, 98 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
new file mode 100644
index 000000000000..0d9a81b61b73
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
@@ -0,0 +1,60 @@
+/** @file
+
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/NorFlashPlatformLib.h>
+
+#include <Platform/MemoryMap.h>
+
+STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
+ {
+ // Environment variable region
+ SYNQUACER_SPI_NOR_BASE, // device base
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase), // region base
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), // region size
+ SIZE_64KB, // block size
+ {
+ 0x3105BD7A, 0x82C3, 0x486F, { 0xB1, 0x03, 0x1E, 0x09, 0x54, 0xEC, 0x85, 0x75 }
+ }
+ },
+};
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
+ OUT UINT32 *Count
+ )
+{
+ if (NorFlashDevices == NULL ||
+ Count == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *Count = ARRAY_SIZE (mNorFlashDevices);
+ *NorFlashDevices = mNorFlashDevices;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
new file mode 100644
index 000000000000..bd84be0aebf8
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
@@ -0,0 +1,38 @@
+#/** @file
+#
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NorFlashSynquacerLib
+ FILE_GUID = 8279227C-C555-4D75-B439-D8A959635CDD
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NorFlashPlatformLib
+
+[Sources]
+ NorFlashSynquacer.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+ BaseLib
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 12/14] Silicon/Synquacer: add NorFlashPlatformLib implementation
2017-09-08 18:23 ` [PATCH edk2-platforms 12/14] Silicon/Synquacer: add NorFlashPlatformLib implementation Ard Biesheuvel
@ 2017-09-11 16:38 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 16:38 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:13PM +0100, Ard Biesheuvel wrote:
> Add the platform glue for the NOR flash driver.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c | 60 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf | 38 +++++++++++++
> 2 files changed, 98 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
> new file mode 100644
> index 000000000000..0d9a81b61b73
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
> @@ -0,0 +1,60 @@
> +/** @file
> +
> + Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + **/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <Library/BaseLib.h>
> +#include <Library/NorFlashPlatformLib.h>
> +
> +#include <Platform/MemoryMap.h>
> +
> +STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
> + {
> + // Environment variable region
> + SYNQUACER_SPI_NOR_BASE, // device base
> + FixedPcdGet32 (PcdFlashNvStorageVariableBase), // region base
> + FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
> + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
> + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), // region size
> + SIZE_64KB, // block size
> + {
> + 0x3105BD7A, 0x82C3, 0x486F, { 0xB1, 0x03, 0x1E, 0x09, 0x54, 0xEC, 0x85, 0x75 }
> + }
> + },
> +};
> +
> +EFI_STATUS
> +NorFlashPlatformInitialization (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> + OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
> + OUT UINT32 *Count
> + )
> +{
> + if (NorFlashDevices == NULL ||
> + Count == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *Count = ARRAY_SIZE (mNorFlashDevices);
> + *NorFlashDevices = mNorFlashDevices;
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
> new file mode 100644
> index 000000000000..bd84be0aebf8
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
> @@ -0,0 +1,38 @@
> +#/** @file
> +#
> +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
If you bump this:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> + BASE_NAME = NorFlashSynquacerLib
> + FILE_GUID = 8279227C-C555-4D75-B439-D8A959635CDD
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NorFlashPlatformLib
> +
> +[Sources]
> + NorFlashSynquacer.c
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> + BaseLib
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 13/14] Silicon/Socionext: add driver for SPI NOR flash
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (11 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 12/14] Silicon/Synquacer: add NorFlashPlatformLib implementation Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 19:13 ` Leif Lindholm
2017-09-08 18:23 ` [PATCH edk2-platforms 14/14] Platform/Synquacer: incorporate NOR flash and variable drivers Ard Biesheuvel
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
This imports the driver sources provided by Socionext for the FIP006
SPI NOR flash device found on Synquacer SoCs. It has been slightly
tweaked to bring it up to date with the changes made on the EDK2 side
since it was forked.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec | 31 +
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf | 78 ++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h | 242 ++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c | 136 ++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c | 1313 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h | 305 +++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c | 845 +++++++++++++
7 files changed, 2950 insertions(+)
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
new file mode 100644
index 000000000000..6c0ac807fd0b
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
@@ -0,0 +1,31 @@
+## @file
+# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
+#
+# Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = Fip006DxePkg
+ PACKAGE_GUID = ABC7870B-FE82-4DAD-8179-FEC5F5194FA0
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gFip006DxeTokenSpaceGuid = {0x4D45399E, 0x98F9, 0x4127, {0x8F, 0xB9,0xF8, 0xDE, 0x22, 0xA1, 0x09, 0x2C}}
+
+[PcdsFixedAtBuild]
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x0|UINT32|0x00000001
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0|UINT32|0x00000002
+ gFip006DxeTokenSpaceGuid.PcdN25qSlaveId|0x0|UINT8|0x00000003
+ gFip006DxeTokenSpaceGuid.PcdN25qBlockSize|256|UINT32|0x00000004
+ gFip006DxeTokenSpaceGuid.PcdN25qBlockCount|524288|UINT32|0x00000005
+
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
new file mode 100644
index 000000000000..5727d4d937c9
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
@@ -0,0 +1,78 @@
+## @file
+# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
+#
+# Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Fip006Dxe
+ FILE_GUID = 44F7D21F-C36F-4766-BC5B-C72E97E6897B
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 0.1
+ ENTRY_POINT = NorFlashInitialise
+
+[Sources]
+ NorFlashDxe.c
+ NorFlashBlockIoDxe.c
+ NorFlashFvbDxe.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ DxeServicesTableLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ NorFlashPlatformLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeLib
+ UefiRuntimeServicesTableLib
+
+[Guids]
+ gEfiAuthenticatedVariableGuid
+ gEfiEventVirtualAddressChangeGuid
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiDiskIoProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress
+
+[Depex]
+ #
+ # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty flash needs populating with default values
+ #
+ BEFORE gVariableRuntimeDxeFileGuid
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
new file mode 100644
index 000000000000..e515d967a1d7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
@@ -0,0 +1,242 @@
+/** @file
+ Socionext FIP006 Register List
+
+ Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __EFI_FIP006_REG_H__
+#define __EFI_FIP006_REG_H__
+
+#define FIP006_REG_MCTRL 0x00 // Module Control
+typedef union {
+ UINT32 Raw : 32;
+ struct {
+ BOOLEAN MEN : 1;
+ BOOLEAN CSEN : 1;
+#define MCTRL_CSEN_DIRECT 0
+#define MCTRL_CSEN_CS 1
+ BOOLEAN CDSS : 1;
+#define MCTRL_CDSS_IHCLK 0
+#define MCTRL_CDSS_IPCLK 1
+ BOOLEAN MES : 1;
+#define MCTRL_MES_READY 1
+ UINT8 : 4;
+ UINT8 : 8;
+ UINT8 : 8;
+ UINT8 : 8;
+ };
+} FIP006_MCTRL;
+
+#define FIP006_REG_PCC0 0x04 // Peripheral Communication Control 0
+#define FIP006_REG_PCC1 0x08 // Peripheral Communication Control 1
+#define FIP006_REG_PCC2 0x0C // Peripheral Communication Control 2
+#define FIP006_REG_PCC3 0x10 // Peripheral Communication Control 3
+typedef union {
+ UINT32 Raw : 32;
+ struct {
+ BOOLEAN CPHA : 1;
+ BOOLEAN CPOL : 1;
+ BOOLEAN ACES : 1;
+ BOOLEAN RTM : 1;
+ BOOLEAN SSPOL : 1;
+ UINT8 SS2CD : 2;
+ BOOLEAN SDIR : 1;
+#define PCC_SDIR_MS_BIT 0
+#define PCC_SDIR_LS_BIT 1
+ BOOLEAN SENDIAN : 1;
+#define PCC_SENDIAN_BIG 0
+#define PCC_SENDIAN_LITTLE 1
+ UINT8 CDRS : 7;
+ BOOLEAN SAFESYNC : 1;
+ UINT8 WRDSEL : 4;
+ UINT8 RDDSEL : 2;
+ UINT8 : 1;
+ UINT8 : 8;
+ } Reg;
+} FIP006_PCC;
+typedef FIP006_PCC FIP006_PCC0, FIP006_PCC1, FIP006_PCC2, FIP006_PCC3;
+
+#define FIP006_REG_TXF 0x14 // Tx Interrupt Flag
+#define TXF_TSSRS BIT6
+#define TXF_TFMTS BIT5
+#define TXF_TFLETS BIT4
+#define TXF_TFUS BIT3
+#define TXF_TFOS BIT2
+#define TXF_TFES BIT1
+#define TXF_TFFS BIT0
+
+#define FIP006_REG_TXE 0x18 // Tx Interrupt Enable
+#define TXE_TSSRE BIT6
+#define TXE_TFMTE BIT5
+#define TXE_TFLETE BIT4
+#define TXE_TFUE BIT3
+#define TXE_TFOE BIT2
+#define TXE_TFEE BIT1
+#define TXE_TFFE BIT0
+
+#define FIP006_REG_TXC 0x1C // Tx Interrupt Clear
+#define TXC_TSSRC BIT6
+#define TXC_TFMTC BIT5
+#define TXC_TFLETC BIT4
+#define TXC_TFUC BIT3
+#define TXC_TFOC BIT2
+#define TXC_TFEC BIT1
+#define TXC_TFFC BIT0
+
+#define FIP006_REG_RXF 0x20 // Rx Interrupt Flag
+#define RXF_RSSRS BIT6
+#define RXF_RFMTS BIT5
+#define RXF_RFLETS BIT4
+#define RXF_RFUS BIT3
+#define RXF_RFOS BIT2
+#define RXF_RFES BIT1
+#define RXF_RFFS BIT0
+
+#define FIP006_REG_RXE 0x24 // Rx Interrupt Enable
+#define RXE_RSSRE BIT6
+#define RXE_RFMTE BIT5
+#define RXE_RFLETE BIT4
+#define RXE_RFUE BIT3
+#define RXE_RFOE BIT2
+#define RXE_RFEE BIT1
+#define RXE_RFFE BIT0
+
+#define FIP006_REG_RXC 0x28 // Rx Interrupt Clear
+#define RXC_RSSRC BIT6
+#define RXC_RFMTC BIT5
+#define RXC_RFLETC BIT4
+#define RXC_RFUC BIT3
+#define RXC_RFOC BIT2
+#define RXC_RFEC BIT1
+#define RXC_RFFC BIT0
+
+#define FIP006_REG_FAULTF 0x2C // Error Interrupt Status
+#define FAULTF_DRCBSFS BIT4
+#define FAULTF_DWCBSFS BIT3
+#define FAULTF_PVFS BIT2
+#define FAULTF_WAFS BIT1
+#define FAULTF_UMAFS BIT0
+
+#define FIP006_REG_FAULTC 0x30 // Error Interrupt Clear
+#define FAULTC_DRCBSFC BIT4
+#define FAULTC_DWCBSFC BIT3
+#define FAULTC_PVFC BIT2
+#define FAULTC_WAFC BIT1
+#define FAULTC_UMAFC BIT0
+
+#define FIP006_REG_DM_CFG 0x34 // Direct Mode DMA Configuration
+#define DM_CFG_MSTARTEN BIT2
+#define DM_CFG_SSDC BIT1
+
+#define FIP006_REG_DM_DMA 0x35 // Direct Mode DMA Enable
+#define DM_DMA_TXDMAEN BIT1
+#define DM_DMA_RXDMAEN BIT0
+
+#define FIP006_REG_DM_START 0x38 // Direct Mode Start Transmission
+#define DM_START BIT0
+#define FIP006_REG_DM_STOP 0x39 // Direct Mode Stop Transmission
+#define DM_STOP BIT0
+
+#define FIP006_REG_DM_PSEL 0x3A // Direct Mode Peripheral Select
+#define DM_PSEL (BIT1 | BIT0)
+
+#define FIP006_REG_DM_TRP 0x3B // Direct Mode Transmission Protocol
+#define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define FIP006_REG_DM_BCC 0x3C // Direct Mode Byte Count Control
+#define FIP006_REG_DM_BCS 0x3E // Direct Mode Byte Count Status
+
+#define FIP006_REG_DM_STATUS 0x40 // Direct Mode Status
+#define DM_STATUS_TXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define DM_STATUS_RXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
+#define DM_STATUS_TXACTIVE BIT1
+#define DM_STATUS_RXACTIVE BIT0
+
+#define FIP006_REG_FIFO_CFG 0x4C // FIFO Configuration
+#define FIFO_CFG_TXFLSH BIT12
+#define FIFO_CFG_RXFLSH BIT11
+#define FIFO_CFG_TXCTRL BIT10
+#define FIFO_CFG_FWIDTH (BIT9 | BIT8)
+#define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4)
+#define FIFO_CFG_RXFTH (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define FIP006_REG_FIFO_TX 0x50 // 16 32-bit Tx FIFO
+#define FIP006_REG_FIFO_RX 0x90 // 16 32-bit Rx FIFO
+
+#define FIP006_REG_CS_CFG 0xD0 // Command Sequencer Configuration
+typedef union {
+ UINT32 Raw : 32;
+ struct {
+ BOOLEAN SRAM : 1;
+#define CS_CFG_SRAM_RO 0
+#define CS_CFG_SRAM_RW 1
+ UINT8 MBM : 2;
+#define CS_CFG_MBM_SINGLE 0
+#define CS_CFG_MBM_DUAL 1
+#define CS_CFG_MBM_QUAD 2
+ BOOLEAN SPICHNG : 1;
+ BOOLEAN BOOTEN : 1;
+ BOOLEAN BSEL : 1;
+ UINT8 : 2;
+ BOOLEAN SSEL0EN : 1;
+ BOOLEAN SSEL1EN : 1;
+ BOOLEAN SSEL2EN : 1;
+ BOOLEAN SSEL3EN : 1;
+ UINT8 : 4;
+ BOOLEAN MSEL : 4;
+ UINT8 : 4;
+ UINT8 : 8;
+ } Reg;
+} FIP006_CS_CFG;
+
+#define FIP006_REG_CS_ITIME 0xD4 // Command Sequencer Idle Timer
+typedef union {
+ UINT32 Raw : 32;
+ struct {
+ UINT16 ITIME : 16;
+ UINT16 : 16;
+ } Reg;
+} FIP006_CS_ITIME;
+#define FIP006_REG_CS_AEXT 0xD8 // Command Sequencer Address Extension
+typedef union {
+ UINT32 Raw : 32;
+ struct {
+ UINT16 : 13;
+ UINT32 AEXT : 19;
+ } Reg;
+} FIP006_CS_AEXT;
+
+#define FIP006_REG_CS_RD 0xDC // Command Sequencer Read Control
+#define CS_RD_DEPTH 8
+#define FIP006_REG_CS_WR 0xEC // Command Sequencer Write Control
+#define CS_WR_DEPTH 8
+typedef union {
+ UINT16 Raw : 16;
+ struct {
+ BOOLEAN DEC : 1;
+ UINT8 TRP : 2;
+ BOOLEAN CONT : 1;
+ UINT8 : 4;
+ union {
+ UINT8 Data : 8;
+ struct {
+ UINT8 Data : 3;
+ UINT8 : 5;
+ } Cmd;
+ } Payload;
+ } Reg;
+} FIP006_CS_CMD;
+typedef FIP006_CS_CMD FIP006_CS_RD, FIP006_CS_WR;
+
+#define FIP006_REG_MID 0xFC // Command Sequencer Module ID
+typedef UINT32 FIP006_MID;
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
new file mode 100644
index 000000000000..b325d1721aa4
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
@@ -0,0 +1,136 @@
+/** @file NorFlashBlockIoDxe.c
+
+ Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "NorFlashDxe.h"
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n",
+ This->Media->MediaId));
+
+ return NorFlashReset (Instance);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+
+ if (This == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+ Media = This->Media;
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes "
+ "(%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if (!Media) {
+ Status = EFI_INVALID_PARAMETER;
+ } else if (!Media->MediaPresent) {
+ Status = EFI_NO_MEDIA;
+ } else if (Media->MediaId != MediaId) {
+ Status = EFI_MEDIA_CHANGED;
+ } else if ((Media->IoAlign > 2) &&
+ (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ Status = NorFlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes "
+ "(%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if( !This->Media->MediaPresent ) {
+ Status = EFI_NO_MEDIA;
+ } else if( This->Media->MediaId != MediaId ) {
+ Status = EFI_MEDIA_CHANGED;
+ } else if( This->Media->ReadOnly ) {
+ Status = EFI_WRITE_PROTECTED;
+ } else {
+ Status = NorFlashWriteBlocks (Instance,Lba,BufferSizeInBytes,Buffer);
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+ // No Flush required for the NOR Flash driver
+ // because cache operations are not permitted.
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashBlockIoFlushBlocks: Function NOT IMPLEMENTED (not required).\n"));
+
+ // Nothing to do so just return without error
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
new file mode 100644
index 000000000000..ad004ddf03b3
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
@@ -0,0 +1,1313 @@
+/** @file NorFlashDxe.c
+
+ Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
+
+//
+// Global variable declarations
+//
+STATIC NOR_FLASH_INSTANCE **mNorFlashInstances;
+STATIC UINT32 mNorFlashDeviceCount;
+
+STATIC CONST UINT16 mFip006NullCmdSeq[] = {
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1),
+ CSDC (0x07, 0, CSDC_TRP_MBM, 1)
+};
+
+STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = {
+ // Register Operations
+ { 0x05, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0x01, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0xE8, TRUE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0x70, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0xB5, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0x85, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0x65, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ // Read Operations
+ { 0x13, TRUE, TRUE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ // Write Operations
+ { 0x02, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+ { 0x32, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_QUAD, CSDC_TRP_SINGLE },
+ // Erase Operations
+ { 0xD8, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
+};
+
+STATIC
+EFI_STATUS
+NorFlashSetHostCSDC (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN BOOLEAN ReadWrite,
+ IN CONST UINT16 CSDC[8]
+ )
+{
+ EFI_PHYSICAL_ADDRESS Dst;
+ UINTN Index;
+
+ Dst = Instance->HostRegisterBaseAddress
+ + (ReadWrite ? FIP006_REG_CS_WR : FIP006_REG_CS_RD);
+ for (Index = 0; Index < 8; Index++) {
+ MmioWrite16 (Dst + (Index << 1), CSDC[Index]);
+ }
+ return EFI_SUCCESS;
+}
+
+STATIC
+CONST CSDC_DEFINITION *
+NorFlashGetCmdDef (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINT8 Code
+ )
+{
+ CONST CSDC_DEFINITION *Cmd;
+ UINTN Index;
+
+ Cmd = NULL;
+ for (Index = 0; Index < Instance->CmdTableSize; Index++) {
+ if (Code == Instance->CmdTable[Index].Code) {
+ Cmd = &Instance->CmdTable[Index];
+ break;
+ }
+ }
+ return Cmd;
+}
+
+STATIC
+EFI_STATUS
+GenCSDC (
+ IN UINT8 Cmd,
+ IN BOOLEAN AddrAccess,
+ IN BOOLEAN AddrMode4Byte,
+ IN BOOLEAN HighZ,
+ IN UINT8 TransferMode,
+ OUT UINT16 CmdSeq[8]
+ )
+{
+ UINTN Index;
+
+ if (!CmdSeq) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Index = 0;
+ CopyMem (CmdSeq, mFip006NullCmdSeq, 8 * sizeof (UINT16));
+
+ CmdSeq[Index++] = CSDC (Cmd, 0, TransferMode, 0);
+ if (AddrAccess) {
+ if (AddrMode4Byte) {
+ CmdSeq[Index++] = CSDC (0x03, 0, TransferMode, 1);
+ }
+ CmdSeq[Index++] = CSDC (0x02, 0, TransferMode, 1);
+ CmdSeq[Index++] = CSDC (0x01, 0, TransferMode, 1);
+ CmdSeq[Index++] = CSDC (0x00, 0, TransferMode, 1);
+ }
+ if (HighZ) {
+ CmdSeq[Index++] = CSDC (0x04, 0, TransferMode, 1);
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+NorFlashSetHostCommand (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINT8 Code
+ )
+{
+ CONST CSDC_DEFINITION *Cmd;
+ UINT16 CSDC[8];
+
+ Cmd = NorFlashGetCmdDef(Instance, Code);
+ if (Cmd == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ GenCSDC (
+ Cmd->Code,
+ Cmd->AddrAccess,
+ Cmd->AddrMode4Byte,
+ Cmd->HighZ,
+ Cmd->CsdcTrp,
+ CSDC
+ );
+ NorFlashSetHostCSDC (Instance, Cmd->ReadWrite, CSDC);
+ return EFI_SUCCESS;
+}
+
+STATIC
+UINT8
+NorFlashReadStatusRegister (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN SR_Address
+ )
+{
+ UINT8 StatusRegister;
+
+ NorFlashSetHostCommand (Instance, 0x05);
+ StatusRegister = NOR_FLASH_READ_BYTE (Instance, 0);
+ NorFlashSetHostCommand (Instance, 0x13);
+ return StatusRegister;
+}
+
+STATIC
+EFI_STATUS
+NorFlashWaitProgramErase (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "NorFlashWaitProgramErase()\n"));
+
+ NorFlashSetHostCommand (Instance, 0x70);
+ while ((NOR_FLASH_READ_BYTE (Instance, 0) & BIT7) == 0);
+ NorFlashSetHostCommand (Instance, 0x13);
+ return EFI_SUCCESS;
+}
+
+// TODO: implement lock checking
+STATIC
+BOOLEAN
+NorFlashBlockIsLocked (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ )
+{
+ return FALSE;
+}
+
+// TODO: implement sector unlocking
+STATIC
+EFI_STATUS
+NorFlashUnlockSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ )
+{
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+NorFlashUnlockSingleBlockIfNecessary (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ if (NorFlashBlockIsLocked (Instance, BlockAddress) == TRUE) {
+ Status = NorFlashUnlockSingleBlock (Instance, BlockAddress);
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+NorFlashEnableWrite (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ UINT8 StatusRegister;
+ UINTN Retry;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashEnableWrite()\n"));
+
+ Status = EFI_DEVICE_ERROR;
+ Retry = 100;
+
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+ while (Retry > 0 && EFI_ERROR (Status)) {
+ NOR_FLASH_WRITE_BYTE (Instance, 0, 0x06);
+ StatusRegister = NorFlashReadStatusRegister (Instance, 0);
+ Status = (StatusRegister & BIT1) ? EFI_SUCCESS : EFI_DEVICE_ERROR;
+ Retry--;
+ }
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+NorFlashDisableWrite (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ UINT8 StatusRegister;
+ UINTN Retry;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashDisableWrite()\n"));
+
+ Status = EFI_DEVICE_ERROR;
+ Retry = 10;
+
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+ while (Retry > 0 && EFI_ERROR (Status)) {
+ NOR_FLASH_WRITE_BYTE (Instance, 0, 0x04);
+ StatusRegister = NorFlashReadStatusRegister (Instance, 0);
+ Status = (StatusRegister & BIT1) ? EFI_DEVICE_ERROR : EFI_SUCCESS;
+ Retry--;
+ }
+ return Status;
+}
+
+/**
+ * The following function presumes that the block has already been unlocked.
+ **/
+STATIC
+EFI_STATUS
+NorFlashEraseSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ )
+{
+ UINT16 Sector;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashEraseSingleBlock(BlockAddress=0x%08x)\n",
+ BlockAddress));
+
+ Sector = (BlockAddress - Instance->RegionBaseAddress) /
+ Instance->Media.BlockSize;
+ Sector += Instance->OffsetLba;
+
+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Erase a block
+ NorFlashSetHostCommand (Instance, 0xD8);
+ *(UINT16*) Instance->RegionBaseAddress = SwapBytes16 (Sector);
+ NorFlashWaitProgramErase (Instance);
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+
+ NorFlashDisableWrite (Instance);
+ return EFI_SUCCESS;
+}
+
+/**
+ * This function unlock and erase an entire NOR Flash block.
+ **/
+EFI_STATUS
+NorFlashUnlockAndEraseSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_TPL OriginalTPL;
+
+ if (!EfiAtRuntime ()) {
+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ } else {
+ // This initialization is only to prevent the compiler to complain about the
+ // use of uninitialized variables
+ OriginalTPL = TPL_HIGH_LEVEL;
+ }
+
+ Index = 0;
+ // The block erase might fail a first time (SW bug ?). Retry it ...
+ do {
+ // Unlock the block if we have to
+ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
+ Index++;
+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
+
+ if (Index == NOR_FLASH_ERASE_RETRY) {
+ DEBUG ((DEBUG_ERROR,
+ "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n",
+ BlockAddress,Index));
+ }
+
+ if (!EfiAtRuntime ()) {
+ // Interruptions can resume.
+ gBS->RestoreTPL (OriginalTPL);
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+NorFlashWriteSingleWord (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN WordAddress,
+ IN UINT32 WriteData
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashWriteSingleWord(WordAddress=0x%08x, WriteData=0x%08x)\n",
+ WordAddress, WriteData));
+
+ Status = EFI_SUCCESS;
+
+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
+ return EFI_DEVICE_ERROR;
+ }
+ NorFlashSetHostCommand (Instance, 0x02);
+ *(UINT32*) WordAddress = WriteData;
+ NorFlashWaitProgramErase (Instance);
+
+ NorFlashDisableWrite (Instance);
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+NorFlashWriteFullBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINT32 *DataBuffer,
+ IN UINT32 BlockSizeInWords
+ )
+{
+ EFI_STATUS Status;
+ UINTN WordAddress;
+ UINT32 WordIndex;
+ UINTN BlockAddress;
+ EFI_TPL OriginalTPL;
+
+ Status = EFI_SUCCESS;
+
+ // Get the physical address of the block
+ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
+ BlockSizeInWords * 4);
+
+ // Start writing from the first address at the start of the block
+ WordAddress = BlockAddress;
+
+ if (!EfiAtRuntime ()) {
+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ } else {
+ // This initialization is only to prevent the compiler to complain about the
+ // use of uninitialized variables
+ OriginalTPL = TPL_HIGH_LEVEL;
+ }
+
+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n",
+ BlockAddress));
+ goto EXIT;
+ }
+
+ for (WordIndex=0;
+ WordIndex < BlockSizeInWords;
+ WordIndex++, DataBuffer++, WordAddress += 4) {
+ Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ }
+
+EXIT:
+ if (!EfiAtRuntime ()) {
+ // Interruptions can resume.
+ gBS->RestoreTPL (OriginalTPL);
+ }
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n",
+ WordAddress, Status));
+ }
+ return Status;
+}
+
+EFI_STATUS
+NorFlashWriteBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ UINT32 *pWriteBuffer;
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_LBA CurrentBlock;
+ UINT32 BlockSizeInWords;
+ UINT32 NumBlocks;
+ UINT32 BlockCount;
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(Instance->Media.ReadOnly == TRUE) {
+ return EFI_WRITE_PROTECTED;
+ }
+
+ // We must have some bytes to read
+ DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n",
+ BufferSizeInBytes));
+ if(BufferSizeInBytes == 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n",
+ Instance->Media.BlockSize));
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks,
+ Instance->Media.LastBlock, Lba));
+
+ if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BlockSizeInWords = Instance->Media.BlockSize / 4;
+
+ // Because the target *Buffer is a pointer to VOID, we must put
+ // all the data into a pointer to a proper data type, so use *ReadBuffer
+ pWriteBuffer = (UINT32 *)Buffer;
+
+ CurrentBlock = Lba;
+ for (BlockCount = 0;
+ BlockCount < NumBlocks;
+ BlockCount++, CurrentBlock++, pWriteBuffer += BlockSizeInWords) {
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n",
+ (UINTN)CurrentBlock));
+
+ Status = NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffer,
+ BlockSizeInWords);
+
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n", Status));
+ return Status;
+}
+
+EFI_STATUS
+NorFlashReadBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ UINT32 NumBlocks;
+ UINTN StartAddress;
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n",
+ BufferSizeInBytes, Instance->Media.BlockSize, Instance->Media.LastBlock,
+ Lba));
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Return if we have not any byte to read
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ // The size of the buffer must be a multiple of the block size
+ if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // All blocks must be within the device
+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashReadBlocks: ERROR - Read will exceed last block\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the address to start reading from
+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
+ Instance->Media.BlockSize);
+
+ // Put the device into Read Array mode
+ NorFlashSetHostCommand (Instance, 0x13);
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+
+ // Readout the data
+ CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ UINTN StartAddress;
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Return if we have not any byte to read
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if (((Lba * Instance->Media.BlockSize) + Offset + BufferSizeInBytes) >
+ Instance->Size) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashRead: ERROR - Read will exceed device size.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the address to start reading from
+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
+ Instance->Media.BlockSize);
+
+ // Put the device into Read Array mode
+ NorFlashSetHostCommand (Instance, 0x13);
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+
+ // Readout the data
+ CopyMem (Buffer, (UINTN *)(StartAddress + Offset), BufferSizeInBytes);
+
+ return EFI_SUCCESS;
+}
+
+/*
+ Write a full or portion of a block. It must not span block boundaries;
+ that is, Offset + *NumBytes <= Instance->Media.BlockSize.
+*/
+EFI_STATUS
+NorFlashWriteSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS TempStatus;
+ UINT32 Tmp;
+ UINT32 TmpBuf;
+ UINT32 WordToWrite;
+ UINT32 Mask;
+ BOOLEAN DoErase;
+ UINTN BytesToWrite;
+ UINTN CurOffset;
+ UINTN WordAddr;
+ UINTN BlockSize;
+ UINTN BlockAddress;
+ UINTN PrevBlockAddress;
+
+ PrevBlockAddress = 0;
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize(Instance);
+ }
+
+ DEBUG ((DEBUG_BLKIO,
+ "NorFlashWriteSingleBlock(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ Lba, Offset, *NumBytes, Buffer));
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWriteSingleBlock: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // The write must not span block boundaries.
+ // We need to check each variable individually because adding two large
+ // values together overflows.
+ if (Offset >= BlockSize ||
+ *NumBytes > BlockSize ||
+ (Offset + *NumBytes) > BlockSize) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
+ Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to write
+ if (*NumBytes == 0) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
+ Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Pick 128bytes as a good start for word operations as opposed to erasing the
+ // block and writing the data regardless if an erase is really needed.
+ // It looks like most individual NV variable writes are smaller than 128bytes.
+ if (*NumBytes <= 128) {
+ // Check to see if we need to erase before programming the data into NOR.
+ // If the destination bits are only changing from 1s to 0s we can just write.
+ // After a block is erased all bits in the block is set to 1.
+ // If any byte requires us to erase we just give up and rewrite all of it.
+ DoErase = FALSE;
+ BytesToWrite = *NumBytes;
+ CurOffset = Offset;
+
+ while (BytesToWrite > 0) {
+ // Read full word from NOR, splice as required. A word is the smallest
+ // unit we can write.
+ TempStatus = NorFlashRead (Instance, Lba, CurOffset & ~(0x3), sizeof(Tmp),
+ &Tmp);
+ if (EFI_ERROR (TempStatus)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Physical address of word in NOR to write.
+ WordAddr = (CurOffset & ~(0x3)) +
+ GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
+ BlockSize);
+
+ // The word of data that is to be written.
+ TmpBuf = *((UINT32*)(Buffer + (*NumBytes - BytesToWrite)));
+
+ // First do word aligned chunks.
+ if ((CurOffset & 0x3) == 0) {
+ if (BytesToWrite >= 4) {
+ // Is the destination still in 'erased' state?
+ if (~Tmp != 0) {
+ // Check to see if we are only changing bits to zero.
+ if ((Tmp ^ TmpBuf) & TmpBuf) {
+ DoErase = TRUE;
+ break;
+ }
+ }
+ // Write this word to NOR
+ WordToWrite = TmpBuf;
+ CurOffset += sizeof(TmpBuf);
+ BytesToWrite -= sizeof(TmpBuf);
+ } else {
+ // BytesToWrite < 4. Do small writes and left-overs
+ Mask = ~((~0) << (BytesToWrite * 8));
+ // Mask out the bytes we want.
+ TmpBuf &= Mask;
+ // Is the destination still in 'erased' state?
+ if ((Tmp & Mask) != Mask) {
+ // Check to see if we are only changing bits to zero.
+ if ((Tmp ^ TmpBuf) & TmpBuf) {
+ DoErase = TRUE;
+ break;
+ }
+ }
+ // Merge old and new data. Write merged word to NOR
+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
+ CurOffset += BytesToWrite;
+ BytesToWrite = 0;
+ }
+ } else {
+ // Do multiple words, but starting unaligned.
+ if (BytesToWrite > (4 - (CurOffset & 0x3))) {
+ Mask = ((~0) << ((CurOffset & 0x3) * 8));
+ // Mask out the bytes we want.
+ TmpBuf &= Mask;
+ // Is the destination still in 'erased' state?
+ if ((Tmp & Mask) != Mask) {
+ // Check to see if we are only changing bits to zero.
+ if ((Tmp ^ TmpBuf) & TmpBuf) {
+ DoErase = TRUE;
+ break;
+ }
+ }
+ // Merge old and new data. Write merged word to NOR
+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
+ BytesToWrite -= (4 - (CurOffset & 0x3));
+ CurOffset += (4 - (CurOffset & 0x3));
+ } else {
+ // Unaligned and fits in one word.
+ Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8);
+ // Mask out the bytes we want.
+ TmpBuf = (TmpBuf << ((CurOffset & 0x3) * 8)) & Mask;
+ // Is the destination still in 'erased' state?
+ if ((Tmp & Mask) != Mask) {
+ // Check to see if we are only changing bits to zero.
+ if ((Tmp ^ TmpBuf) & TmpBuf) {
+ DoErase = TRUE;
+ break;
+ }
+ }
+ // Merge old and new data. Write merged word to NOR
+ WordToWrite = (Tmp & ~Mask) | TmpBuf;
+ CurOffset += BytesToWrite;
+ BytesToWrite = 0;
+ }
+ }
+
+ //
+ // Write the word to NOR.
+ //
+
+ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
+ BlockSize);
+ if (BlockAddress != PrevBlockAddress) {
+ TempStatus = NorFlashUnlockSingleBlockIfNecessary (Instance,
+ BlockAddress);
+ if (EFI_ERROR (TempStatus)) {
+ return EFI_DEVICE_ERROR;
+ }
+ PrevBlockAddress = BlockAddress;
+ }
+ TempStatus = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite);
+ if (EFI_ERROR (TempStatus)) {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ // Exit if we got here and could write all the data. Otherwise do the
+ // Erase-Write cycle.
+ if (!DoErase) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ // Check we did get some memory. Buffer is BlockSize.
+ if (Instance->ShadowBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Read NOR Flash data into shadow buffer
+ TempStatus = NorFlashReadBlocks (Instance, Lba, BlockSize,
+ Instance->ShadowBuffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Put the data at the appropriate location inside the buffer area
+ CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
+
+ // Write the modified buffer back to the NorFlash
+ TempStatus = NorFlashWriteBlocks (Instance, Lba, BlockSize,
+ Instance->ShadowBuffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ Although DiskIoDxe will automatically install the DiskIO protocol whenever
+ we install the BlockIO protocol, its implementation is sub-optimal as it reads
+ and writes entire blocks using the BlockIO protocol. In fact we can access
+ NOR flash with a finer granularity than that, so we can improve performance
+ by directly producing the DiskIO protocol.
+*/
+
+/**
+ Read BufferSize bytes from Offset into Buffer.
+
+ @param This Protocol instance pointer.
+ @param MediaId Id of the media, changes every time the media is
+ replaced.
+ @param Offset The starting byte offset to read from
+ @param BufferSize Size of Buffer
+ @param Buffer Buffer containing read data
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing
+ the read.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_INVALID_PARAMETER The read request contains device addresses that
+ are not valid for the device.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NorFlashDiskIoReadDisk (
+ IN EFI_DISK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 DiskOffset,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ UINT32 BlockSize;
+ UINT32 BlockOffset;
+ EFI_LBA Lba;
+
+ Instance = INSTANCE_FROM_DISKIO_THIS(This);
+
+ if (MediaId != Instance->Media.MediaId) {
+ return EFI_MEDIA_CHANGED;
+ }
+
+ BlockSize = Instance->Media.BlockSize;
+ Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
+
+ return NorFlashRead (Instance, Lba, BlockOffset, BufferSize, Buffer);
+}
+
+/**
+ Writes a specified number of bytes to a device.
+
+ @param This Indicates a pointer to the calling context.
+ @param MediaId ID of the medium to be written.
+ @param Offset The starting byte offset on the logical block I/O device to
+ write.
+ @param BufferSize The size in bytes of Buffer. The number of bytes to write
+ to the device.
+ @param Buffer A pointer to the buffer containing the data to be written.
+
+ @retval EFI_SUCCESS The data was written correctly to the device.
+ @retval EFI_WRITE_PROTECTED The device can not be written to.
+ @retval EFI_DEVICE_ERROR The device reported an error while performing
+ the write.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
+ @retval EFI_INVALID_PARAMETER The write request contains device addresses that
+ are not valid for the device.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NorFlashDiskIoWriteDisk (
+ IN EFI_DISK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN UINT64 DiskOffset,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ UINT32 BlockSize;
+ UINT32 BlockOffset;
+ EFI_LBA Lba;
+ UINTN RemainingBytes;
+ UINTN WriteSize;
+ EFI_STATUS Status;
+
+ Instance = INSTANCE_FROM_DISKIO_THIS(This);
+
+ if (MediaId != Instance->Media.MediaId) {
+ return EFI_MEDIA_CHANGED;
+ }
+
+ BlockSize = Instance->Media.BlockSize;
+ Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
+
+ RemainingBytes = BufferSize;
+
+ // Write either all the remaining bytes, or the number of bytes that bring
+ // us up to a block boundary, whichever is less.
+ // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next
+ // block boundary (even if it is already on one).
+ WriteSize = MIN (RemainingBytes,
+ ((DiskOffset | (BlockSize - 1)) + 1) - DiskOffset);
+
+ do {
+ if (WriteSize == BlockSize) {
+ // Write a full block
+ Status = NorFlashWriteFullBlock (Instance, Lba, Buffer,
+ BlockSize / sizeof (UINT32));
+ } else {
+ // Write a partial block
+ Status = NorFlashWriteSingleBlock (Instance, Lba, BlockOffset, &WriteSize,
+ Buffer);
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ // Now continue writing either all the remaining bytes or single blocks.
+ RemainingBytes -= WriteSize;
+ Buffer = (UINT8 *) Buffer + WriteSize;
+ Lba++;
+ BlockOffset = 0;
+ WriteSize = MIN (RemainingBytes, BlockSize);
+ } while (RemainingBytes);
+
+ return Status;
+}
+
+STATIC CONST NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
+ NOR_FLASH_SIGNATURE, // Signature
+ NULL, // Handle ... NEED TO BE FILLED
+
+ FALSE, // Initialized
+ NULL, // Initialize
+
+ 0, // HostRegisterBaseAddress ... NEED TO BE FILLED
+ 0, // DeviceBaseAddress ... NEED TO BE FILLED
+ 0, // RegionBaseAddress ... NEED TO BE FILLED
+ 0, // Size ... NEED TO BE FILLED
+ 0, // StartLba
+ 0, // OffsetLba
+
+ {
+ EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
+ NULL, // Media ... NEED TO BE FILLED
+ NorFlashBlockIoReset, // Reset;
+ NorFlashBlockIoReadBlocks, // ReadBlocks
+ NorFlashBlockIoWriteBlocks, // WriteBlocks
+ NorFlashBlockIoFlushBlocks // FlushBlocks
+ }, // BlockIoProtocol
+
+ {
+ 0, // MediaId ... NEED TO BE FILLED
+ FALSE, // RemovableMedia
+ TRUE, // MediaPresent
+ FALSE, // LogicalPartition
+ FALSE, // ReadOnly
+ FALSE, // WriteCaching;
+ 0, // BlockSize ... NEED TO BE FILLED
+ 4, // IoAlign
+ 0, // LastBlock ... NEED TO BE FILLED
+ 0, // LowestAlignedLba
+ 1, // LogicalBlocksPerPhysicalBlock
+ }, //Media;
+
+ {
+ EFI_DISK_IO_PROTOCOL_REVISION, // Revision
+ NorFlashDiskIoReadDisk, // ReadDisk
+ NorFlashDiskIoWriteDisk // WriteDisk
+ },
+
+ FALSE, // SupportFvb ... NEED TO BE FILLED
+ {
+ FvbGetAttributes, // GetAttributes
+ FvbSetAttributes, // SetAttributes
+ FvbGetPhysicalAddress, // GetPhysicalAddress
+ FvbGetBlockSize, // GetBlockSize
+ FvbRead, // Read
+ FvbWrite, // Write
+ FvbEraseBlocks, // EraseBlocks
+ NULL, //ParentHandle
+ }, // FvbProtoccol;
+
+ NULL, // ShadowBuffer
+ {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)sizeof(VENDOR_DEVICE_PATH),
+ (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } },
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
+ } // DevicePath
+};
+
+STATIC
+EFI_STATUS
+NorFlashCreateInstance (
+ IN UINTN HostRegisterBase,
+ IN UINTN NorFlashDeviceBase,
+ IN UINTN NorFlashRegionBase,
+ IN UINTN NorFlashSize,
+ IN UINT32 MediaId,
+ IN UINT32 BlockSize,
+ IN BOOLEAN SupportFvb,
+ IN CONST GUID *NorFlashGuid,
+ IN CONST CSDC_DEFINITION *CommandTable,
+ IN UINTN CommandTableSize,
+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE* Instance;
+
+ ASSERT(NorFlashInstance != NULL);
+
+ Instance = AllocateRuntimeCopyPool (sizeof mNorFlashInstanceTemplate,
+ &mNorFlashInstanceTemplate);
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->HostRegisterBaseAddress = HostRegisterBase;
+ Instance->DeviceBaseAddress = NorFlashDeviceBase;
+ Instance->RegionBaseAddress = NorFlashRegionBase;
+ Instance->Size = NorFlashSize;
+
+ Instance->BlockIoProtocol.Media = &Instance->Media;
+ Instance->Media.MediaId = MediaId;
+ Instance->Media.BlockSize = BlockSize;
+ Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
+ Instance->OffsetLba = (NorFlashRegionBase - NorFlashDeviceBase) / BlockSize;
+
+ CopyGuid (&Instance->DevicePath.Vendor.Guid, NorFlashGuid);
+
+ Instance->CmdTable = CommandTable;
+ Instance->CmdTableSize = CommandTableSize;
+
+ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);;
+ if (Instance->ShadowBuffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ NorFlashReset (Instance);
+ if (SupportFvb) {
+ Instance->SupportFvb = TRUE;
+ Instance->Initialize = NorFlashFvbInitialize;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance);
+ return Status;
+ }
+ } else {
+ Instance->Initialized = TRUE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ &gEfiDiskIoProtocolGuid, &Instance->DiskIoProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance);
+ return Status;
+ }
+ }
+
+ *NorFlashInstance = Instance;
+ return Status;
+}
+
+EFI_STATUS
+NorFlashReset (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ FIP006_CS_CFG CsCfg;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashReset()\n"));
+ NOR_FLASH_GET_HOST_REG(Instance, CS_CFG, CsCfg);
+ CsCfg.Reg.MBM = CS_CFG_MBM_SINGLE;
+ CsCfg.Reg.SRAM = CS_CFG_SRAM_RW;
+ NOR_FLASH_SET_HOST_REG(Instance, CS_CFG, CsCfg);
+ NorFlashSetHostCommand (Instance, 0x13);
+ NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
+ return EFI_SUCCESS;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+STATIC
+VOID
+EFIAPI
+NorFlashVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->HostRegisterBaseAddress);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
+
+ // Convert BlockIo protocol
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
+
+ // Convert Fvb
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
+ EfiConvertPointer (0x0,
+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
+
+ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer);
+ }
+
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->CmdTable);
+ }
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashInitialise (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS HostRegisterBaseAddress;
+ UINT32 Index;
+ NOR_FLASH_DESCRIPTION* NorFlashDevices;
+ BOOLEAN ContainVariableStorage;
+
+ // Register HSSPI FIP006 register region
+ HostRegisterBaseAddress = PcdGet32 (PcdFip006DxeRegBaseAddress);
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ HostRegisterBaseAddress, SIZE_4KB,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gDS->SetMemorySpaceAttributes (
+ HostRegisterBaseAddress, SIZE_4KB,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NorFlashPlatformInitialization ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashInitialise: Fail to initialize Nor Flash devices\n"));
+ return Status;
+ }
+
+ // Initialize NOR flash instances
+ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n"));
+ return Status;
+ }
+
+ if (mNorFlashDeviceCount > 1) {
+ DEBUG ((DEBUG_WARN, "%a: device count exceeds 1\n", __FUNCTION__));
+ DEBUG ((DEBUG_WARN, "%a: use only first device\n", __FUNCTION__));
+ mNorFlashDeviceCount = 1;
+ }
+ mNorFlashInstances = AllocateRuntimePool (sizeof(NOR_FLASH_INSTANCE*) *
+ mNorFlashDeviceCount);
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ // Check if this NOR Flash device contain the variable storage region
+ ContainVariableStorage =
+ (NorFlashDevices[Index].RegionBaseAddress <=
+ PcdGet32 (PcdFlashNvStorageVariableBase)) &&
+ (PcdGet32 (PcdFlashNvStorageVariableBase) +
+ PcdGet32 (PcdFlashNvStorageVariableSize) <=
+ NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
+
+ Status = NorFlashCreateInstance (
+ HostRegisterBaseAddress,
+ NorFlashDevices[Index].DeviceBaseAddress,
+ NorFlashDevices[Index].RegionBaseAddress,
+ NorFlashDevices[Index].Size,
+ Index,
+ NorFlashDevices[Index].BlockSize,
+ ContainVariableStorage,
+ &NorFlashDevices[Index].Guid,
+ mN25qCSDCDefTable,
+ ARRAY_SIZE (mN25qCSDCDefTable),
+ &mNorFlashInstances[Index]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",
+ Index));
+ }
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
+ NorFlashVirtualNotifyEvent, NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mNorFlashVirtualAddrChangeEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
new file mode 100644
index 000000000000..ca82bda6dfb7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
@@ -0,0 +1,305 @@
+/** @file NorFlashDxe.h
+
+ Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_DXE_H__
+#define __NOR_FLASH_DXE_H__
+
+
+#include <Base.h>
+#include <PiDxe.h>
+
+#include <Guid/EventGroup.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/DiskIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NorFlashPlatformLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/DxeServicesTableLib.h>
+
+#include "Fip006Reg.h"
+
+#define NOR_FLASH_ERASE_RETRY 10
+
+#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
+
+#define NOR_FLASH_READ_BYTE(Instance, Addr) \
+ (((UINT8*) Instance->RegionBaseAddress + Addr)[0])
+
+#define NOR_FLASH_WRITE_BYTE(Instance, Addr, Src) \
+ do { \
+ ((UINT8*) Instance->RegionBaseAddress + Addr)[0] = Src; \
+ } while (0)
+
+#define NOR_FLASH_GET_HOST_REG(Instance, Reg, Dst) \
+ do { \
+ Dst.Raw = MmioRead32(Instance->HostRegisterBaseAddress + FIP006_REG_##Reg); \
+ } while (0)
+
+#define NOR_FLASH_SET_HOST_REG(Instance, Reg, Src) \
+ do { \
+ MmioWrite32 (Instance->HostRegisterBaseAddress + FIP006_REG_##Reg, Src.Raw); \
+ } while (0)
+
+#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
+#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
+#define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, NOR_FLASH_SIGNATURE)
+
+#define CSDC(Data, Cont, Trp, Dec) \
+ ((Data << 8) | (Cont << 3) | (Trp << 1) | Dec)
+#define CSDC_TRP_MBM 0
+#define CSDC_TRP_DUAL 1
+#define CSDC_TRP_QUAD 2
+#define CSDC_TRP_SINGLE 3
+
+typedef struct {
+ UINT8 Code;
+ BOOLEAN AddrAccess;
+ BOOLEAN AddrMode4Byte;
+ BOOLEAN HighZ;
+ BOOLEAN ReadWrite;
+ UINT8 CscfgMbm;
+ UINT8 CsdcTrp;
+} CSDC_DEFINITION;
+
+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
+
+typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
+
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NOR_FLASH_DEVICE_PATH;
+
+struct _NOR_FLASH_INSTANCE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+
+ BOOLEAN Initialized;
+ NOR_FLASH_INITIALIZE Initialize;
+
+ UINTN HostRegisterBaseAddress;
+ UINTN DeviceBaseAddress;
+ UINTN RegionBaseAddress;
+ UINTN Size;
+ EFI_LBA StartLba;
+ EFI_LBA OffsetLba;
+
+ EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
+ EFI_BLOCK_IO_MEDIA Media;
+ EFI_DISK_IO_PROTOCOL DiskIoProtocol;
+
+ BOOLEAN SupportFvb;
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+ VOID* ShadowBuffer;
+
+ NOR_FLASH_DEVICE_PATH DevicePath;
+
+ CONST CSDC_DEFINITION *CmdTable;
+ UINTN CmdTableSize;
+};
+
+EFI_STATUS
+NorFlashReadCfiData (
+ IN UINTN DeviceBaseAddress,
+ IN UINTN CFI_Offset,
+ IN UINT32 NumberOfBytes,
+ OUT UINT32 *Data
+ );
+
+EFI_STATUS
+NorFlashWriteBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN TargetAddress,
+ IN UINTN BufferSizeInBytes,
+ IN UINT32 *Buffer
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+);
+
+//
+// NorFlashFvbDxe.c
+//
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ );
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ );
+
+//
+// NorFlashDxe.c
+//
+
+EFI_STATUS
+NorFlashUnlockAndEraseSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN BlockAddress
+ );
+
+EFI_STATUS
+NorFlashWriteSingleBlock (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashWriteBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ );
+
+EFI_STATUS
+NorFlashReadBlocks (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+NorFlashRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+NorFlashWrite (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashReset (
+ IN NOR_FLASH_INSTANCE *Instance
+ );
+
+#endif /* __NOR_FLASH_DXE_H__ */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
new file mode 100644
index 000000000000..b63d778d84bc
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
@@ -0,0 +1,845 @@
+/*++ @file NorFlashFvbDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ --*/
+
+#include <PiDxe.h>
+
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Guid/VariableFormat.h>
+#include <Guid/SystemNvDataGuid.h>
+
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mFvbVirtualAddrChangeEvent;
+STATIC UINTN mFlashNvStorageVariableBase;
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr - Location to initialise the headers
+
+**/
+STATIC
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN BlockSize;
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize (Instance);
+ }
+
+ HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) +
+ sizeof(EFI_FV_BLOCK_MAP_ENTRY) +
+ sizeof(VARIABLE_STORE_HEADER);
+ Headers = AllocateZeroPool(HeadersLength);
+
+ BlockSize = Instance->Media.BlockSize;
+
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area
+ // AND the FTW working area AND the FTW Spare contiguous.
+ ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) +
+ PcdGet32(PcdFlashNvStorageVariableSize) ==
+ PcdGet32(PcdFlashNvStorageFtwWorkingBase));
+ ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) +
+ PcdGet32(PcdFlashNvStorageFtwWorkingSize) ==
+ PcdGet32(PcdFlashNvStorageFtwSpareBase));
+
+ // Check if the size of the area is at least one block size
+ ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) &&
+ (PcdGet32(PcdFlashNvStorageVariableSize) / BlockSize > 0));
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) &&
+ (PcdGet32(PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0));
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) &&
+ (PcdGet32(PcdFlashNvStorageFtwSpareSize) / BlockSize > 0));
+
+ // Ensure the Variable areas are aligned on block size boundaries
+ ASSERT((PcdGet32(PcdFlashNvStorageVariableBase) % BlockSize) == 0);
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0);
+ ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength =
+ PcdGet32(PcdFlashNvStorageVariableSize) +
+ PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32(PcdFlashNvStorageFtwSpareSize);
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP |
+ EFI_FVB2_READ_STATUS |
+ EFI_FVB2_STICKY_WRITE |
+ EFI_FVB2_MEMORY_MAPPED |
+ EFI_FVB2_ERASE_POLARITY |
+ EFI_FVB2_WRITE_STATUS |
+ EFI_FVB2_WRITE_ENABLED_CAP;
+
+ FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) +
+ sizeof(EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 (
+ (UINT16*)FirmwareVolumeHeader,
+ FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VOID *)((UINTN)Headers +
+ FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
+ VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) -
+ FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+ FreePool (Headers);
+ return Status;
+}
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader - A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS - The firmware volume is consistent
+ @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN VariableStoreLength;
+ UINTN FvLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress;
+
+ FvLength = PcdGet32(PcdFlashNvStorageVariableSize) +
+ PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32(PcdFlashNvStorageFtwSpareSize);
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ( (FwVolHeader->Revision != EFI_FVH_REVISION)
+ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
+ || (FwVolHeader->FvLength != FvLength)
+ )
+ {
+ DEBUG ((DEBUG_INFO, "%a: No Firmware Volume header present\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) {
+ DEBUG ((DEBUG_INFO, "%a: Firmware Volume Guid non-compatible\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG ((DEBUG_INFO, "%a: FV checksum is invalid (Checksum:0x%X)\n",
+ __FUNCTION__, Checksum));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreHeader = (VOID *)((UINTN)FwVolHeader +
+ FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
+ !CompareGuid (&VariableStoreHeader->Signature,
+ &gEfiAuthenticatedVariableGuid)) {
+ DEBUG ((DEBUG_INFO, "%a: Variable Store Guid non-compatible\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) -
+ FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength) {
+ DEBUG ((DEBUG_INFO, "%a: Variable Store Length does not match\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in
+ EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ FlashFvbAttributes = EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS |
+ EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED |
+ EFI_FVB2_ERASE_POLARITY;
+
+ // Check if it is write protected
+ if (!Instance->Media.ReadOnly) {
+ FlashFvbAttributes |= EFI_FVB2_WRITE_STATUS | EFI_FVB2_WRITE_ENABLED_CAP;
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to
+ EFI_FVB_ATTRIBUTES_2 that contains the desired
+ firmware volume settings.
+ On successful return, it contains the new
+ settings of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with
+ the capabilities as declared in the firmware
+ volume header.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",
+ *Attributes));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n",
+ Instance->RegionBaseAddress));
+
+ ASSERT(Address != NULL);
+
+ *Address = mFlashNvStorageVariableBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block whose size to return
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO,
+ "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba,
+ Instance->Media.BlockSize, Instance->Media.LastBlock));
+
+ if (Lba > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR,
+ "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n",
+ Lba, Instance->Media.LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // This is easy because in this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) Instance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+ DEBUG ((DEBUG_BLKIO,
+ "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize,
+ *NumberOfBlocks));
+
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the
+ buffer.
+ At exit, *NumBytes contains the total number of
+ bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be
+ used to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and
+ contents are in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of
+ bytes returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
+ could not be read.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS TempStatus;
+ UINTN BlockSize;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO,
+ "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize(Instance);
+ }
+
+ TempStatus = EFI_SUCCESS;
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO,
+ "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n",
+ Offset, *NumBytes, BlockSize ));
+
+ // The read must not span block boundaries.
+ // We need to check each variable individually because adding two large
+ // values together overflows.
+ if (Offset >= BlockSize ||
+ *NumBytes > BlockSize ||
+ (Offset + *NumBytes) > BlockSize) {
+ DEBUG ((DEBUG_ERROR,
+ "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
+ Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to read
+ if (*NumBytes == 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Decide if we are doing full block reads or not.
+ if (*NumBytes % BlockSize != 0) {
+ TempStatus = NorFlashRead (Instance, Instance->StartLba + Lba, Offset,
+ *NumBytes, Buffer);
+ if (EFI_ERROR (TempStatus)) {
+ return EFI_DEVICE_ERROR;
+ }
+ } else {
+ // Read NOR Flash data into shadow buffer
+ TempStatus = NorFlashReadBlocks (Instance, Instance->StartLba + Lba,
+ BlockSize, Buffer);
+ if (EFI_ERROR (TempStatus)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the
+ buffer.
+ At exit, *NumBytes contains the total number of
+ bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of
+ bytes actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be
+ written.
+
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset,
+ NumBytes, Buffer);
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks
+ to erase.
+
+ The list is terminated with an
+ EFI_LBA_LIST_TERMINATOR.
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
+ state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly
+ and could not be written.
+ The firmware device may have been partially
+ erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable
+ argument list do not exist in the firmware
+ volume.
+
+ **/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly) {
+ // Firmware volume is in WriteDisabled state
+ DEBUG ((DEBUG_ERROR,
+ "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"));
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to ensure
+ // all specified blocks are valid
+
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // All blocks must be within range
+ DEBUG ((DEBUG_BLKIO,
+ "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
+ Instance->StartLba + StartingLba, NumOfLba, Instance->Media.LastBlock));
+ if (NumOfLba == 0 ||
+ (Instance->StartLba + StartingLba + NumOfLba - 1) >
+ Instance->Media.LastBlock) {
+ VA_END (Args);
+ DEBUG ((DEBUG_ERROR,
+ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+ //
+ // To get here, all must be ok, so start erasing
+ //
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0) {
+
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress,
+ Instance->StartLba + StartingLba,
+ Instance->Media.BlockSize);
+
+ // Erase it
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
+ Instance->StartLba + StartingLba, BlockAddress));
+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
+ if (EFI_ERROR(Status)) {
+ VA_END (Args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+EXIT:
+ return Status;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+STATIC
+VOID
+EFIAPI
+FvbVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ )
+{
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+
+ DEBUG ((DEBUG_BLKIO,"NorFlashFvbInitialize\n"));
+
+ Instance->Initialized = TRUE;
+ mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
+
+ // Set the index of the first LBA for the FVB
+ Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) -
+ Instance->RegionBaseAddress) /
+ Instance->Media.BlockSize;
+
+ BootMode = GetBootModeHob ();
+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // Determine if there is a valid header at the beginning of the NorFlash
+ Status = ValidateFvHeader (Instance);
+ }
+
+ // Install the Default FVB header if required
+ if (EFI_ERROR(Status)) {
+ // There is no valid header, so time to install one.
+ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n",
+ __FUNCTION__));
+
+ // Erase all the NorFlash that is reserved for variable storage
+ FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) +
+ PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32(PcdFlashNvStorageFtwSpareSize)) /
+ Instance->Media.BlockSize;
+
+ Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba,
+ EFI_LBA_LIST_TERMINATOR);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ Status = InitializeFvAndVariableStoreHeaders (Instance);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
+ //
+ RuntimeMmioRegionSize = Instance->Size;
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ Instance->RegionBaseAddress, RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gDS->SetMemorySpaceAttributes (
+ Instance->RegionBaseAddress, RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ FvbVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mFvbVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 13/14] Silicon/Socionext: add driver for SPI NOR flash
2017-09-08 18:23 ` [PATCH edk2-platforms 13/14] Silicon/Socionext: add driver for SPI NOR flash Ard Biesheuvel
@ 2017-09-11 19:13 ` Leif Lindholm
[not found] ` <e55ff6c595f74189bd53787f3b6b2283@SOC-EX03V.e01.socionext.com>
0 siblings, 1 reply; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 19:13 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:14PM +0100, Ard Biesheuvel wrote:
> This imports the driver sources provided by Socionext for the FIP006
> SPI NOR flash device found on Synquacer SoCs. It has been slightly
> tweaked to bring it up to date with the changes made on the EDK2 side
> since it was forked.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec | 31 +
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf | 78 ++
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h | 242 ++++
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c | 136 ++
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c | 1313 ++++++++++++++++++++
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h | 305 +++++
> Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c | 845 +++++++++++++
> 7 files changed, 2950 insertions(+)
>
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
> new file mode 100644
> index 000000000000..6c0ac807fd0b
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
> @@ -0,0 +1,31 @@
> +## @file
> +# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
> +#
> +# Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
Bump.
> + PACKAGE_NAME = Fip006DxePkg
> + PACKAGE_GUID = ABC7870B-FE82-4DAD-8179-FEC5F5194FA0
> + PACKAGE_VERSION = 0.1
> +
> +[Guids]
> + gFip006DxeTokenSpaceGuid = {0x4D45399E, 0x98F9, 0x4127, {0x8F, 0xB9,0xF8, 0xDE, 0x22, 0xA1, 0x09, 0x2C}}
> +
> +[PcdsFixedAtBuild]
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x0|UINT32|0x00000001
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0|UINT32|0x00000002
> + gFip006DxeTokenSpaceGuid.PcdN25qSlaveId|0x0|UINT8|0x00000003
> + gFip006DxeTokenSpaceGuid.PcdN25qBlockSize|256|UINT32|0x00000004
> + gFip006DxeTokenSpaceGuid.PcdN25qBlockCount|524288|UINT32|0x00000005
> +
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
> new file mode 100644
> index 000000000000..5727d4d937c9
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
> @@ -0,0 +1,78 @@
> +## @file
> +# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver
> +#
> +# Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Bump.
> + BASE_NAME = Fip006Dxe
> + FILE_GUID = 44F7D21F-C36F-4766-BC5B-C72E97E6897B
> + MODULE_TYPE = DXE_RUNTIME_DRIVER
> + VERSION_STRING = 0.1
> + ENTRY_POINT = NorFlashInitialise
> +
> +[Sources]
> + NorFlashDxe.c
> + NorFlashBlockIoDxe.c
> + NorFlashFvbDxe.c
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + DevicePathLib
> + DxeServicesTableLib
> + HobLib
> + IoLib
> + MemoryAllocationLib
> + NorFlashPlatformLib
> + UefiLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiRuntimeLib
> + UefiRuntimeServicesTableLib
> +
> +[Guids]
> + gEfiAuthenticatedVariableGuid
> + gEfiEventVirtualAddressChangeGuid
> + gEfiSystemNvDataFvGuid
> + gEfiVariableGuid
> +
> +[Protocols]
> + gEfiBlockIoProtocolGuid
> + gEfiDevicePathProtocolGuid
> + gEfiDiskIoProtocolGuid
> + gEfiFirmwareVolumeBlockProtocolGuid
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress
> +
> +[Depex]
> + #
> + # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty flash needs populating with default values
> + #
> + BEFORE gVariableRuntimeDxeFileGuid
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
> new file mode 100644
> index 000000000000..e515d967a1d7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
> @@ -0,0 +1,242 @@
> +/** @file
> + Socionext FIP006 Register List
> +
> + Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __EFI_FIP006_REG_H__
> +#define __EFI_FIP006_REG_H__
> +
> +#define FIP006_REG_MCTRL 0x00 // Module Control
> +typedef union {
> + UINT32 Raw : 32;
> + struct {
> + BOOLEAN MEN : 1;
> + BOOLEAN CSEN : 1;
> +#define MCTRL_CSEN_DIRECT 0
> +#define MCTRL_CSEN_CS 1
> + BOOLEAN CDSS : 1;
> +#define MCTRL_CDSS_IHCLK 0
> +#define MCTRL_CDSS_IPCLK 1
> + BOOLEAN MES : 1;
> +#define MCTRL_MES_READY 1
> + UINT8 : 4;
> + UINT8 : 8;
> + UINT8 : 8;
> + UINT8 : 8;
> + };
> +} FIP006_MCTRL;
I am generally not a fan of using bitfields like this...
> +
> +#define FIP006_REG_PCC0 0x04 // Peripheral Communication Control 0
> +#define FIP006_REG_PCC1 0x08 // Peripheral Communication Control 1
> +#define FIP006_REG_PCC2 0x0C // Peripheral Communication Control 2
> +#define FIP006_REG_PCC3 0x10 // Peripheral Communication Control 3
> +typedef union {
> + UINT32 Raw : 32;
> + struct {
> + BOOLEAN CPHA : 1;
> + BOOLEAN CPOL : 1;
> + BOOLEAN ACES : 1;
> + BOOLEAN RTM : 1;
> + BOOLEAN SSPOL : 1;
> + UINT8 SS2CD : 2;
> + BOOLEAN SDIR : 1;
> +#define PCC_SDIR_MS_BIT 0
> +#define PCC_SDIR_LS_BIT 1
> + BOOLEAN SENDIAN : 1;
> +#define PCC_SENDIAN_BIG 0
> +#define PCC_SENDIAN_LITTLE 1
> + UINT8 CDRS : 7;
> + BOOLEAN SAFESYNC : 1;
> + UINT8 WRDSEL : 4;
> + UINT8 RDDSEL : 2;
> + UINT8 : 1;
> + UINT8 : 8;
> + } Reg;
> +} FIP006_PCC;
> +typedef FIP006_PCC FIP006_PCC0, FIP006_PCC1, FIP006_PCC2, FIP006_PCC3;
> +
> +#define FIP006_REG_TXF 0x14 // Tx Interrupt Flag
> +#define TXF_TSSRS BIT6
> +#define TXF_TFMTS BIT5
> +#define TXF_TFLETS BIT4
> +#define TXF_TFUS BIT3
> +#define TXF_TFOS BIT2
> +#define TXF_TFES BIT1
> +#define TXF_TFFS BIT0
> +
> +#define FIP006_REG_TXE 0x18 // Tx Interrupt Enable
> +#define TXE_TSSRE BIT6
> +#define TXE_TFMTE BIT5
> +#define TXE_TFLETE BIT4
> +#define TXE_TFUE BIT3
> +#define TXE_TFOE BIT2
> +#define TXE_TFEE BIT1
> +#define TXE_TFFE BIT0
> +
> +#define FIP006_REG_TXC 0x1C // Tx Interrupt Clear
> +#define TXC_TSSRC BIT6
> +#define TXC_TFMTC BIT5
> +#define TXC_TFLETC BIT4
> +#define TXC_TFUC BIT3
> +#define TXC_TFOC BIT2
> +#define TXC_TFEC BIT1
> +#define TXC_TFFC BIT0
> +
> +#define FIP006_REG_RXF 0x20 // Rx Interrupt Flag
> +#define RXF_RSSRS BIT6
> +#define RXF_RFMTS BIT5
> +#define RXF_RFLETS BIT4
> +#define RXF_RFUS BIT3
> +#define RXF_RFOS BIT2
> +#define RXF_RFES BIT1
> +#define RXF_RFFS BIT0
> +
> +#define FIP006_REG_RXE 0x24 // Rx Interrupt Enable
> +#define RXE_RSSRE BIT6
> +#define RXE_RFMTE BIT5
> +#define RXE_RFLETE BIT4
> +#define RXE_RFUE BIT3
> +#define RXE_RFOE BIT2
> +#define RXE_RFEE BIT1
> +#define RXE_RFFE BIT0
> +
> +#define FIP006_REG_RXC 0x28 // Rx Interrupt Clear
> +#define RXC_RSSRC BIT6
> +#define RXC_RFMTC BIT5
> +#define RXC_RFLETC BIT4
> +#define RXC_RFUC BIT3
> +#define RXC_RFOC BIT2
> +#define RXC_RFEC BIT1
> +#define RXC_RFFC BIT0
> +
> +#define FIP006_REG_FAULTF 0x2C // Error Interrupt Status
> +#define FAULTF_DRCBSFS BIT4
> +#define FAULTF_DWCBSFS BIT3
> +#define FAULTF_PVFS BIT2
> +#define FAULTF_WAFS BIT1
> +#define FAULTF_UMAFS BIT0
> +
> +#define FIP006_REG_FAULTC 0x30 // Error Interrupt Clear
> +#define FAULTC_DRCBSFC BIT4
> +#define FAULTC_DWCBSFC BIT3
> +#define FAULTC_PVFC BIT2
> +#define FAULTC_WAFC BIT1
> +#define FAULTC_UMAFC BIT0
> +
> +#define FIP006_REG_DM_CFG 0x34 // Direct Mode DMA Configuration
> +#define DM_CFG_MSTARTEN BIT2
> +#define DM_CFG_SSDC BIT1
> +
> +#define FIP006_REG_DM_DMA 0x35 // Direct Mode DMA Enable
> +#define DM_DMA_TXDMAEN BIT1
> +#define DM_DMA_RXDMAEN BIT0
> +
> +#define FIP006_REG_DM_START 0x38 // Direct Mode Start Transmission
> +#define DM_START BIT0
> +#define FIP006_REG_DM_STOP 0x39 // Direct Mode Stop Transmission
> +#define DM_STOP BIT0
> +
> +#define FIP006_REG_DM_PSEL 0x3A // Direct Mode Peripheral Select
> +#define DM_PSEL (BIT1 | BIT0)
> +
> +#define FIP006_REG_DM_TRP 0x3B // Direct Mode Transmission Protocol
> +#define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define FIP006_REG_DM_BCC 0x3C // Direct Mode Byte Count Control
> +#define FIP006_REG_DM_BCS 0x3E // Direct Mode Byte Count Status
> +
> +#define FIP006_REG_DM_STATUS 0x40 // Direct Mode Status
> +#define DM_STATUS_TXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define DM_STATUS_RXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define DM_STATUS_TXACTIVE BIT1
> +#define DM_STATUS_RXACTIVE BIT0
> +
> +#define FIP006_REG_FIFO_CFG 0x4C // FIFO Configuration
> +#define FIFO_CFG_TXFLSH BIT12
> +#define FIFO_CFG_RXFLSH BIT11
> +#define FIFO_CFG_TXCTRL BIT10
> +#define FIFO_CFG_FWIDTH (BIT9 | BIT8)
> +#define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4)
> +#define FIFO_CFG_RXFTH (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define FIP006_REG_FIFO_TX 0x50 // 16 32-bit Tx FIFO
> +#define FIP006_REG_FIFO_RX 0x90 // 16 32-bit Rx FIFO
> +
> +#define FIP006_REG_CS_CFG 0xD0 // Command Sequencer Configuration
> +typedef union {
> + UINT32 Raw : 32;
> + struct {
> + BOOLEAN SRAM : 1;
> +#define CS_CFG_SRAM_RO 0
> +#define CS_CFG_SRAM_RW 1
> + UINT8 MBM : 2;
> +#define CS_CFG_MBM_SINGLE 0
> +#define CS_CFG_MBM_DUAL 1
> +#define CS_CFG_MBM_QUAD 2
> + BOOLEAN SPICHNG : 1;
> + BOOLEAN BOOTEN : 1;
> + BOOLEAN BSEL : 1;
> + UINT8 : 2;
> + BOOLEAN SSEL0EN : 1;
> + BOOLEAN SSEL1EN : 1;
> + BOOLEAN SSEL2EN : 1;
> + BOOLEAN SSEL3EN : 1;
> + UINT8 : 4;
> + BOOLEAN MSEL : 4;
> + UINT8 : 4;
> + UINT8 : 8;
> + } Reg;
> +} FIP006_CS_CFG;
> +
> +#define FIP006_REG_CS_ITIME 0xD4 // Command Sequencer Idle Timer
> +typedef union {
> + UINT32 Raw : 32;
> + struct {
> + UINT16 ITIME : 16;
> + UINT16 : 16;
> + } Reg;
> +} FIP006_CS_ITIME;
> +#define FIP006_REG_CS_AEXT 0xD8 // Command Sequencer Address Extension
> +typedef union {
> + UINT32 Raw : 32;
> + struct {
> + UINT16 : 13;
> + UINT32 AEXT : 19;
> + } Reg;
> +} FIP006_CS_AEXT;
> +
> +#define FIP006_REG_CS_RD 0xDC // Command Sequencer Read Control
> +#define CS_RD_DEPTH 8
> +#define FIP006_REG_CS_WR 0xEC // Command Sequencer Write Control
> +#define CS_WR_DEPTH 8
> +typedef union {
> + UINT16 Raw : 16;
> + struct {
> + BOOLEAN DEC : 1;
> + UINT8 TRP : 2;
> + BOOLEAN CONT : 1;
> + UINT8 : 4;
> + union {
> + UINT8 Data : 8;
> + struct {
> + UINT8 Data : 3;
> + UINT8 : 5;
> + } Cmd;
> + } Payload;
> + } Reg;
> +} FIP006_CS_CMD;
> +typedef FIP006_CS_CMD FIP006_CS_RD, FIP006_CS_WR;
> +
> +#define FIP006_REG_MID 0xFC // Command Sequencer Module ID
> +typedef UINT32 FIP006_MID;
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
> new file mode 100644
> index 000000000000..b325d1721aa4
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
> @@ -0,0 +1,136 @@
> +/** @file NorFlashBlockIoDxe.c
> +
> + Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
Add Linaro copyright?
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include "NorFlashDxe.h"
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReset (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN BOOLEAN ExtendedVerification
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS(This);
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashBlockIoReset(MediaId=0x%x)\n",
> + This->Media->MediaId));
> +
> + return NorFlashReset (Instance);
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReadBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> + EFI_BLOCK_IO_MEDIA *Media;
> +
> + if (This == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS(This);
> + Media = This->Media;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes "
> + "(%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
> +
> + if (!Media) {
> + Status = EFI_INVALID_PARAMETER;
> + } else if (!Media->MediaPresent) {
> + Status = EFI_NO_MEDIA;
> + } else if (Media->MediaId != MediaId) {
> + Status = EFI_MEDIA_CHANGED;
> + } else if ((Media->IoAlign > 2) &&
> + (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + Status = NorFlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer);
> + }
> +
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoWriteBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS(This);
Space before (?
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashBlockIoWriteBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes "
> + "(%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer));
> +
> + if( !This->Media->MediaPresent ) {
And drop superflous whitespace.
> + Status = EFI_NO_MEDIA;
> + } else if( This->Media->MediaId != MediaId ) {
> + Status = EFI_MEDIA_CHANGED;
> + } else if( This->Media->ReadOnly ) {
> + Status = EFI_WRITE_PROTECTED;
> + } else {
> + Status = NorFlashWriteBlocks (Instance,Lba,BufferSizeInBytes,Buffer);
> + }
> +
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoFlushBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This
> + )
> +{
> + // No Flush required for the NOR Flash driver
> + // because cache operations are not permitted.
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashBlockIoFlushBlocks: Function NOT IMPLEMENTED (not required).\n"));
> +
> + // Nothing to do so just return without error
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
> new file mode 100644
> index 000000000000..ad004ddf03b3
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
> @@ -0,0 +1,1313 @@
> +/** @file NorFlashDxe.c
> +
> + Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
Add copyright notice?
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/UefiLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/PcdLib.h>
> +
Sort alphabetically?
> +#include "NorFlashDxe.h"
> +
> +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
> +
> +//
> +// Global variable declarations
> +//
> +STATIC NOR_FLASH_INSTANCE **mNorFlashInstances;
> +STATIC UINT32 mNorFlashDeviceCount;
> +
> +STATIC CONST UINT16 mFip006NullCmdSeq[] = {
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1),
> + CSDC (0x07, 0, CSDC_TRP_MBM, 1)
> +};
> +
> +STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = {
> + // Register Operations
> + { 0x05, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0x01, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0xE8, TRUE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0x70, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0xB5, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0x85, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0x65, FALSE, FALSE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + // Read Operations
> + { 0x13, TRUE, TRUE, FALSE, FALSE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + // Write Operations
> + { 0x02, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> + { 0x32, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_QUAD, CSDC_TRP_SINGLE },
> + // Erase Operations
> + { 0xD8, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, CSDC_TRP_SINGLE },
> +};
> +
> +STATIC
> +EFI_STATUS
> +NorFlashSetHostCSDC (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN BOOLEAN ReadWrite,
> + IN CONST UINT16 CSDC[8]
> + )
> +{
> + EFI_PHYSICAL_ADDRESS Dst;
> + UINTN Index;
> +
> + Dst = Instance->HostRegisterBaseAddress
> + + (ReadWrite ? FIP006_REG_CS_WR : FIP006_REG_CS_RD);
> + for (Index = 0; Index < 8; Index++) {
ARRAY_SIZE instead of 8?
> + MmioWrite16 (Dst + (Index << 1), CSDC[Index]);
> + }
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +CONST CSDC_DEFINITION *
> +NorFlashGetCmdDef (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINT8 Code
> + )
> +{
> + CONST CSDC_DEFINITION *Cmd;
> + UINTN Index;
> +
> + Cmd = NULL;
> + for (Index = 0; Index < Instance->CmdTableSize; Index++) {
> + if (Code == Instance->CmdTable[Index].Code) {
> + Cmd = &Instance->CmdTable[Index];
> + break;
> + }
> + }
> + return Cmd;
> +}
> +
> +STATIC
> +EFI_STATUS
> +GenCSDC (
> + IN UINT8 Cmd,
> + IN BOOLEAN AddrAccess,
> + IN BOOLEAN AddrMode4Byte,
> + IN BOOLEAN HighZ,
> + IN UINT8 TransferMode,
> + OUT UINT16 CmdSeq[8]
> + )
> +{
> + UINTN Index;
> +
> + if (!CmdSeq) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Index = 0;
> + CopyMem (CmdSeq, mFip006NullCmdSeq, 8 * sizeof (UINT16));
ARRAY_SIZE?
> +
> + CmdSeq[Index++] = CSDC (Cmd, 0, TransferMode, 0);
> + if (AddrAccess) {
> + if (AddrMode4Byte) {
> + CmdSeq[Index++] = CSDC (0x03, 0, TransferMode, 1);
> + }
> + CmdSeq[Index++] = CSDC (0x02, 0, TransferMode, 1);
> + CmdSeq[Index++] = CSDC (0x01, 0, TransferMode, 1);
> + CmdSeq[Index++] = CSDC (0x00, 0, TransferMode, 1);
> + }
> + if (HighZ) {
> + CmdSeq[Index++] = CSDC (0x04, 0, TransferMode, 1);
Can anythng be done about these magic hex values?
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashSetHostCommand (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINT8 Code
> + )
> +{
> + CONST CSDC_DEFINITION *Cmd;
> + UINT16 CSDC[8];
> +
> + Cmd = NorFlashGetCmdDef(Instance, Code);
> + if (Cmd == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + GenCSDC (
> + Cmd->Code,
> + Cmd->AddrAccess,
> + Cmd->AddrMode4Byte,
> + Cmd->HighZ,
> + Cmd->CsdcTrp,
> + CSDC
> + );
> + NorFlashSetHostCSDC (Instance, Cmd->ReadWrite, CSDC);
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +UINT8
> +NorFlashReadStatusRegister (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN SR_Address
> + )
> +{
> + UINT8 StatusRegister;
> +
> + NorFlashSetHostCommand (Instance, 0x05);
> + StatusRegister = NOR_FLASH_READ_BYTE (Instance, 0);
> + NorFlashSetHostCommand (Instance, 0x13);
Magic values?
> + return StatusRegister;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashWaitProgramErase (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + DEBUG ((DEBUG_BLKIO, "NorFlashWaitProgramErase()\n"));
> +
> + NorFlashSetHostCommand (Instance, 0x70);
> + while ((NOR_FLASH_READ_BYTE (Instance, 0) & BIT7) == 0);
> + NorFlashSetHostCommand (Instance, 0x13);
Magic values? (Including BIT7.)
> + return EFI_SUCCESS;
> +}
> +
> +// TODO: implement lock checking
Is this a TODO for this series, or inherited?
> +STATIC
> +BOOLEAN
> +NorFlashBlockIsLocked (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + )
> +{
> + return FALSE;
> +}
> +
> +// TODO: implement sector unlocking
> +STATIC
> +EFI_STATUS
> +NorFlashUnlockSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashUnlockSingleBlockIfNecessary (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = EFI_SUCCESS;
> +
> + if (NorFlashBlockIsLocked (Instance, BlockAddress) == TRUE) {
> + Status = NorFlashUnlockSingleBlock (Instance, BlockAddress);
> + }
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashEnableWrite (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 StatusRegister;
> + UINTN Retry;
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashEnableWrite()\n"));
> +
> + Status = EFI_DEVICE_ERROR;
> + Retry = 100;
Are 100 retries really necessary?
Polling 100 times to wait for a status flag to flip is one
thing. Repeating a command 100 times is something else.
> +
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> + while (Retry > 0 && EFI_ERROR (Status)) {
> + NOR_FLASH_WRITE_BYTE (Instance, 0, 0x06);
> + StatusRegister = NorFlashReadStatusRegister (Instance, 0);
> + Status = (StatusRegister & BIT1) ? EFI_SUCCESS : EFI_DEVICE_ERROR;
Magic values? (0x06 and BIT1.)
> + Retry--;
> + }
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashDisableWrite (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 StatusRegister;
> + UINTN Retry;
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashDisableWrite()\n"));
> +
> + Status = EFI_DEVICE_ERROR;
> + Retry = 10;
And why just (but still) 10 when going the other way.
> +
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> + while (Retry > 0 && EFI_ERROR (Status)) {
> + NOR_FLASH_WRITE_BYTE (Instance, 0, 0x04);
> + StatusRegister = NorFlashReadStatusRegister (Instance, 0);
> + Status = (StatusRegister & BIT1) ? EFI_DEVICE_ERROR : EFI_SUCCESS;
Magic?
> + Retry--;
> + }
> + return Status;
> +}
> +
> +/**
> + * The following function presumes that the block has already been unlocked.
> + **/
> +STATIC
> +EFI_STATUS
> +NorFlashEraseSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + )
> +{
> + UINT16 Sector;
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashEraseSingleBlock(BlockAddress=0x%08x)\n",
> + BlockAddress));
> +
> + Sector = (BlockAddress - Instance->RegionBaseAddress) /
> + Instance->Media.BlockSize;
> + Sector += Instance->OffsetLba;
> +
> + if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // Erase a block
> + NorFlashSetHostCommand (Instance, 0xD8);
Magic?
> + *(UINT16*) Instance->RegionBaseAddress = SwapBytes16 (Sector);
Space after cast.
> + NorFlashWaitProgramErase (Instance);
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> +
> + NorFlashDisableWrite (Instance);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + * This function unlock and erase an entire NOR Flash block.
> + **/
> +EFI_STATUS
> +NorFlashUnlockAndEraseSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + )
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> + EFI_TPL OriginalTPL;
> +
> + if (!EfiAtRuntime ()) {
> + // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
> + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
> + } else {
> + // This initialization is only to prevent the compiler to complain about the
> + // use of uninitialized variables
> + OriginalTPL = TPL_HIGH_LEVEL;
> + }
> +
> + Index = 0;
> + // The block erase might fail a first time (SW bug ?). Retry it ...
> + do {
> + // Unlock the block if we have to
> + Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
> + Index++;
> + } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
> +
> + if (Index == NOR_FLASH_ERASE_RETRY) {
> + DEBUG ((DEBUG_ERROR,
> + "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n",
> + BlockAddress,Index));
> + }
> +
> + if (!EfiAtRuntime ()) {
> + // Interruptions can resume.
> + gBS->RestoreTPL (OriginalTPL);
> + }
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashWriteSingleWord (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN WordAddress,
> + IN UINT32 WriteData
> + )
> +{
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashWriteSingleWord(WordAddress=0x%08x, WriteData=0x%08x)\n",
> + WordAddress, WriteData));
> +
> + Status = EFI_SUCCESS;
> +
> + if (EFI_ERROR (NorFlashEnableWrite (Instance))) {
> + return EFI_DEVICE_ERROR;
> + }
> + NorFlashSetHostCommand (Instance, 0x02);
Magic?
> + *(UINT32*) WordAddress = WriteData;
Space after cast.
> + NorFlashWaitProgramErase (Instance);
> +
> + NorFlashDisableWrite (Instance);
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +NorFlashWriteFullBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINT32 *DataBuffer,
> + IN UINT32 BlockSizeInWords
> + )
> +{
> + EFI_STATUS Status;
> + UINTN WordAddress;
> + UINT32 WordIndex;
> + UINTN BlockAddress;
> + EFI_TPL OriginalTPL;
> +
> + Status = EFI_SUCCESS;
> +
> + // Get the physical address of the block
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
> + BlockSizeInWords * 4);
> +
> + // Start writing from the first address at the start of the block
> + WordAddress = BlockAddress;
> +
> + if (!EfiAtRuntime ()) {
> + // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
> + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
> + } else {
> + // This initialization is only to prevent the compiler to complain about the
> + // use of uninitialized variables
> + OriginalTPL = TPL_HIGH_LEVEL;
> + }
> +
> + Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n",
> + BlockAddress));
> + goto EXIT;
> + }
> +
> + for (WordIndex=0;
> + WordIndex < BlockSizeInWords;
> + WordIndex++, DataBuffer++, WordAddress += 4) {
> + Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
> + if (EFI_ERROR (Status)) {
> + goto EXIT;
> + }
> + }
> +
> +EXIT:
> + if (!EfiAtRuntime ()) {
> + // Interruptions can resume.
I would probably go with "Re-enable pre-emption" :)
> + gBS->RestoreTPL (OriginalTPL);
> + }
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = \"%r\".\n",
> + WordAddress, Status));
> + }
> + return Status;
> +}
> +
> +EFI_STATUS
> +NorFlashWriteBlocks (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> + )
> +{
> + UINT32 *pWriteBuffer;
> + EFI_STATUS Status = EFI_SUCCESS;
> + EFI_LBA CurrentBlock;
> + UINT32 BlockSizeInWords;
> + UINT32 NumBlocks;
> + UINT32 BlockCount;
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if(Instance->Media.ReadOnly == TRUE) {
> + return EFI_WRITE_PROTECTED;
> + }
> +
> + // We must have some bytes to read
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n",
> + BufferSizeInBytes));
> + if(BufferSizeInBytes == 0) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // The size of the buffer must be a multiple of the block size
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n",
> + Instance->Media.BlockSize));
> + if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // All blocks must be within the device
> + NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks,
> + Instance->Media.LastBlock, Lba));
> +
> + if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + BlockSizeInWords = Instance->Media.BlockSize / 4;
> +
> + // Because the target *Buffer is a pointer to VOID, we must put
> + // all the data into a pointer to a proper data type, so use *ReadBuffer
> + pWriteBuffer = (UINT32 *)Buffer;
> +
> + CurrentBlock = Lba;
> + for (BlockCount = 0;
> + BlockCount < NumBlocks;
> + BlockCount++, CurrentBlock++, pWriteBuffer += BlockSizeInWords) {
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n",
> + (UINTN)CurrentBlock));
> +
> + Status = NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffer,
> + BlockSizeInWords);
> +
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + }
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n", Status));
> + return Status;
> +}
> +
> +EFI_STATUS
> +NorFlashReadBlocks (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + )
> +{
> + UINT32 NumBlocks;
> + UINTN StartAddress;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n",
> + BufferSizeInBytes, Instance->Media.BlockSize, Instance->Media.LastBlock,
> + Lba));
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Return if we have not any byte to read
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + // The size of the buffer must be a multiple of the block size
> + if ((BufferSizeInBytes % Instance->Media.BlockSize) != 0) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // All blocks must be within the device
> + NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->Media.BlockSize ;
> +
> + if ((Lba + NumBlocks) > (Instance->Media.LastBlock + 1)) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashReadBlocks: ERROR - Read will exceed last block\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Get the address to start reading from
> + StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
> + Instance->Media.BlockSize);
> +
> + // Put the device into Read Array mode
> + NorFlashSetHostCommand (Instance, 0x13);
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> +
> + // Readout the data
> + CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN StartAddress;
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Return if we have not any byte to read
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + if (((Lba * Instance->Media.BlockSize) + Offset + BufferSizeInBytes) >
> + Instance->Size) {
Could fit onto one line with a local variable for "Lba * Instance->Media.Blocksize".
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashRead: ERROR - Read will exceed device size.\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Get the address to start reading from
> + StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
> + Instance->Media.BlockSize);
> +
> + // Put the device into Read Array mode
> + NorFlashSetHostCommand (Instance, 0x13);
Magic?
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> +
> + // Readout the data
> + CopyMem (Buffer, (UINTN *)(StartAddress + Offset), BufferSizeInBytes);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/*
> + Write a full or portion of a block. It must not span block boundaries;
> + that is, Offset + *NumBytes <= Instance->Media.BlockSize.
> +*/
> +EFI_STATUS
> +NorFlashWriteSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS TempStatus;
> + UINT32 Tmp;
> + UINT32 TmpBuf;
> + UINT32 WordToWrite;
> + UINT32 Mask;
> + BOOLEAN DoErase;
> + UINTN BytesToWrite;
> + UINTN CurOffset;
> + UINTN WordAddr;
> + UINTN BlockSize;
> + UINTN BlockAddress;
> + UINTN PrevBlockAddress;
Preferable to avoid the ambiguous 'word' moniker.
> +
> + PrevBlockAddress = 0;
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize(Instance);
> + }
> +
> + DEBUG ((DEBUG_BLKIO,
> + "NorFlashWriteSingleBlock(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
> + Lba, Offset, *NumBytes, Buffer));
> +
> + // Detect WriteDisabled state
> + if (Instance->Media.ReadOnly == TRUE) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashWriteSingleBlock: ERROR - Can not write: Device is in WriteDisabled state.\n"));
> + // It is in WriteDisabled state, return an error right away
> + return EFI_ACCESS_DENIED;
> + }
> +
> + // Cache the block size to avoid de-referencing pointers all the time
> + BlockSize = Instance->Media.BlockSize;
> +
> + // The write must not span block boundaries.
> + // We need to check each variable individually because adding two large
> + // values together overflows.
> + if (Offset >= BlockSize ||
> + *NumBytes > BlockSize ||
> + (Offset + *NumBytes) > BlockSize) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
> + Offset, *NumBytes, BlockSize ));
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // We must have some bytes to write
> + if (*NumBytes == 0) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
> + Offset, *NumBytes, BlockSize ));
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // Pick 128bytes as a good start for word operations as opposed to erasing the
> + // block and writing the data regardless if an erase is really needed.
> + // It looks like most individual NV variable writes are smaller than 128bytes.
> + if (*NumBytes <= 128) {
> + // Check to see if we need to erase before programming the data into NOR.
> + // If the destination bits are only changing from 1s to 0s we can just write.
> + // After a block is erased all bits in the block is set to 1.
> + // If any byte requires us to erase we just give up and rewrite all of it.
> + DoErase = FALSE;
> + BytesToWrite = *NumBytes;
> + CurOffset = Offset;
> +
> + while (BytesToWrite > 0) {
> + // Read full word from NOR, splice as required. A word is the smallest
> + // unit we can write.
> + TempStatus = NorFlashRead (Instance, Lba, CurOffset & ~(0x3), sizeof(Tmp),
> + &Tmp);
> + if (EFI_ERROR (TempStatus)) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // Physical address of word in NOR to write.
> + WordAddr = (CurOffset & ~(0x3)) +
> + GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
> + BlockSize);
> +
> + // The word of data that is to be written.
> + TmpBuf = *((UINT32*)(Buffer + (*NumBytes - BytesToWrite)));
> +
> + // First do word aligned chunks.
'word' is ambiguous here. 32-bit is probably correct.
> + if ((CurOffset & 0x3) == 0) {
> + if (BytesToWrite >= 4) {
> + // Is the destination still in 'erased' state?
> + if (~Tmp != 0) {
> + // Check to see if we are only changing bits to zero.
> + if ((Tmp ^ TmpBuf) & TmpBuf) {
> + DoErase = TRUE;
> + break;
> + }
> + }
> + // Write this word to NOR
!word
> + WordToWrite = TmpBuf;
> + CurOffset += sizeof(TmpBuf);
> + BytesToWrite -= sizeof(TmpBuf);
> + } else {
> + // BytesToWrite < 4. Do small writes and left-overs
> + Mask = ~((~0) << (BytesToWrite * 8));
> + // Mask out the bytes we want.
> + TmpBuf &= Mask;
> + // Is the destination still in 'erased' state?
> + if ((Tmp & Mask) != Mask) {
> + // Check to see if we are only changing bits to zero.
> + if ((Tmp ^ TmpBuf) & TmpBuf) {
> + DoErase = TRUE;
> + break;
> + }
> + }
> + // Merge old and new data. Write merged word to NOR
> + WordToWrite = (Tmp & ~Mask) | TmpBuf;
> + CurOffset += BytesToWrite;
> + BytesToWrite = 0;
> + }
> + } else {
> + // Do multiple words, but starting unaligned.
!word
> + if (BytesToWrite > (4 - (CurOffset & 0x3))) {
> + Mask = ((~0) << ((CurOffset & 0x3) * 8));
> + // Mask out the bytes we want.
> + TmpBuf &= Mask;
> + // Is the destination still in 'erased' state?
> + if ((Tmp & Mask) != Mask) {
> + // Check to see if we are only changing bits to zero.
> + if ((Tmp ^ TmpBuf) & TmpBuf) {
> + DoErase = TRUE;
> + break;
> + }
> + }
> + // Merge old and new data. Write merged word to NOR
> + WordToWrite = (Tmp & ~Mask) | TmpBuf;
> + BytesToWrite -= (4 - (CurOffset & 0x3));
> + CurOffset += (4 - (CurOffset & 0x3));
> + } else {
> + // Unaligned and fits in one word.
> + Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8);
> + // Mask out the bytes we want.
> + TmpBuf = (TmpBuf << ((CurOffset & 0x3) * 8)) & Mask;
> + // Is the destination still in 'erased' state?
> + if ((Tmp & Mask) != Mask) {
> + // Check to see if we are only changing bits to zero.
> + if ((Tmp ^ TmpBuf) & TmpBuf) {
> + DoErase = TRUE;
> + break;
> + }
> + }
> + // Merge old and new data. Write merged word to NOR
> + WordToWrite = (Tmp & ~Mask) | TmpBuf;
> + CurOffset += BytesToWrite;
> + BytesToWrite = 0;
> + }
> + }
> +
> + //
> + // Write the word to NOR.
> + //
> +
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba,
> + BlockSize);
> + if (BlockAddress != PrevBlockAddress) {
> + TempStatus = NorFlashUnlockSingleBlockIfNecessary (Instance,
> + BlockAddress);
> + if (EFI_ERROR (TempStatus)) {
> + return EFI_DEVICE_ERROR;
> + }
> + PrevBlockAddress = BlockAddress;
> + }
> + TempStatus = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite);
> + if (EFI_ERROR (TempStatus)) {
> + return EFI_DEVICE_ERROR;
> + }
> + }
> + // Exit if we got here and could write all the data. Otherwise do the
> + // Erase-Write cycle.
> + if (!DoErase) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + // Check we did get some memory. Buffer is BlockSize.
> + if (Instance->ShadowBuffer == NULL) {
> + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // Read NOR Flash data into shadow buffer
> + TempStatus = NorFlashReadBlocks (Instance, Lba, BlockSize,
> + Instance->ShadowBuffer);
> + if (EFI_ERROR (TempStatus)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // Put the data at the appropriate location inside the buffer area
> + CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
> +
> + // Write the modified buffer back to the NorFlash
> + TempStatus = NorFlashWriteBlocks (Instance, Lba, BlockSize,
> + Instance->ShadowBuffer);
> + if (EFI_ERROR (TempStatus)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/*
> + Although DiskIoDxe will automatically install the DiskIO protocol whenever
> + we install the BlockIO protocol, its implementation is sub-optimal as it reads
> + and writes entire blocks using the BlockIO protocol. In fact we can access
> + NOR flash with a finer granularity than that, so we can improve performance
> + by directly producing the DiskIO protocol.
> +*/
> +
> +/**
> + Read BufferSize bytes from Offset into Buffer.
> +
> + @param This Protocol instance pointer.
> + @param MediaId Id of the media, changes every time the media is
> + replaced.
> + @param Offset The starting byte offset to read from
> + @param BufferSize Size of Buffer
> + @param Buffer Buffer containing read data
> +
> + @retval EFI_SUCCESS The data was read correctly from the device.
> + @retval EFI_DEVICE_ERROR The device reported an error while performing
> + the read.
> + @retval EFI_NO_MEDIA There is no media in the device.
> + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
> + @retval EFI_INVALID_PARAMETER The read request contains device addresses that
> + are not valid for the device.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NorFlashDiskIoReadDisk (
> + IN EFI_DISK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN UINT64 DiskOffset,
> + IN UINTN BufferSize,
> + OUT VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + UINT32 BlockSize;
> + UINT32 BlockOffset;
> + EFI_LBA Lba;
> +
> + Instance = INSTANCE_FROM_DISKIO_THIS(This);
> +
> + if (MediaId != Instance->Media.MediaId) {
> + return EFI_MEDIA_CHANGED;
> + }
> +
> + BlockSize = Instance->Media.BlockSize;
> + Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
> +
> + return NorFlashRead (Instance, Lba, BlockOffset, BufferSize, Buffer);
> +}
> +
> +/**
> + Writes a specified number of bytes to a device.
> +
> + @param This Indicates a pointer to the calling context.
> + @param MediaId ID of the medium to be written.
> + @param Offset The starting byte offset on the logical block I/O device to
> + write.
> + @param BufferSize The size in bytes of Buffer. The number of bytes to write
> + to the device.
> + @param Buffer A pointer to the buffer containing the data to be written.
> +
> + @retval EFI_SUCCESS The data was written correctly to the device.
> + @retval EFI_WRITE_PROTECTED The device can not be written to.
> + @retval EFI_DEVICE_ERROR The device reported an error while performing
> + the write.
> + @retval EFI_NO_MEDIA There is no media in the device.
> + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
> + @retval EFI_INVALID_PARAMETER The write request contains device addresses that
> + are not valid for the device.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NorFlashDiskIoWriteDisk (
> + IN EFI_DISK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN UINT64 DiskOffset,
> + IN UINTN BufferSize,
> + IN VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + UINT32 BlockSize;
> + UINT32 BlockOffset;
> + EFI_LBA Lba;
> + UINTN RemainingBytes;
> + UINTN WriteSize;
> + EFI_STATUS Status;
> +
> + Instance = INSTANCE_FROM_DISKIO_THIS(This);
> +
> + if (MediaId != Instance->Media.MediaId) {
> + return EFI_MEDIA_CHANGED;
> + }
> +
> + BlockSize = Instance->Media.BlockSize;
> + Lba = (EFI_LBA) DivU64x32Remainder (DiskOffset, BlockSize, &BlockOffset);
Space after cast.
> +
> + RemainingBytes = BufferSize;
> +
> + // Write either all the remaining bytes, or the number of bytes that bring
> + // us up to a block boundary, whichever is less.
> + // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next
> + // block boundary (even if it is already on one).
> + WriteSize = MIN (RemainingBytes,
> + ((DiskOffset | (BlockSize - 1)) + 1) - DiskOffset);
> +
> + do {
> + if (WriteSize == BlockSize) {
> + // Write a full block
> + Status = NorFlashWriteFullBlock (Instance, Lba, Buffer,
> + BlockSize / sizeof (UINT32));
> + } else {
> + // Write a partial block
> + Status = NorFlashWriteSingleBlock (Instance, Lba, BlockOffset, &WriteSize,
> + Buffer);
> + }
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + // Now continue writing either all the remaining bytes or single blocks.
> + RemainingBytes -= WriteSize;
> + Buffer = (UINT8 *) Buffer + WriteSize;
Space after cast.
> + Lba++;
> + BlockOffset = 0;
> + WriteSize = MIN (RemainingBytes, BlockSize);
> + } while (RemainingBytes);
> +
> + return Status;
> +}
> +
> +STATIC CONST NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
> + NOR_FLASH_SIGNATURE, // Signature
> + NULL, // Handle ... NEED TO BE FILLED
> +
> + FALSE, // Initialized
> + NULL, // Initialize
> +
> + 0, // HostRegisterBaseAddress ... NEED TO BE FILLED
> + 0, // DeviceBaseAddress ... NEED TO BE FILLED
> + 0, // RegionBaseAddress ... NEED TO BE FILLED
> + 0, // Size ... NEED TO BE FILLED
> + 0, // StartLba
> + 0, // OffsetLba
> +
> + {
> + EFI_BLOCK_IO_PROTOCOL_REVISION2, // Revision
> + NULL, // Media ... NEED TO BE FILLED
> + NorFlashBlockIoReset, // Reset;
> + NorFlashBlockIoReadBlocks, // ReadBlocks
> + NorFlashBlockIoWriteBlocks, // WriteBlocks
> + NorFlashBlockIoFlushBlocks // FlushBlocks
> + }, // BlockIoProtocol
> +
> + {
> + 0, // MediaId ... NEED TO BE FILLED
> + FALSE, // RemovableMedia
> + TRUE, // MediaPresent
> + FALSE, // LogicalPartition
> + FALSE, // ReadOnly
> + FALSE, // WriteCaching;
> + 0, // BlockSize ... NEED TO BE FILLED
> + 4, // IoAlign
> + 0, // LastBlock ... NEED TO BE FILLED
> + 0, // LowestAlignedLba
> + 1, // LogicalBlocksPerPhysicalBlock
> + }, //Media;
> +
> + {
> + EFI_DISK_IO_PROTOCOL_REVISION, // Revision
> + NorFlashDiskIoReadDisk, // ReadDisk
> + NorFlashDiskIoWriteDisk // WriteDisk
> + },
> +
> + FALSE, // SupportFvb ... NEED TO BE FILLED
> + {
> + FvbGetAttributes, // GetAttributes
> + FvbSetAttributes, // SetAttributes
> + FvbGetPhysicalAddress, // GetPhysicalAddress
> + FvbGetBlockSize, // GetBlockSize
> + FvbRead, // Read
> + FvbWrite, // Write
> + FvbEraseBlocks, // EraseBlocks
> + NULL, //ParentHandle
> + }, // FvbProtoccol;
> +
> + NULL, // ShadowBuffer
> + {
> + {
> + {
> + HARDWARE_DEVICE_PATH,
> + HW_VENDOR_DP,
> + {
> + (UINT8)sizeof(VENDOR_DEVICE_PATH),
> + (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)
Space after sizeof?
> + }
> + },
> + { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } },
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
> + }
> + } // DevicePath
> +};
> +
> +STATIC
> +EFI_STATUS
> +NorFlashCreateInstance (
> + IN UINTN HostRegisterBase,
> + IN UINTN NorFlashDeviceBase,
> + IN UINTN NorFlashRegionBase,
> + IN UINTN NorFlashSize,
> + IN UINT32 MediaId,
> + IN UINT32 BlockSize,
> + IN BOOLEAN SupportFvb,
> + IN CONST GUID *NorFlashGuid,
> + IN CONST CSDC_DEFINITION *CommandTable,
> + IN UINTN CommandTableSize,
> + OUT NOR_FLASH_INSTANCE** NorFlashInstance
> + )
> +{
> + EFI_STATUS Status;
> + NOR_FLASH_INSTANCE* Instance;
> +
> + ASSERT(NorFlashInstance != NULL);
> +
> + Instance = AllocateRuntimeCopyPool (sizeof mNorFlashInstanceTemplate,
Parentheses with sizeof.
> + &mNorFlashInstanceTemplate);
> + if (Instance == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Instance->HostRegisterBaseAddress = HostRegisterBase;
> + Instance->DeviceBaseAddress = NorFlashDeviceBase;
> + Instance->RegionBaseAddress = NorFlashRegionBase;
> + Instance->Size = NorFlashSize;
> +
> + Instance->BlockIoProtocol.Media = &Instance->Media;
> + Instance->Media.MediaId = MediaId;
> + Instance->Media.BlockSize = BlockSize;
> + Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
Spaces around -.
> + Instance->OffsetLba = (NorFlashRegionBase - NorFlashDeviceBase) / BlockSize;
> +
> + CopyGuid (&Instance->DevicePath.Vendor.Guid, NorFlashGuid);
> +
> + Instance->CmdTable = CommandTable;
> + Instance->CmdTableSize = CommandTableSize;
> +
> + Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);;
Double ;.
> + if (Instance->ShadowBuffer == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + NorFlashReset (Instance);
> + if (SupportFvb) {
> + Instance->SupportFvb = TRUE;
> + Instance->Initialize = NorFlashFvbInitialize;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Instance->Handle,
> + &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
> + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
> + &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + FreePool (Instance);
> + return Status;
> + }
> + } else {
> + Instance->Initialized = TRUE;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Instance->Handle,
> + &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
> + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
> + &gEfiDiskIoProtocolGuid, &Instance->DiskIoProtocol,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + FreePool (Instance);
> + return Status;
> + }
> + }
> +
> + *NorFlashInstance = Instance;
> + return Status;
> +}
> +
> +EFI_STATUS
> +NorFlashReset (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + FIP006_CS_CFG CsCfg;
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashReset()\n"));
> + NOR_FLASH_GET_HOST_REG(Instance, CS_CFG, CsCfg);
Missing space.
> + CsCfg.Reg.MBM = CS_CFG_MBM_SINGLE;
> + CsCfg.Reg.SRAM = CS_CFG_SRAM_RW;
> + NOR_FLASH_SET_HOST_REG(Instance, CS_CFG, CsCfg);
Missing space.
> + NorFlashSetHostCommand (Instance, 0x13);
Magic?
> + NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq);
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Fixup internal data so that EFI can be call in virtual mode.
> + Call the passed in Child Notify event and convert any pointers in
> + lib to virtual mode.
> +
> + @param[in] Event The Event that is being processed
> + @param[in] Context Event Context
> +**/
> +STATIC
> +VOID
> +EFIAPI
> +NorFlashVirtualNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->HostRegisterBaseAddress);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
> +
> + // Convert BlockIo protocol
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
> +
> + // Convert Fvb
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
> + EfiConvertPointer (0x0,
> + (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
> +
> + if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer);
> + }
> +
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->CmdTable);
> + }
> +
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashInitialise (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PHYSICAL_ADDRESS HostRegisterBaseAddress;
> + UINT32 Index;
> + NOR_FLASH_DESCRIPTION* NorFlashDevices;
> + BOOLEAN ContainVariableStorage;
> +
> + // Register HSSPI FIP006 register region
> + HostRegisterBaseAddress = PcdGet32 (PcdFip006DxeRegBaseAddress);
> +
> + Status = gDS->AddMemorySpace (
> + EfiGcdMemoryTypeMemoryMappedIo,
> + HostRegisterBaseAddress, SIZE_4KB,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gDS->SetMemorySpaceAttributes (
> + HostRegisterBaseAddress, SIZE_4KB,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = NorFlashPlatformInitialization ();
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashInitialise: Fail to initialize Nor Flash devices\n"));
> + return Status;
> + }
> +
> + // Initialize NOR flash instances
> + Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n"));
> + return Status;
> + }
> +
> + if (mNorFlashDeviceCount > 1) {
> + DEBUG ((DEBUG_WARN, "%a: device count exceeds 1\n", __FUNCTION__));
> + DEBUG ((DEBUG_WARN, "%a: use only first device\n", __FUNCTION__));
> + mNorFlashDeviceCount = 1;
> + }
> + mNorFlashInstances = AllocateRuntimePool (sizeof(NOR_FLASH_INSTANCE*) *
> + mNorFlashDeviceCount);
> +
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
> + // Check if this NOR Flash device contain the variable storage region
> + ContainVariableStorage =
> + (NorFlashDevices[Index].RegionBaseAddress <=
> + PcdGet32 (PcdFlashNvStorageVariableBase)) &&
> + (PcdGet32 (PcdFlashNvStorageVariableBase) +
> + PcdGet32 (PcdFlashNvStorageVariableSize) <=
> + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
> +
> + Status = NorFlashCreateInstance (
> + HostRegisterBaseAddress,
> + NorFlashDevices[Index].DeviceBaseAddress,
> + NorFlashDevices[Index].RegionBaseAddress,
> + NorFlashDevices[Index].Size,
> + Index,
> + NorFlashDevices[Index].BlockSize,
> + ContainVariableStorage,
> + &NorFlashDevices[Index].Guid,
> + mN25qCSDCDefTable,
> + ARRAY_SIZE (mN25qCSDCDefTable),
> + &mNorFlashInstances[Index]
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR,
> + "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n",
> + Index));
> + }
> + }
> +
> + //
> + // Register for the virtual address change event
> + //
> + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
> + NorFlashVirtualNotifyEvent, NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &mNorFlashVirtualAddrChangeEvent);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
> new file mode 100644
> index 000000000000..ca82bda6dfb7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
> @@ -0,0 +1,305 @@
> +/** @file NorFlashDxe.h
> +
> + Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NOR_FLASH_DXE_H__
> +#define __NOR_FLASH_DXE_H__
> +
> +
> +#include <Base.h>
> +#include <PiDxe.h>
> +
> +#include <Guid/EventGroup.h>
> +
> +#include <Protocol/BlockIo.h>
> +#include <Protocol/DiskIo.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/NorFlashPlatformLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +#include <Library/DxeServicesTableLib.h>
Can these be sorted.
> +
> +#include "Fip006Reg.h"
> +
> +#define NOR_FLASH_ERASE_RETRY 10
Hmm, so we have a define for RETRY but not enable/disable write?
> +
> +#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
Needs additional parentheses around (BaseAddr) and (LbaSize).
> +
> +#define NOR_FLASH_READ_BYTE(Instance, Addr) \
> + (((UINT8*) Instance->RegionBaseAddress + Addr)[0])
(Instance), (Addr)
> +
> +#define NOR_FLASH_WRITE_BYTE(Instance, Addr, Src) \
> + do { \
> + ((UINT8*) Instance->RegionBaseAddress + Addr)[0] = Src; \
(Instance), (Addr)
> + } while (0)
> +
> +#define NOR_FLASH_GET_HOST_REG(Instance, Reg, Dst) \
> + do { \
> + Dst.Raw = MmioRead32(Instance->HostRegisterBaseAddress + FIP006_REG_##Reg); \
(Dst), (Instance)
> + } while (0)
> +
> +#define NOR_FLASH_SET_HOST_REG(Instance, Reg, Src) \
> + do { \
> + MmioWrite32 (Instance->HostRegisterBaseAddress + FIP006_REG_##Reg, Src.Raw); \
(Instance), (Src)
> + } while (0)
> +
> +#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
> +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
> +#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
> +#define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, NOR_FLASH_SIGNATURE)
(a) x3
> +
> +#define CSDC(Data, Cont, Trp, Dec) \
> + ((Data << 8) | (Cont << 3) | (Trp << 1) | Dec)
(Data), (Cont), (Trp), (Dec)
> +#define CSDC_TRP_MBM 0
> +#define CSDC_TRP_DUAL 1
> +#define CSDC_TRP_QUAD 2
> +#define CSDC_TRP_SINGLE 3
> +
> +typedef struct {
> + UINT8 Code;
> + BOOLEAN AddrAccess;
> + BOOLEAN AddrMode4Byte;
> + BOOLEAN HighZ;
> + BOOLEAN ReadWrite;
> + UINT8 CscfgMbm;
> + UINT8 CsdcTrp;
> +} CSDC_DEFINITION;
> +
> +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
> +
> +typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
> +
> +typedef struct {
> + VENDOR_DEVICE_PATH Vendor;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NOR_FLASH_DEVICE_PATH;
> +
> +struct _NOR_FLASH_INSTANCE {
> + UINT32 Signature;
> + EFI_HANDLE Handle;
> +
> + BOOLEAN Initialized;
> + NOR_FLASH_INITIALIZE Initialize;
> +
> + UINTN HostRegisterBaseAddress;
> + UINTN DeviceBaseAddress;
> + UINTN RegionBaseAddress;
> + UINTN Size;
> + EFI_LBA StartLba;
> + EFI_LBA OffsetLba;
> +
> + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
> + EFI_BLOCK_IO_MEDIA Media;
> + EFI_DISK_IO_PROTOCOL DiskIoProtocol;
> +
> + BOOLEAN SupportFvb;
> + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
> + VOID* ShadowBuffer;
> +
> + NOR_FLASH_DEVICE_PATH DevicePath;
> +
> + CONST CSDC_DEFINITION *CmdTable;
> + UINTN CmdTableSize;
> +};
> +
> +EFI_STATUS
> +NorFlashReadCfiData (
> + IN UINTN DeviceBaseAddress,
> + IN UINTN CFI_Offset,
> + IN UINT32 NumberOfBytes,
> + OUT UINT32 *Data
> + );
> +
> +EFI_STATUS
> +NorFlashWriteBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN TargetAddress,
> + IN UINTN BufferSizeInBytes,
> + IN UINT32 *Buffer
> + );
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReset (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN BOOLEAN ExtendedVerification
> + );
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReadBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> +);
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoWriteBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> +);
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoFlushBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This
> +);
> +
> +//
> +// NorFlashFvbDxe.c
> +//
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashFvbInitialize (
> + IN NOR_FLASH_INSTANCE* Instance
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumberOfBlocks
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbRead(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN OUT UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbWrite(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + ...
> + );
> +
> +//
> +// NorFlashDxe.c
> +//
> +
> +EFI_STATUS
> +NorFlashUnlockAndEraseSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN BlockAddress
> + );
> +
> +EFI_STATUS
> +NorFlashWriteSingleBlock (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashWriteBlocks (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashReadBlocks (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashWrite (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashReset (
> + IN NOR_FLASH_INSTANCE *Instance
> + );
> +
> +#endif /* __NOR_FLASH_DXE_H__ */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
> new file mode 100644
> index 000000000000..b63d778d84bc
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
> @@ -0,0 +1,845 @@
> +/*++ @file NorFlashFvbDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + --*/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/PcdLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Guid/VariableFormat.h>
> +#include <Guid/SystemNvDataGuid.h>
Alphabetically sorted?
> +
> +#include "NorFlashDxe.h"
> +
> +STATIC EFI_EVENT mFvbVirtualAddrChangeEvent;
> +STATIC UINTN mFlashNvStorageVariableBase;
> +
> +///
> +/// The Firmware Volume Block Protocol is the low-level interface
> +/// to a firmware volume. File-level access to a firmware volume
> +/// should not be done using the Firmware Volume Block Protocol.
> +/// Normal access to a firmware volume must use the Firmware
> +/// Volume Protocol. Typically, only the file system driver that
> +/// produces the Firmware Volume Protocol will bind to the
> +/// Firmware Volume Block Protocol.
> +///
> +
> +/**
> + Initialises the FV Header and Variable Store Header
> + to support variable operations.
> +
> + @param[in] Ptr - Location to initialise the headers
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitializeFvAndVariableStoreHeaders (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + EFI_STATUS Status;
> + VOID* Headers;
> + UINTN HeadersLength;
> + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
> + VARIABLE_STORE_HEADER *VariableStoreHeader;
> + UINTN BlockSize;
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize (Instance);
> + }
> +
> + HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) +
> + sizeof(EFI_FV_BLOCK_MAP_ENTRY) +
> + sizeof(VARIABLE_STORE_HEADER);
> + Headers = AllocateZeroPool(HeadersLength);
> +
> + BlockSize = Instance->Media.BlockSize;
> +
> + // FirmwareVolumeHeader->FvLength is declared to have the Variable area
> + // AND the FTW working area AND the FTW Spare contiguous.
> + ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) +
> + PcdGet32(PcdFlashNvStorageVariableSize) ==
> + PcdGet32(PcdFlashNvStorageFtwWorkingBase));
> + ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) +
> + PcdGet32(PcdFlashNvStorageFtwWorkingSize) ==
> + PcdGet32(PcdFlashNvStorageFtwSpareBase));
> +
> + // Check if the size of the area is at least one block size
> + ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) &&
> + (PcdGet32(PcdFlashNvStorageVariableSize) / BlockSize > 0));
> + ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingSize) > 0) &&
> + (PcdGet32(PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0));
> + ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) &&
> + (PcdGet32(PcdFlashNvStorageFtwSpareSize) / BlockSize > 0));
> +
> + // Ensure the Variable areas are aligned on block size boundaries
> + ASSERT((PcdGet32(PcdFlashNvStorageVariableBase) % BlockSize) == 0);
> + ASSERT((PcdGet32(PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0);
> + ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0);
Space after ASSERT above?
> +
> + //
> + // EFI_FIRMWARE_VOLUME_HEADER
> + //
> + FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
> + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
> + FirmwareVolumeHeader->FvLength =
> + PcdGet32(PcdFlashNvStorageVariableSize) +
> + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32(PcdFlashNvStorageFtwSpareSize);
Missing space after PcdGet32 (many, above - some, below).
That 4-space indentation does not look accurate.
> + FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
> + FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP |
> + EFI_FVB2_READ_STATUS |
> + EFI_FVB2_STICKY_WRITE |
> + EFI_FVB2_MEMORY_MAPPED |
> + EFI_FVB2_ERASE_POLARITY |
> + EFI_FVB2_WRITE_STATUS |
> + EFI_FVB2_WRITE_ENABLED_CAP;
> +
> + FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) +
> + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
> + FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
> + FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
> + FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
> + FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
> + FirmwareVolumeHeader->BlockMap[1].Length = 0;
> + FirmwareVolumeHeader->Checksum = CalculateCheckSum16 (
> + (UINT16*)FirmwareVolumeHeader,
> + FirmwareVolumeHeader->HeaderLength);
> +
> + //
> + // VARIABLE_STORE_HEADER
> + //
> + VariableStoreHeader = (VOID *)((UINTN)Headers +
> + FirmwareVolumeHeader->HeaderLength);
> + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
> + VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) -
> + FirmwareVolumeHeader->HeaderLength;
> + VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
> + VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
> +
> + // Install the combined super-header in the NorFlash
> + Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
> +
> + FreePool (Headers);
> + return Status;
> +}
> +
> +/**
> + Check the integrity of firmware volume header.
> +
> + @param[in] FwVolHeader - A pointer to a firmware volume header
> +
> + @retval EFI_SUCCESS - The firmware volume is consistent
> + @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
> +
> +**/
> +EFI_STATUS
> +ValidateFvHeader (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + UINT16 Checksum;
> + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
> + VARIABLE_STORE_HEADER *VariableStoreHeader;
> + UINTN VariableStoreLength;
> + UINTN FvLength;
> +
> + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress;
> +
> + FvLength = PcdGet32(PcdFlashNvStorageVariableSize) +
> + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32(PcdFlashNvStorageFtwSpareSize);
Missing space after PcdGet32.
> +
> + //
> + // Verify the header revision, header signature, length
> + // Length of FvBlock cannot be 2**64-1
> + // HeaderLength cannot be an odd number
> + //
> + if ( (FwVolHeader->Revision != EFI_FVH_REVISION)
> + || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
> + || (FwVolHeader->FvLength != FvLength)
Yikes. Move those "||" to preceding lines, please?
> + )
> + {
> + DEBUG ((DEBUG_INFO, "%a: No Firmware Volume header present\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + // Check the Firmware Volume Guid
> + if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) {
> + DEBUG ((DEBUG_INFO, "%a: Firmware Volume Guid non-compatible\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + // Verify the header checksum
> + Checksum = CalculateSum16((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
Missing space after 16.
> + if (Checksum != 0) {
> + DEBUG ((DEBUG_INFO, "%a: FV checksum is invalid (Checksum:0x%X)\n",
> + __FUNCTION__, Checksum));
> + return EFI_NOT_FOUND;
> + }
> +
> + VariableStoreHeader = (VOID *)((UINTN)FwVolHeader +
> + FwVolHeader->HeaderLength);
> +
> + // Check the Variable Store Guid
> + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
> + !CompareGuid (&VariableStoreHeader->Signature,
> + &gEfiAuthenticatedVariableGuid)) {
> + DEBUG ((DEBUG_INFO, "%a: Variable Store Guid non-compatible\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) -
> + FwVolHeader->HeaderLength;
> + if (VariableStoreHeader->Size != VariableStoreLength) {
> + DEBUG ((DEBUG_INFO, "%a: Variable Store Length does not match\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The GetAttributes() function retrieves the attributes and
> + current settings of the block.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
> + current settings are returned.
> + Type EFI_FVB_ATTRIBUTES_2 is defined in
> + EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS(This);
> +
> + FlashFvbAttributes = EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS |
> + EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED |
> + EFI_FVB2_ERASE_POLARITY;
> +
> + // Check if it is write protected
> + if (!Instance->Media.ReadOnly) {
> + FlashFvbAttributes |= EFI_FVB2_WRITE_STATUS | EFI_FVB2_WRITE_ENABLED_CAP;
> + }
> +
> + *Attributes = FlashFvbAttributes;
> +
> + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The SetAttributes() function sets configurable firmware volume attributes
> + and returns the new settings of the firmware volume.
> +
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Attributes On input, Attributes is a pointer to
> + EFI_FVB_ATTRIBUTES_2 that contains the desired
> + firmware volume settings.
> + On successful return, it contains the new
> + settings of the firmware volume.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
> +
> + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with
> + the capabilities as declared in the firmware
> + volume header.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",
> + *Attributes));
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + The GetPhysicalAddress() function retrieves the base address of
> + a memory-mapped firmware volume. This function should be called
> + only for memory-mapped firmware volumes.
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Address Pointer to a caller-allocated
> + EFI_PHYSICAL_ADDRESS that, on successful
> + return from GetPhysicalAddress(), contains the
> + base address of the firmware volume.
> +
> + @retval EFI_SUCCESS The firmware volume base address was returned.
> +
> + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS(This);
Space after "_THIS".
> +
> + DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n",
> + Instance->RegionBaseAddress));
> +
> + ASSERT(Address != NULL);
Space missing.
> +
> + *Address = mFlashNvStorageVariableBase;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The GetBlockSize() function retrieves the size of the requested
> + block. It also returns the number of additional blocks with
> + the identical size. The GetBlockSize() function is used to
> + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
> +
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba Indicates the block whose size to return
> +
> + @param BlockSize Pointer to a caller-allocated UINTN in which
> + the size of the block is returned.
> +
> + @param NumberOfBlocks Pointer to a caller-allocated UINTN in
> + which the number of consecutive blocks,
> + starting with Lba, is returned. All
> + blocks in this range have a size of
> + BlockSize.
> +
> +
> + @retval EFI_SUCCESS The firmware volume base address was returned.
> +
> + @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumberOfBlocks
> + )
> +{
> + EFI_STATUS Status;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS(This);
> +
> + DEBUG ((DEBUG_BLKIO,
> + "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba,
> + Instance->Media.BlockSize, Instance->Media.LastBlock));
> +
> + if (Lba > Instance->Media.LastBlock) {
> + DEBUG ((DEBUG_ERROR,
> + "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n",
> + Lba, Instance->Media.LastBlock));
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + // This is easy because in this platform each NorFlash device has equal sized blocks.
> + *BlockSize = (UINTN) Instance->Media.BlockSize;
> + *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
> +
> + DEBUG ((DEBUG_BLKIO,
> + "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize,
> + *NumberOfBlocks));
> +
> + Status = EFI_SUCCESS;
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Reads the specified number of bytes into a buffer from the specified block.
> +
> + The Read() function reads the requested number of bytes from the
> + requested block and stores them in the provided buffer.
> + Implementations should be mindful that the firmware volume
> + might be in the ReadDisabled state. If it is in this state,
> + the Read() function must return the status code
> + EFI_ACCESS_DENIED without modifying the contents of the
> + buffer. The Read() function must also prevent spanning block
> + boundaries. If a read is requested that would span a block
> + boundary, the read must read up to the boundary but not
> + beyond. The output parameter NumBytes must be set to correctly
> + indicate the number of bytes actually read. The caller must be
> + aware that a read may be partially completed.
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba The starting logical block index from which to read
> +
> + @param Offset Offset into the block at which to begin reading.
> +
> + @param NumBytes Pointer to a UINTN.
> + At entry, *NumBytes contains the total size of the
> + buffer.
> + At exit, *NumBytes contains the total number of
> + bytes read.
> +
> + @param Buffer Pointer to a caller-allocated buffer that will be
> + used to hold the data that is read.
> +
> + @retval EFI_SUCCESS The firmware volume was read successfully, and
> + contents are in Buffer.
> +
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
> + On output, NumBytes contains the total number of
> + bytes returned in Buffer.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
> +
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
> + could not be read.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN OUT UINT8 *Buffer
> + )
> +{
> + EFI_STATUS TempStatus;
> + UINTN BlockSize;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS(This);
> +
> + DEBUG ((DEBUG_BLKIO,
> + "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n",
> + Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize(Instance);
> + }
> +
> + TempStatus = EFI_SUCCESS;
> +
> + // Cache the block size to avoid de-referencing pointers all the time
> + BlockSize = Instance->Media.BlockSize;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n",
> + Offset, *NumBytes, BlockSize ));
> +
> + // The read must not span block boundaries.
> + // We need to check each variable individually because adding two large
> + // values together overflows.
> + if (Offset >= BlockSize ||
> + *NumBytes > BlockSize ||
> + (Offset + *NumBytes) > BlockSize) {
> + DEBUG ((DEBUG_ERROR,
> + "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
> + Offset, *NumBytes, BlockSize ));
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // We must have some bytes to read
> + if (*NumBytes == 0) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + // Decide if we are doing full block reads or not.
> + if (*NumBytes % BlockSize != 0) {
> + TempStatus = NorFlashRead (Instance, Instance->StartLba + Lba, Offset,
> + *NumBytes, Buffer);
> + if (EFI_ERROR (TempStatus)) {
> + return EFI_DEVICE_ERROR;
> + }
> + } else {
> + // Read NOR Flash data into shadow buffer
> + TempStatus = NorFlashReadBlocks (Instance, Instance->StartLba + Lba,
> + BlockSize, Buffer);
> + if (EFI_ERROR (TempStatus)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes the specified number of bytes from the input buffer to the block.
> +
> + The Write() function writes the specified number of bytes from
> + the provided buffer to the specified block and offset. If the
> + firmware volume is sticky write, the caller must ensure that
> + all the bits of the specified range to write are in the
> + EFI_FVB_ERASE_POLARITY state before calling the Write()
> + function, or else the result will be unpredictable. This
> + unpredictability arises because, for a sticky-write firmware
> + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
> + state but cannot flip it back again. Before calling the
> + Write() function, it is recommended for the caller to first call
> + the EraseBlocks() function to erase the specified block to
> + write. A block erase cycle will transition bits from the
> + (NOT)EFI_FVB_ERASE_POLARITY state back to the
> + EFI_FVB_ERASE_POLARITY state. Implementations should be
> + mindful that the firmware volume might be in the WriteDisabled
> + state. If it is in this state, the Write() function must
> + return the status code EFI_ACCESS_DENIED without modifying the
> + contents of the firmware volume. The Write() function must
> + also prevent spanning block boundaries. If a write is
> + requested that spans a block boundary, the write must store up
> + to the boundary but not beyond. The output parameter NumBytes
> + must be set to correctly indicate the number of bytes actually
> + written. The caller must be aware that a write may be
> + partially completed. All writes, partial or otherwise, must be
> + fully flushed to the hardware before the Write() service
> + returns.
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba The starting logical block index to write to.
> +
> + @param Offset Offset into the block at which to begin writing.
> +
> + @param NumBytes The pointer to a UINTN.
> + At entry, *NumBytes contains the total size of the
> + buffer.
> + At exit, *NumBytes contains the total number of
> + bytes actually written.
> +
> + @param Buffer The pointer to a caller-allocated buffer that
> + contains the source for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was written successfully.
> +
> + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
> + On output, NumBytes contains the total number of
> + bytes actually written.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
> +
> + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be
> + written.
> +
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> +
> + return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset,
> + NumBytes, Buffer);
> +}
> +
> +/**
> + Erases and initialises a firmware volume block.
> +
> + The EraseBlocks() function erases one or more blocks as denoted
> + by the variable argument list. The entire parameter list of
> + blocks must be verified before erasing any blocks. If a block is
> + requested that does not exist within the associated firmware
> + volume (it has a larger index than the last block of the
> + firmware volume), the EraseBlocks() function must return the
> + status code EFI_INVALID_PARAMETER without modifying the contents
> + of the firmware volume. Implementations should be mindful that
> + the firmware volume might be in the WriteDisabled state. If it
> + is in this state, the EraseBlocks() function must return the
> + status code EFI_ACCESS_DENIED without modifying the contents of
> + the firmware volume. All calls to EraseBlocks() must be fully
> + flushed to the hardware before the EraseBlocks() service
> + returns.
> +
> + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
> + instance.
> +
> + @param ... The variable argument list is a list of tuples.
> + Each tuple describes a range of LBAs to erase
> + and consists of the following:
> + - An EFI_LBA that indicates the starting LBA
> + - A UINTN that indicates the number of blocks
> + to erase.
> +
> + The list is terminated with an
> + EFI_LBA_LIST_TERMINATOR.
> +
> + @retval EFI_SUCCESS The erase request successfully completed.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> + state.
> +
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> + and could not be written.
> + The firmware device may have been partially
> + erased.
> +
> + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable
> + argument list do not exist in the firmware
> + volume.
> +
> + **/
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + ...
> + )
> +{
> + EFI_STATUS Status;
> + VA_LIST Args;
> + UINTN BlockAddress; // Physical address of Lba to erase
> + EFI_LBA StartingLba; // Lba from which we start erasing
> + UINTN NumOfLba; // Number of Lba blocks to erase
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS(This);
> +
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
> +
> + Status = EFI_SUCCESS;
> +
> + // Detect WriteDisabled state
> + if (Instance->Media.ReadOnly) {
> + // Firmware volume is in WriteDisabled state
> + DEBUG ((DEBUG_ERROR,
> + "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"));
> + return EFI_ACCESS_DENIED;
> + }
> +
> + // Before erasing, check the entire list of parameters to ensure
> + // all specified blocks are valid
> +
> + VA_START (Args, This);
> + do {
> + // Get the Lba from which we start erasing
> + StartingLba = VA_ARG (Args, EFI_LBA);
> +
> + // Have we reached the end of the list?
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
> + //Exit the while loop
> + break;
> + }
> +
> + // How many Lba blocks are we requested to erase?
> + NumOfLba = VA_ARG (Args, UINT32);
> +
> + // All blocks must be within range
> + DEBUG ((DEBUG_BLKIO,
> + "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
> + Instance->StartLba + StartingLba, NumOfLba, Instance->Media.LastBlock));
> + if (NumOfLba == 0 ||
> + (Instance->StartLba + StartingLba + NumOfLba - 1) >
> + Instance->Media.LastBlock) {
> + VA_END (Args);
> + DEBUG ((DEBUG_ERROR,
> + "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"));
> + Status = EFI_INVALID_PARAMETER;
> + goto EXIT;
> + }
> + } while (TRUE);
> + VA_END (Args);
> +
> + //
> + // To get here, all must be ok, so start erasing
> + //
> + VA_START (Args, This);
> + do {
> + // Get the Lba from which we start erasing
> + StartingLba = VA_ARG (Args, EFI_LBA);
> +
> + // Have we reached the end of the list?
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
> + // Exit the while loop
> + break;
> + }
> +
> + // How many Lba blocks are we requested to erase?
> + NumOfLba = VA_ARG (Args, UINT32);
> +
> + // Go through each one and erase it
> + while (NumOfLba > 0) {
> +
> + // Get the physical address of Lba to erase
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress,
> + Instance->StartLba + StartingLba,
> + Instance->Media.BlockSize);
> +
> + // Erase it
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
> + Instance->StartLba + StartingLba, BlockAddress));
> + Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
> + if (EFI_ERROR(Status)) {
> + VA_END (Args);
> + Status = EFI_DEVICE_ERROR;
> + goto EXIT;
> + }
> +
> + // Move to the next Lba
> + StartingLba++;
> + NumOfLba--;
> + }
> + } while (TRUE);
> + VA_END (Args);
> +
> +EXIT:
> + return Status;
> +}
> +
> +/**
> + Fixup internal data so that EFI can be call in virtual mode.
> + Call the passed in Child Notify event and convert any pointers in
> + lib to virtual mode.
> +
> + @param[in] Event The Event that is being processed
> + @param[in] Context Event Context
> +**/
> +STATIC
> +VOID
> +EFIAPI
> +FvbVirtualNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashFvbInitialize (
> + IN NOR_FLASH_INSTANCE* Instance
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 FvbNumLba;
> + EFI_BOOT_MODE BootMode;
> + UINTN RuntimeMmioRegionSize;
> +
> + DEBUG ((DEBUG_BLKIO,"NorFlashFvbInitialize\n"));
> +
> + Instance->Initialized = TRUE;
> + mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
> +
> + // Set the index of the first LBA for the FVB
> + Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) -
> + Instance->RegionBaseAddress) /
> + Instance->Media.BlockSize;
> +
> + BootMode = GetBootModeHob ();
> + if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + // Determine if there is a valid header at the beginning of the NorFlash
> + Status = ValidateFvHeader (Instance);
> + }
> +
> + // Install the Default FVB header if required
> + if (EFI_ERROR(Status)) {
> + // There is no valid header, so time to install one.
> + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
> + DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n",
> + __FUNCTION__));
> +
> + // Erase all the NorFlash that is reserved for variable storage
> + FvbNumLba = (PcdGet32(PcdFlashNvStorageVariableSize) +
> + PcdGet32(PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32(PcdFlashNvStorageFtwSpareSize)) /
> + Instance->Media.BlockSize;
Missing spaces and shaky indentation.
/
Leif
> +
> + Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba,
> + EFI_LBA_LIST_TERMINATOR);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + // Install all appropriate headers
> + Status = InitializeFvAndVariableStoreHeaders (Instance);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> + }
> +
> + //
> + // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
> + //
> + RuntimeMmioRegionSize = Instance->Size;
> +
> + Status = gDS->AddMemorySpace (
> + EfiGcdMemoryTypeMemoryMappedIo,
> + Instance->RegionBaseAddress, RuntimeMmioRegionSize,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gDS->SetMemorySpaceAttributes (
> + Instance->RegionBaseAddress, RuntimeMmioRegionSize,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register for the virtual address change event
> + //
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + FvbVirtualNotifyEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &mFvbVirtualAddrChangeEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH edk2-platforms 14/14] Platform/Synquacer: incorporate NOR flash and variable drivers
2017-09-08 18:23 [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB Ard Biesheuvel
` (12 preceding siblings ...)
2017-09-08 18:23 ` [PATCH edk2-platforms 13/14] Silicon/Socionext: add driver for SPI NOR flash Ard Biesheuvel
@ 2017-09-08 18:23 ` Ard Biesheuvel
2017-09-11 19:13 ` Leif Lindholm
13 siblings, 1 reply; 33+ messages in thread
From: Ard Biesheuvel @ 2017-09-08 18:23 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu, Ard Biesheuvel
Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one, and enabling the prerequisite
FTW and NOR flash drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 32 ++++++++++++++++++--
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 9 ++++--
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c | 10 ++++++
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf | 2 ++
4 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 92c1d3eb8283..11b2e63453cd 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -319,6 +319,19 @@
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+ #
+ # Variable store
+ #
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x54800000
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x08000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x08400000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x08410000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x08420000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
[PcdsDynamicHii]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
@@ -360,7 +373,6 @@
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -378,6 +390,22 @@
}
#
+ # Variable services
+ #
+ Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf {
+ <LibraryClasses>
+ NorFlashPlatformLib|Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ }
+
+ #
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
@@ -481,7 +509,7 @@
#
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
<LibraryClasses>
- #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+ NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
<PcdsFixedAtBuild>
# support ACPI v5.0 or later
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index de97d3e56ded..86685a22208b 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -1,4 +1,3 @@
-
#
# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
# Copyright (c) 2017, Linaro Limited. All rights reserved.
@@ -102,7 +101,6 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -116,6 +114,13 @@ READ_LOCK_STATUS = TRUE
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
#
+ # Variable services
+ #
+ INF Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+ #
# UEFI applications
#
INF ShellPkg/Application/Shell/Shell.inf
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
index 1d25d63f1b6c..1af30a2bbe60 100644
--- a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
@@ -87,6 +87,16 @@ STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
+ // variable store
+ ARM_DEVICE_REGION (FixedPcdGet32 (PcdFip006DxeRegBaseAddress),
+ EFI_PAGE_SIZE),
+ ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageVariableBase),
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize)),
+ ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwWorkingBase),
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)),
+ ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase),
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)),
+
{ }
};
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
index 5f45c30a5e92..044c19ff9600 100644
--- a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
@@ -30,6 +30,7 @@
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Socionext/Synquacer/Synquacer.dec
+ Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
[LibraryClasses]
ArmLib
@@ -48,3 +49,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress
--
2.11.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH edk2-platforms 14/14] Platform/Synquacer: incorporate NOR flash and variable drivers
2017-09-08 18:23 ` [PATCH edk2-platforms 14/14] Platform/Synquacer: incorporate NOR flash and variable drivers Ard Biesheuvel
@ 2017-09-11 19:13 ` Leif Lindholm
0 siblings, 0 replies; 33+ messages in thread
From: Leif Lindholm @ 2017-09-11 19:13 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, methavanitpong.pipat, masahisa.kojima,
masami.hiramatsu
On Fri, Sep 08, 2017 at 07:23:15PM +0100, Ard Biesheuvel wrote:
> Wire up the non-volatile EFI variable store support, by switching from
> the emulation driver to the real one, and enabling the prerequisite
> FTW and NOR flash drivers.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 32 ++++++++++++++++++--
> Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 9 ++++--
> Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c | 10 ++++++
> Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf | 2 ++
> 4 files changed, 49 insertions(+), 4 deletions(-)
>
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index 92c1d3eb8283..11b2e63453cd 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -319,6 +319,19 @@
> #
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
>
> + #
> + # Variable store
> + #
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x54800000
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x08000000
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x08400000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x08410000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x08420000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
> +
> [PcdsDynamicHii]
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
>
> @@ -360,7 +373,6 @@
> MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
>
> @@ -378,6 +390,22 @@
> }
>
> #
> + # Variable services
> + #
> + Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf {
> + <LibraryClasses>
> + NorFlashPlatformLib|Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <LibraryClasses>
> + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> + }
> +
> + #
> # UEFI application (Shell Embedded Boot Loader)
> #
> ShellPkg/Application/Shell/Shell.inf {
> @@ -481,7 +509,7 @@
> #
> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
> <LibraryClasses>
> - #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
>
> <PcdsFixedAtBuild>
> # support ACPI v5.0 or later
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index de97d3e56ded..86685a22208b 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -1,4 +1,3 @@
> -
> #
> # Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> # Copyright (c) 2017, Linaro Limited. All rights reserved.
> @@ -102,7 +101,6 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
>
> @@ -116,6 +114,13 @@ READ_LOCK_STATUS = TRUE
> INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
>
> #
> + # Variable services
> + #
> + INF Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> +
> + #
> # UEFI applications
> #
> INF ShellPkg/Application/Shell/Shell.inf
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> index 1d25d63f1b6c..1af30a2bbe60 100644
> --- a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> @@ -87,6 +87,16 @@ STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
> ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
> SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
>
> + // variable store
> + ARM_DEVICE_REGION (FixedPcdGet32 (PcdFip006DxeRegBaseAddress),
> + EFI_PAGE_SIZE),
> + ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageVariableBase),
> + FixedPcdGet32 (PcdFlashNvStorageVariableSize)),
> + ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwWorkingBase),
> + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)),
> + ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase),
> + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)),
> +
> { }
> };
>
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> index 5f45c30a5e92..044c19ff9600 100644
> --- a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> @@ -30,6 +30,7 @@
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> Silicon/Socionext/Synquacer/Synquacer.dec
> + Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
>
> [LibraryClasses]
> ArmLib
> @@ -48,3 +49,4 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress
> --
> 2.11.0
>
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