From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C9F2820958BD5 for ; Mon, 11 Sep 2017 09:34:43 -0700 (PDT) Received: by mail-wr0-x235.google.com with SMTP id o42so15827796wrb.3 for ; Mon, 11 Sep 2017 09:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=laTIoCgW+kIHku3tbvPCqXLnXhqp8+MbzhIoomiNyKc=; b=IAQiWTrhEseLTULE4814f7fo/mNrvNdmeSorsjuWO/fegsYveP4Hix5DMvdm7i3HrT eMOZn+FFwjM77fnqK4EobIseCbDXq4CzxnQlvW2aBO5SzaUic2qjnG+GnTqt4tYOhOLn NmiOHHKHObkZgJlRgOuPSbRcfFk7NCXUp5Ir0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=laTIoCgW+kIHku3tbvPCqXLnXhqp8+MbzhIoomiNyKc=; b=mkBcZ9mlr8EXDKo4UzyFvuLtvsgIqNKE6hTLK/VK5duD5NraB8cVhQok71IyevL2qA yZDMOjfnt6qNKtTv09GcnQbrkYVFThvvoiim1arstwhIuFtqROwuFW7GYjH7qVO7zs3I cenZSHHwulEeeiWZZkA+DqexgeXlkpgNv8NDYp1yeh4Y3pcf7EaG60v0f/oAT7FKQj7h PrSDbzn+9vX6NxjeKseziRg2NZ3vU0pQK9Yr+BctrXBuxy7zqPMn/uWmWlZCgG1gjdpG MJa1c7BU9y6GzddEubS0IVdGsdCkryPfxWLYok3yNYO6oHHXj97CpKpeKvKeC+eOIQsX 6vFQ== X-Gm-Message-State: AHPjjUgXvfEdkpHCOm7PzVdD7EBWzM5ByOhzJ+cjzJ/HZqJu3Zak/RNz tj5LNgRIuqyOOppHSRkcwA== X-Google-Smtp-Source: ADKCNb7JM3aEDQJ/s+08P4IocSYPsKRRHsvcHfaGjChYeVXwNnQ5FWOLAEumlGif4rFeDQfiNq42yQ== X-Received: by 10.223.150.27 with SMTP id b27mr9050504wra.100.1505147858042; Mon, 11 Sep 2017 09:37:38 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id k141sm4331365wmg.15.2017.09.11.09.37.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 09:37:37 -0700 (PDT) Date: Mon, 11 Sep 2017 17:37:35 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, methavanitpong.pipat@socionext.com, masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20170911163735.7odz2pilwxebdcpo@bivouac.eciton.net> References: <20170908182315.9591-1-ard.biesheuvel@linaro.org> <20170908182315.9591-12-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20170908182315.9591-12-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 11/14] Silicon/Synquacer: add device tree support for eval board X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Sep 2017 16:34:44 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 08, 2017 at 07:23:12PM +0100, Ard Biesheuvel wrote: > Add a device tree description of the Synquacer SoC, and expose it for > the SynquacerEvalBoard platforms. This includes the menu option in the > UEFI boot menu to switch between ACPI and DT. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 9 + > Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 12 + > Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi | 517 ++++++++++++++++++++ > Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts | 21 + > Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf | 28 ++ > 5 files changed, 587 insertions(+) > > diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc > index b2befd2480c4..92c1d3eb8283 100644 > --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc > +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc > @@ -489,3 +489,12 @@ > } > MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf > + > + # > + # DT support > + # > + Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf > + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf { > + > + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf > + } > diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf > index 35742ad5a347..de97d3e56ded 100644 > --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf > +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf > @@ -1,3 +1,4 @@ > + > # > # Copyright (c) 2013-2014, ARM Limited. All rights reserved. > # Copyright (c) 2017, Linaro Limited. All rights reserved. > @@ -190,6 +191,12 @@ READ_LOCK_STATUS = TRUE > INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf > > + # > + # DT support > + # > + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf > + INF RuleOverride = DTB Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf > + > [FV.FVMAIN_COMPACT] > FvAlignment = 8 > ERASE_POLARITY = 1 > @@ -342,3 +349,8 @@ READ_LOCK_STATUS = TRUE > RAW ACPI |.acpi > RAW ASL |.aml > } > + > +[Rule.Common.USER_DEFINED.DTB] > + FILE FREEFORM = $(NAMED_GUID) { > + RAW BIN |.dtb > + } > diff --git a/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi > new file mode 100644 > index 000000000000..8142bcc6adc8 > --- /dev/null > +++ b/Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi > @@ -0,0 +1,517 @@ > +/** @file > + * Copyright (c) 2017, Linaro Limited. All rights reserved. > + * > + * This program and the accompanying materials are licensed and made > + * available under the terms and conditions of the BSD License which > + * accompanies this distribution. The full text of the license may be > + * found at http://opensource.org/licenses/bsd-license.php > + * > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > + * IMPLIED. > + */ > + > +#define GIC_SPI 0 > +#define GIC_PPI 1 > + > +#define IRQ_TYPE_NONE 0 > +#define IRQ_TYPE_EDGE_RISING 1 > +#define IRQ_TYPE_EDGE_FALLING 2 > +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) > +#define IRQ_TYPE_LEVEL_HIGH 4 > +#define IRQ_TYPE_LEVEL_LOW 8 > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; > + > + aliases { > + serial0 = &soc_uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x0>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x1>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU2: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x100>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU3: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x101>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU4: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x200>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU5: cpu@201 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x201>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU6: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x300>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU7: cpu@301 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x301>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU8: cpu@400 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x400>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU9: cpu@401 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x401>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU10: cpu@500 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x500>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU11: cpu@501 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x501>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU12: cpu@600 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x600>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU13: cpu@601 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x601>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU14: cpu@700 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x700>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU15: cpu@701 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x701>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU16: cpu@800 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x800>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU17: cpu@801 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x801>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU18: cpu@900 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x900>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU19: cpu@901 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0x901>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU20: cpu@a00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0xa00>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU21: cpu@a01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0xa01>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU22: cpu@b00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0xb00>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + CPU23: cpu@b01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53","arm,armv8"; > + reg = <0xb01>; > + enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + core1 { > + cpu = <&CPU1>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&CPU2>; > + }; > + core1 { > + cpu = <&CPU3>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&CPU4>; > + }; > + core1 { > + cpu = <&CPU5>; > + }; > + }; > + cluster3 { > + core0 { > + cpu = <&CPU6>; > + }; > + core1 { > + cpu = <&CPU7>; > + }; > + }; > + cluster4 { > + core0 { > + cpu = <&CPU8>; > + }; > + core1 { > + cpu = <&CPU9>; > + }; > + }; > + cluster5 { > + core0 { > + cpu = <&CPU10>; > + }; > + core1 { > + cpu = <&CPU11>; > + }; > + }; > + cluster6 { > + core0 { > + cpu = <&CPU12>; > + }; > + core1 { > + cpu = <&CPU13>; > + }; > + }; > + cluster7 { > + core0 { > + cpu = <&CPU14>; > + }; > + core1 { > + cpu = <&CPU15>; > + }; > + }; > + cluster8 { > + core0 { > + cpu = <&CPU16>; > + }; > + core1 { > + cpu = <&CPU17>; > + }; > + }; > + cluster9 { > + core0 { > + cpu = <&CPU18>; > + }; > + core1 { > + cpu = <&CPU19>; > + }; > + }; > + cluster10 { > + core0 { > + cpu = <&CPU20>; > + }; > + core1 { > + cpu = <&CPU21>; > + }; > + }; > + cluster11 { > + core0 { > + cpu = <&CPU22>; > + }; > + core1 { > + cpu = <&CPU23>; > + }; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "arm,psci"; > + > + CPU_SLEEP_0: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010000>; > + entry-latency-us = <300>; > + exit-latency-us = <1200>; > + min-residency-us = <2000>; > + local-timer-stop; > + }; > + > + CLUSTER_SLEEP_0: cluster-sleep-0 { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x1010000>; > + entry-latency-us = <400>; > + exit-latency-us = <1200>; > + min-residency-us = <2500>; > + local-timer-stop; > + }; > + }; > + > + gic: interrupt-controller@30000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x30000000 0x0 0x10000>, // GICD > + <0x0 0x30400000 0x0 0x300000>, // GICR > + <0x0 0x2c000000 0x0 0x2000>, // GICC > + <0x0 0x2c010000 0x0 0x1000>, // GICH > + <0x0 0x2c020000 0x0 0x2000>; // GICV > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + interrupts = ; > + > + its: gic-its@30020000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0x30020000 0x0 0x20000>; > + #msi-cells = <1>; > + msi-controller; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , // secure > + , // non-secure > + , // virtual > + ; // HYP > + }; > + > + mmio-timer@2a810000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x2a810000 0x0 0x10000>; > + clock-frequency = <100000000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + frame@2a830000 { > + frame-number = <0>; > + interrupts = ; > + reg = <0x0 0x2a830000 0x0 0x10000>; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + mailbox: mhu@45000000 { > + compatible = "arm,mhu", "arm,primecell"; > + reg = <0x0 0x45000000 0x0 0x1000>; > + interrupts = , > + ; /* Non-Sec */ > + interrupt-names = "mhu_lpri_rx", "mhu_hpri_rx"; > + #mbox-cells = <1>; > + clocks = <&clk_apb>; > + clock-names = "apb_pclk"; > + }; > + > + sram: sram@45200000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x45200000 0x0 0x200>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x45200000 0x200>; > + > + cpu_scp_hpri: scp-shmem@0 { > + reg = <0x0 0x200>; > + }; > + }; > + > + scpi { > + compatible = "arm,scpi"; > + mboxes = <&mailbox 1>; > + shmem = <&cpu_scp_hpri>; > + }; > + > + clk_uart: refclk62500khz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <62500000>; > + clock-output-names = "uartclk"; > + }; > + > + clk_apb: refclk100mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + clock-output-names = "apb_pclk"; > + }; > + > + soc_uart0: uart@2a400000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x0 0x2a400000 0x0 0x1000>; > + interrupts = ; > + clocks = <&clk_uart &clk_apb>; > + clock-names = "uartclk", "apb_pclk"; > + }; > + > + clk_netsec: refclk125mhz { > + compatible = "fixed-clock"; > + clock-frequency = <125000000>; > + #clock-cells = <0>; > + }; > + > + eth0: netsec@522D0000 { > + compatible = "socionext,netsecv5"; > + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; > + interrupts = ; > + clocks = <&clk_netsec>; > + phy-mode = "rgmii"; > + max-speed = <1000>; > + max-frame-size = <9000>; > + phy-handle = <ðphy0>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@1 { > + device_type = "ethernet-phy"; > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > + }; > + > + smmu: iommu@582c0000 { > + compatible = "arm,mmu-500", "arm,smmu-v2"; > + reg = <0x0 0x582c0000 0x0 0x10000>; > + #global-interrupts = <1>; > + interrupts = , > + , > + ; > + #iommu-cells = <1>; > + status = "disabled"; > + }; > + > + pcie0: pcie@60000000 { > + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; > + device_type = "pci"; > + reg = <0x0 0x60000000 0x0 0x7f00000>; > + bus-range = <0x0 0x7e>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>, > + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>, > + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>; > + > + #interrupt-cells = <0x1>; > + interrupt-map-mask = <0x0 0x0 0x0 0x0>; > + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; > + > + /* Synquacer SoC supports ITS device ID 0 only */ > + msi-map-mask = <0x0>; > + msi-map = <0x0 &its 0x0 0x1>; > + dma-coherent; > + }; > + > + pcie1: pcie@70000000 { > + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; > + device_type = "pci"; > + reg = <0x0 0x70000000 0x0 0x7f00000>; > + bus-range = <0x0 0x7e>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, > + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, > + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; > + > + #interrupt-cells = <0x1>; > + interrupt-map-mask = <0x0 0x0 0x0 0x0>; > + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; > + > + /* Synquacer SoC supports ITS device ID 0 only */ > + msi-map-mask = <0x0>; > + msi-map = <0x0 &its 0x0 0x1>; > + dma-coherent; > + }; > +}; > diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts > new file mode 100644 > index 000000000000..0e46d2979128 > --- /dev/null > +++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts > @@ -0,0 +1,21 @@ > +/** @file > + * Copyright (c) 2017, Linaro Limited. All rights reserved. > + * > + * This program and the accompanying materials are licensed and made > + * available under the terms and conditions of the BSD License which > + * accompanies this distribution. The full text of the license may be > + * found at http://opensource.org/licenses/bsd-license.php > + * > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > + * IMPLIED. > + */ > + > +/dts-v1/; > + > +#include "Synquacer.dtsi" > + > +/ { > + model = "Synquacer Evaluation Board"; > + compatible = "socionext,synquacer-eval-board", "socionext,synquacer"; > +}; > diff --git a/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf > new file mode 100644 > index 000000000000..4ca35c5f1d78 > --- /dev/null > +++ b/Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf > @@ -0,0 +1,28 @@ > +## @file > +# > +# Device tree description of the Synquacer platform > +# > +# Copyright (c) 2017, Linaro Ltd. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010019 > + BASE_NAME = SynquacerDeviceTree > + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid > + MODULE_TYPE = USER_DEFINED > + VERSION_STRING = 1.0 > + > +[Sources] > + SynquacerEvalBoard.dts > + > +[Packages] > + MdePkg/MdePkg.dec > -- > 2.11.0 >