From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CDC9C21E87976 for ; Thu, 14 Sep 2017 09:08:29 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.33.90]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8EGBQai020049; Thu, 14 Sep 2017 17:11:26 +0100 From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Leif Lindholm , Matteo Carlini Date: Thu, 14 Sep 2017 17:11:21 +0100 Message-Id: <20170914161121.3160-1-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 Subject: [PATCH] ArmPkg: ARM v8.2 updates for detecting FP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Sep 2017 16:08:30 -0000 From: Sami Mujawar The ARMv8.2-FP16 extension introduces support for half precision floating point and the processor ID registers have been updated to enable detection of the implementation. The possible values for the FP bits in ID_AA64PFR0_EL1[19:16] are: - 0000 : Floating-point is implemented. - 0001 : Floating-point including Half-precision support is implemented. - 1111 : Floating-point is not implemented. - All other values are reserved. Previously ArmEnableVFP() compared the FP bits with 0000b to see if the FP was implemented, before enabling FP. Modified this check to enable the FP if the FP bits 19:16 are not 1111b. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar Signed-off-by: Evan Lloyd --- ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index dde6a756528f3abf1bd5a142448e42122a9bd8fa..2d136d242b943fe2f365bc824953b7fe10c944b7 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved. # Copyright (c) 2016, Linaro Limited. All rights reserved. # # This program and the accompanying materials @@ -403,9 +403,11 @@ ASM_FUNC(ArmEnableVFP) mov x1, x30 // Save LR bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0) mov x30, x1 // Restore LR - ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation - cmp x0, #0 // VFP is implemented if '0'. - b.ne 4f // Exit if VFP not implemented. + ubfx x0, x0, #16, #4 // Extract the FP bits 16:19 + cmp x0, #0xF // Check if FP bits are '1111b', + // i.e. Floating Point not implemented + b.eq 4f // Exit when VFP is not implemented. + // FVP is implemented. // Make sure VFP exceptions are not trapped (to any exception level). mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")