From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 24A6921D492C5 for ; Fri, 15 Sep 2017 09:03:10 -0700 (PDT) Received: by mail-wr0-x235.google.com with SMTP id m18so2203615wrm.2 for ; Fri, 15 Sep 2017 09:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EkeUIxCzCKTif+sJ9qQA+qYicmIpT7bYP38RM5mJ9YM=; b=KSU4mm/o+U3S/zbFIXQEJjCTm1LFvyvQnTT2c7jFPRokjgAn1q1R5H/8VkO2dxrTPd i5hGWejtCr9BHdWMQM21XqLkFxvdj2859F0vrP3Jl6g9ulYUJCFFPO5HgZHnKpj/+aV6 Fmjf8KSfTHLo6qZJlf98Zys9hosDfI23L/Sfg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EkeUIxCzCKTif+sJ9qQA+qYicmIpT7bYP38RM5mJ9YM=; b=ZdsDq2WA4WKTg4BdqatRWNp7fdwil5vlU1ezMRmrXJqTwEttwuVf2u92tIATIjChOk AMuLJC17XVLBt2c2yFjIujk9wgUsEwle2CFv8tXNJgiw+PBbXSBicfekfhg8yDGCCbZX vQ3XCAVn6bpQYYuteG1aRcFjUmgWtUkD6m8c8ro2jn6b04vXOyJriZidjJlUfaDkZWlp +HyNj2SQPW11270M0ku5Iz3NdBpXoWlPu37jS+lXEn4cH2/+2+p3h3GBjz1uETyVHmsj 5sY4Kw2TrT5XtH9eWUd6iA+GQHngAtqKfBPleTrcF48LsLWsDB9dPqVwvOKaE/L4zQve yPvg== X-Gm-Message-State: AHPjjUjgjBLNUfsl/ShlgDkvyss7j6njH+6POveB8FbdYNlgWKN7nVmZ LQvG6J3CBeLP/zlI X-Google-Smtp-Source: AOwi7QBl7Y3r1zY40jD6wfLCHRlgxyCf2oWNKyVPQe+fHdxBVSEfWMPQw4xtIGcy/1UKpvZ3sQpJGA== X-Received: by 10.223.186.202 with SMTP id w10mr2158635wrg.132.1505491569020; Fri, 15 Sep 2017 09:06:09 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 77sm1275474wmt.16.2017.09.15.09.06.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Sep 2017 09:06:07 -0700 (PDT) Date: Fri, 15 Sep 2017 17:06:05 +0100 From: Leif Lindholm To: evan.lloyd@arm.com Cc: edk2-devel@lists.01.org, Ard Biesheuvel , Matteo Carlini , Sami Mujawar Message-ID: <20170915160605.inw32x6vhgnkgseu@bivouac.eciton.net> References: <20170914161121.3160-1-evan.lloyd@arm.com> MIME-Version: 1.0 In-Reply-To: <20170914161121.3160-1-evan.lloyd@arm.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] ArmPkg: ARM v8.2 updates for detecting FP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Sep 2017 16:03:10 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 14, 2017 at 05:11:21PM +0100, evan.lloyd@arm.com wrote: > From: Sami Mujawar I have fixed Sami's email address up before pushing. > The ARMv8.2-FP16 extension introduces support for half precision > floating point and the processor ID registers have been updated to > enable detection of the implementation. > > The possible values for the FP bits in ID_AA64PFR0_EL1[19:16] are: > - 0000 : Floating-point is implemented. > - 0001 : Floating-point including Half-precision support is > implemented. > - 1111 : Floating-point is not implemented. > - All other values are reserved. > > Previously ArmEnableVFP() compared the FP bits with 0000b to see if > the FP was implemented, before enabling FP. Modified this check to > enable the FP if the FP bits 19:16 are not 1111b. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sami Mujawar > Signed-off-by: Evan Lloyd So ... I think longer-term we should try to move a lot of this type of stuff to c instead, but this is a clear fix - thanks! Reviewed-by: Leif Lindholm Pushed as 2f16993c25 > --- > ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > index dde6a756528f3abf1bd5a142448e42122a9bd8fa..2d136d242b943fe2f365bc824953b7fe10c944b7 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > @@ -1,7 +1,7 @@ > #------------------------------------------------------------------------------ > # > # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
> -# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. > +# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved. > # Copyright (c) 2016, Linaro Limited. All rights reserved. > # > # This program and the accompanying materials > @@ -403,9 +403,11 @@ ASM_FUNC(ArmEnableVFP) > mov x1, x30 // Save LR > bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0) > mov x30, x1 // Restore LR > - ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation > - cmp x0, #0 // VFP is implemented if '0'. > - b.ne 4f // Exit if VFP not implemented. > + ubfx x0, x0, #16, #4 // Extract the FP bits 16:19 > + cmp x0, #0xF // Check if FP bits are '1111b', > + // i.e. Floating Point not implemented > + b.eq 4f // Exit when VFP is not implemented. > + > // FVP is implemented. > // Make sure VFP exceptions are not trapped (to any exception level). > mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR) > -- > Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") >