From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A58B521CEB108 for ; Tue, 19 Sep 2017 12:15:19 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2F01180468; Tue, 19 Sep 2017 19:18:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2F01180468 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-37.rdu2.redhat.com [10.10.120.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 059305D6A4; Tue, 19 Sep 2017 19:18:21 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Aleksei Kovura , Gerd Hoffmann , Igor Mammedov , Jordan Justen , Ruiyu Ni Date: Tue, 19 Sep 2017 21:18:13 +0200 Message-Id: <20170919191815.3004-2-lersek@redhat.com> In-Reply-To: <20170919191815.3004-1-lersek@redhat.com> References: <20170919191815.3004-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 19 Sep 2017 19:18:24 +0000 (UTC) Subject: [PATCH 1/3] OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Sep 2017 19:15:19 -0000 * Introduce the PIIX4_PAM* and MCH_PAM* macros under "OvmfPkg/Include/IndustryStandard". These macros capture the PAM register offsets (in PCI config space) on the respective Memory Controller B/D/F, from the respective data sheets. * Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases, the B/D/F is 0/0/0. * Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new field contains the return value of the PCI_LIB_ADDRESS() macro. * Under CsmSupportLib, replace the "mRegisterValues440" elements as follows: REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData --> PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData * Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as follows: REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData --> DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData * Under CsmSupportLib, update the register address calculations as follows (for all of PciOr8(), PciAnd8() and PciRead8()): PCI_LIB_ADDRESS ( PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset ) --> mRegisterValues[Index].PAMRegPciLibAddress * Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros. Technically speaking, these changes could be split into three patches (IndustryStandard macro additions, CsmSupportLib code updates, CsmSupportLib macro removals). However, the patch is not big, and in this case it is actually helpful to present the code movement / refactoring in one step, for easier verification. Cc: Aleksei Kovura Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugs.launchpad.net/qemu/+bug/1715700 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 22 +------ OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++ OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 8 +++ OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 62 ++++++++++---------- 4 files changed, 53 insertions(+), 52 deletions(-) diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h index f755a2a359e5..01d3109a7d7d 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h @@ -30,26 +30,6 @@ #include #include -#define PAM_PCI_BUS 0 -#define PAM_PCI_DEV 0 -#define PAM_PCI_FUNC 0 - -#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0 -#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1 -#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2 -#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3 -#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4 -#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5 -#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6 - -#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0 -#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1 -#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2 -#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3 -#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4 -#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5 -#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6 - #define PAM_BASE_ADDRESS 0xc0000 #define PAM_LIMIT_ADDRESS BASE_1MB @@ -67,7 +47,7 @@ typedef struct { // Provides a map of the PAM registers and bits used to set Read/Write access. // typedef struct { - UINT8 PAMRegOffset; + UINTN PAMRegPciLibAddress; UINT8 ReadEnableData; UINT8 WriteEnableData; } PAM_REGISTER_VALUE; diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h index baa4c063f16a..efe6e5c27834 100644 --- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -27,6 +27,19 @@ // #define INTEL_82441_DEVICE_ID 0x1237 +// +// B/D/F/Type: 0/0/0/PCI +// +#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) + +#define PIIX4_PAM0 0x59 +#define PIIX4_PAM1 0x5A +#define PIIX4_PAM2 0x5B +#define PIIX4_PAM3 0x5C +#define PIIX4_PAM4 0x5D +#define PIIX4_PAM5 0x5E +#define PIIX4_PAM6 0x5F + // // B/D/F/Type: 0/1/3/PCI // diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 68485bec71f7..193a262e5b54 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -47,6 +47,14 @@ #define MCH_PCIEXBAR_HIGH 0x64 #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 +#define MCH_PAM0 0x90 +#define MCH_PAM1 0x91 +#define MCH_PAM2 0x92 +#define MCH_PAM3 0x93 +#define MCH_PAM4 0x94 +#define MCH_PAM5 0x95 +#define MCH_PAM6 0x96 + #define MCH_SMRAM 0x9D #define MCH_SMRAM_D_LCK BIT4 #define MCH_SMRAM_G_SMRAME BIT3 diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c index 8d5d2e58a994..c13d4bb88f47 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c @@ -52,35 +52,35 @@ STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = { }; STATIC PAM_REGISTER_VALUE mRegisterValues440[] = { - {REG_PAM1_OFFSET_440, 0x01, 0x02}, - {REG_PAM1_OFFSET_440, 0x10, 0x20}, - {REG_PAM2_OFFSET_440, 0x01, 0x02}, - {REG_PAM2_OFFSET_440, 0x10, 0x20}, - {REG_PAM3_OFFSET_440, 0x01, 0x02}, - {REG_PAM3_OFFSET_440, 0x10, 0x20}, - {REG_PAM4_OFFSET_440, 0x01, 0x02}, - {REG_PAM4_OFFSET_440, 0x10, 0x20}, - {REG_PAM5_OFFSET_440, 0x01, 0x02}, - {REG_PAM5_OFFSET_440, 0x10, 0x20}, - {REG_PAM6_OFFSET_440, 0x01, 0x02}, - {REG_PAM6_OFFSET_440, 0x10, 0x20}, - {REG_PAM0_OFFSET_440, 0x10, 0x20} + {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20} }; STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = { - {REG_PAM1_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM1_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM2_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM2_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM3_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM3_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM4_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM4_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM5_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM5_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM6_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM6_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM0_OFFSET_Q35, 0x10, 0x20} + {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20} }; STATIC PAM_REGISTER_VALUE *mRegisterValues; @@ -145,12 +145,12 @@ LegacyRegionManipulationInternal ( if (ReadEnable != NULL) { if (*ReadEnable) { PciOr8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, mRegisterValues[Index].ReadEnableData ); } else { PciAnd8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, (UINT8) (~mRegisterValues[Index].ReadEnableData) ); } @@ -158,12 +158,12 @@ LegacyRegionManipulationInternal ( if (WriteEnable != NULL) { if (*WriteEnable) { PciOr8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, mRegisterValues[Index].WriteEnableData ); } else { PciAnd8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, (UINT8) (~mRegisterValues[Index].WriteEnableData) ); } @@ -204,7 +204,7 @@ LegacyRegionGetInfoInternal ( // *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]); for (Index = 0; Index < *DescriptorCount; Index++) { - PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset)); + PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress); mSectionArray[Index].ReadEnabled = FALSE; if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) { mSectionArray[Index].ReadEnabled = TRUE; -- 2.14.1.3.gb7cf6e02401b