From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BFE7621ECCB1B for ; Wed, 20 Sep 2017 08:05:37 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 20 Sep 2017 08:08:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,421,1500966000"; d="scan'208";a="137532692" Received: from zwei4-mobl1.ccr.corp.intel.com ([10.255.29.9]) by orsmga002.jf.intel.com with ESMTP; 20 Sep 2017 08:08:40 -0700 From: zwei4 To: edk2-devel@lists.01.org Date: Wed, 20 Sep 2017 23:08:34 +0800 Message-Id: <20170920150834.1864-1-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Calibrate PMIC IMON. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Sep 2017 15:05:38 -0000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- .../PlatformPostMemPei/PlatformInit.c | 76 ++++++++++++++++++++++ .../PlatformSettings/PlatformSetupDxe/UnCore.vfi | 6 +- .../BroxtonSiPkg/NorthCluster/Include/SaRegs.h | 8 ++- 3 files changed, 86 insertions(+), 4 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c index bfed3bf1a..66b0e49f4 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPei/PlatformInit.c @@ -311,6 +311,80 @@ BXTPolicyInit ( return EFI_SUCCESS; } +VOID +ConfigurePmicIMON ( + VOID + ) +{ + UINTN PciD0F0RegBase = 0; + UINTN MchBar = 0; + UINT32 Data; + UINT16 StallCount; + UINT64 PkgPwrSKU; + + PciD0F0RegBase = MmPciAddress (0,SA_MC_BUS,SA_MC_DEV,SA_MC_FUN,0); + MchBar = MmioRead32 (PciD0F0RegBase + R_SA_MCHBAR_REG) &~BIT0; + PkgPwrSKU = AsmReadMsr64 (MSR_PACKAGE_POWER_SKU); + + StallCount = 0; + while (StallCount < 1000) { + Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE); + if ((Data & BIT31) == BIT31) { + MicroSecondDelay (1); + } else { + break; + } + StallCount++; + } + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xfa0d04a4); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000011d); + + StallCount = 0; + while (StallCount < 1000) { + Data = MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE); + if ((Data & BIT31) == BIT31) { + MicroSecondDelay (1); + } else { + break; + } + StallCount++; + } + + if ((PkgPwrSKU & 0x07FFF) >= 0x0903){ + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xe8330466); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d); + } else { + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xed3303b3); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d); + } + +} /** Platform Init PEI module entry point @@ -363,6 +437,8 @@ PlatformInitEntryPoint ( } PWM_Fan_Start (); + + ConfigurePmicIMON(); // // Initialize PlatformInfo HOB diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi index 32eea2005..f8b4b47ec 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/UnCore.vfi @@ -1,7 +1,7 @@ // /** @file // UnCore Setup formset. // -// Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+// Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the BSD License @@ -104,8 +104,8 @@ form formid = UNCORE_FORM_ID, oneof varid = Setup.EnableRenderStandby, prompt = STRING_TOKEN(STR_VIDEO_RS2_PROMPT), help = STRING_TOKEN(STR_VIDEO_RS2_HELP), - option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED; - option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED; + option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED; + option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED; endoneof; oneof varid = Setup.GTTSize, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h index 5dd844092..e985e75c4 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h @@ -15,7 +15,7 @@ Registers / bits of new devices introduced in a SA generation will be just named as "_SA_" without [generation_name] inserted. - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -59,6 +59,12 @@ #define R_SA_MC_CAPID0_B 0xE8 #define R_SA_MCHBAR_REG 0x48 +// +// IA-Punit Mailbox on MCH BAR +// +#define R_BIOS_MAILBOX_DATA 0x7080 +#define R_BIOS_MAILBOX_INTERFACE 0x7084 + // // Silicon Steppings // -- 2.14.1.windows.1