From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22f.google.com (mail-wm0-x22f.google.com [IPv6:2a00:1450:400c:c09::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8C72021E1B762 for ; Thu, 21 Sep 2017 05:37:49 -0700 (PDT) Received: by mail-wm0-x22f.google.com with SMTP id q124so1471236wmb.0 for ; Thu, 21 Sep 2017 05:40:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=gZ8vJuHaWaqnY/z17fKxpZI4VBHAD8+1EGCwweS68AU=; b=dH96bQ0SGrCb94Gxy0AgC2WuyogiFk8JhUHq3eKB7VVwjSrg3PYPEVdlq3UNWByOT1 OK3Zf0uTJ9fxDr9hC5kWRDBt6SlgCYerMxwgRaitnYp5WUq2Lw9a4Ztv8xDSUtp47qpa wO6FuHXMQ4BlYsSve4hFdruDsbkPotzhCY1Xo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=gZ8vJuHaWaqnY/z17fKxpZI4VBHAD8+1EGCwweS68AU=; b=AUt86U2wU5Ov3zcnZSQVNX9DdjaPyCOGPl5nzNp5/YlmkpvohJPyIn3M9sBLJ3TJMI knOtcq3kmm4Ddg9O2wVChsALEWbGaHQm2DYBY253rZXqLPa6GKO6fzPF+s4qStZGU0Di 87s05RnJ7NTPA3gc3v3ctYyNCHFWEyldPEAjNHw3Wvwb7EiHKYiEfrfnNBmp8Xjifw1a CP3vm/ZvS9pLUwhVsexBAGbV0Vdl056JLGx44U+o71lbaDbgit/hDo9gbfRXIkZMKsVD uTBaMgTMg16k4DH8HA3CyyUnCpxGkuHkaXfv9TKLQZwASlbdC3RVBtxVVn2wjy31clk5 58og== X-Gm-Message-State: AHPjjUhBQWE2ZLnqL7jT9VXVOUDROJUvRP7nBODG12fSGO/coTDRxr4+ VbG0WHAH3Ujt0FgJZ8+uqbXQ+A== X-Google-Smtp-Source: AOwi7QAVaVxNIRixzWjqMgIqs7+9zuxjtWYpI+o5tml+Xoc5rx8g5MGdbIGaM4kJdz96oiLeQk4CsQ== X-Received: by 10.28.31.140 with SMTP id f134mr825492wmf.81.1505997654644; Thu, 21 Sep 2017 05:40:54 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b47sm1767203wra.73.2017.09.21.05.40.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Sep 2017 05:40:53 -0700 (PDT) Date: Thu, 21 Sep 2017 13:40:52 +0100 From: Leif Lindholm To: Heyi Guo Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com Message-ID: <20170921124051.n2atbde3ubtpjivb@bivouac.eciton.net> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> MIME-Version: 1.0 In-Reply-To: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 12:37:50 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 21, 2017 at 06:59:39PM +0800, Heyi Guo wrote: > Code can also be found in github: > https://github.com/hisilicon/OpenPlatformPkg.git > branch: rp-1710-platforms-v3 rp-1710-osi-v3 This is looking a lot better, thanks. But it could be useful to have a separate cover letter for the edk2-non-osi patches. > Note: If occurs BIOS boot hang up issue, please revert below commit to fix: > "2f03dc8" Can you give more information? 2f03dc8 is "Silicon/Hisilicon: switch to NonDiscoverable driver for EHCI". / Leif > Chenhui Sun (1): > Hisilicon/D03: Disable the function of PerfTuning > > Heyi Guo (4): > Hisilicon/D05: Modify dsc and fdf file > Hisilicon/D03: Modify dsc and fdf file > Hisilicon: Fix the drivers use the same GUID issue > Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase > > Ming Huang (4): > Hisilicon D03/D05: get firmware version from FIRMWARE_VER > D05/ACPI: Disable D05 SAS0 and SAS2 > D05/ACPI: Modify I2C device > Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. > > huangming (2): > Hisilicon/D05/Pcie: fix bug of size definition > D05/PCIe: Modify PcieRegionBase of secondary chip > > Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- > Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- > Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- > Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- > Platform/Hisilicon/D03/D03.dsc | 13 ++- > Platform/Hisilicon/D03/D03.fdf | 5 +- > Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- > Platform/Hisilicon/D05/D05.dsc | 83 +++++++++-------- > Platform/Hisilicon/D05/D05.fdf | 4 +- > Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- > Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- > Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++---- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++- > Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +---- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++ > Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +- > Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- > Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- > Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- > 24 files changed, 205 insertions(+), 105 deletions(-) > > -- > 1.9.1 >