From: Leif Lindholm <leif.lindholm@linaro.org>
To: Heyi Guo <heyi.guo@linaro.org>
Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org,
graeme.gregory@linaro.org, ard.biesheuvel@linaro.org,
guoheyi@huawei.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com
Subject: Re: [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
Date: Thu, 21 Sep 2017 13:57:31 +0100 [thread overview]
Message-ID: <20170921125731.kesnfqddogo2g2ht@bivouac.eciton.net> (raw)
In-Reply-To: <1505991597-52989-11-git-send-email-heyi.guo@linaro.org>
On Thu, Sep 21, 2017 at 06:59:49PM +0800, Heyi Guo wrote:
> Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++--------
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++--
> 2 files changed, 35 insertions(+), 17 deletions(-)
>
> diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
> index a970da6..e3d3988 100644
> --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
> +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
> @@ -1410,9 +1410,8 @@ SetResource(
> Ptr->ResType = 1;
> Ptr->GenFlag = 0;
> Ptr->SpecificFlag = 0;
> - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
> - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
> - (RootBridgeInstance->MemBase & 0xFFFFFFFF);
> + /* PCIE Device Iobar address should be based on IoBase */
> + Ptr->AddrRangeMin = RootBridgeInstance->IoBase;
> Ptr->AddrRangeMax = 0;
> Ptr->AddrTranslationOffset = \
> (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
> @@ -1429,9 +1428,13 @@ SetResource(
> Ptr->GenFlag = 0;
> Ptr->SpecificFlag = 0;
> Ptr->AddrSpaceGranularity = 32;
> - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
> - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
> - (RootBridgeInstance->MemBase & 0xFFFFFFFF);
> + /* PCIE device Bar should be based on PciRegionBase */
> + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
> + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n"));
> + return EFI_UNSUPPORTED;
> + }
> + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
> + RootBridgeInstance->PciRegionBase;
> Ptr->AddrRangeMax = 0;
> Ptr->AddrTranslationOffset = \
> (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
> @@ -1448,9 +1451,13 @@ SetResource(
> Ptr->GenFlag = 0;
> Ptr->SpecificFlag = 6;
> Ptr->AddrSpaceGranularity = 32;
> - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
> - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
> - (RootBridgeInstance->MemBase & 0xFFFFFFFF);
> + /* PCIE device Bar should be based on PciRegionBase */
> + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
> + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n"));
> + return EFI_UNSUPPORTED;
> + }
> + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
> + RootBridgeInstance->PciRegionBase;
> Ptr->AddrRangeMax = 0;
> Ptr->AddrTranslationOffset = \
> (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
> @@ -1467,9 +1474,9 @@ SetResource(
> Ptr->GenFlag = 0;
> Ptr->SpecificFlag = 0;
> Ptr->AddrSpaceGranularity = 64;
> - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
> - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
> - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
> + /* PCIE device Bar should be based on PciRegionBase */
> + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
> + RootBridgeInstance->PciRegionBase;
> Ptr->AddrRangeMax = 0;
> Ptr->AddrTranslationOffset = \
> (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
> @@ -1486,9 +1493,9 @@ SetResource(
> Ptr->GenFlag = 0;
> Ptr->SpecificFlag = 6;
> Ptr->AddrSpaceGranularity = 64;
> - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
> - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
> - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
> + /* PCIE device Bar should be based on PciRegionBase */
> + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
> + RootBridgeInstance->PciRegionBase;
> Ptr->AddrRangeMax = 0;
> Ptr->AddrTranslationOffset = \
> (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
> diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> index 03edcf1..10d766a 100644
> --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
> @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration (
> PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
> for (Index = 0; Index < TypeMax; Index++) {
> if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
> - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
> - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
> + switch (Index) {
> + case TypeIo:
> + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase;
> + break;
> + case TypeBus:
> + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
> + break;
> + default:
> + /* PCIE Device bar address should be base on PciRegionBase */
> + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase +
> + PrivateData->PciRegionBase;
> + }
> + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1;
> Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
> }
> }
> --
> 1.9.1
>
next prev parent reply other threads:[~2017-09-21 12:54 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-21 10:59 [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 1/7] Hisilicon/D03/Net: Update Snp driver Heyi Guo
2017-09-21 12:51 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-21 13:01 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 02/11] Hisilicon/D03: " Heyi Guo
2017-09-21 13:02 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 2/7] Hisilicon/D03/Sas: Add SasPlatform Heyi Guo
2017-09-21 12:49 ` Leif Lindholm
[not found] ` <3A622B96E322004395454DF73A38DDFA75577DB2@dggemm508-mbx.china.huawei.com>
2017-09-23 16:52 ` 答复: " Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 3/7] Hisilicon/D03: Update binary file Heyi Guo
2017-09-21 12:54 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-21 13:03 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 4/7] Hisilicon/D05/Net: Update Snp driver Heyi Guo
2017-09-21 12:56 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 5/7] Hisilicon/D05/Sas: Add SasPlatform Heyi Guo
2017-09-21 13:00 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
2017-09-21 12:57 ` Leif Lindholm [this message]
2017-09-21 10:59 ` [PATCH edk2-platforms v3 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-21 13:04 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 6/7] Hisilicon/D05: Update binary file Heyi Guo
2017-09-21 12:59 ` Leif Lindholm
[not found] ` <3A622B96E322004395454DF73A38DDFA75577D70@dggemm508-mbx.china.huawei.com>
2017-09-22 9:55 ` 答复: " Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
2017-09-21 13:04 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 7/7] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-21 13:07 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-21 13:11 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-21 13:12 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
2017-09-21 13:14 ` Leif Lindholm
2017-09-21 12:11 ` [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix graeme.gregory
2017-09-21 12:40 ` Leif Lindholm
2017-09-21 13:32 ` Ard Biesheuvel
2017-09-22 3:20 ` Heyi Guo
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