From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x233.google.com (mail-wr0-x233.google.com [IPv6:2a00:1450:400c:c0c::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4884D21E1B764 for ; Thu, 21 Sep 2017 05:54:29 -0700 (PDT) Received: by mail-wr0-x233.google.com with SMTP id a43so4516140wrc.0 for ; Thu, 21 Sep 2017 05:57:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=pJOygZBS3jNkZIJZHxMhP6T3hXSxQUT3QUug2sd+aw8=; b=iaUMmmOuaEeP6nxNpWOy5SAGU04vn0oqF0053zH1L+tMiAG/j1d8EK1eDGPxjZTySW OjXzFlNxSb7Prs5UvWI47qUrAGNAR9SI1N8ejvuAbl+NMIHI61iaxtiCJUdQoNrv8jyt Ei1OZcEHYRiDRA/M2ABUpHcClgRdqz3pdwCFE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=pJOygZBS3jNkZIJZHxMhP6T3hXSxQUT3QUug2sd+aw8=; b=UZbg7Zhygr0UoEy6L/idEy1k4iL9eEvTiQTwhlotHloJPYbumswmgvRnZSfiRPhEKR lWmu3G8HkBIDkbuCFxwf7oypZtVWynu34nTxIjFqUtJuevtnxjSybkYjk5D9XJhuuyQi OBRx6QhrQeHe5mQo7CmBDgucGn3K3ZkK5wFy9xOSoPxrLCWlyIv2bq/laAea3caxuwNq hiBLHOKz1iQtb7mwVh7ysSgooni5QEGKJu/zHyo34Q1U6sCGKJbuobdgzhPM85lNjjse ReqLFJcsooj4Kxx8Q3hKRUqTP39wxak2TJAUQhP97WmoecofWkG9QJqI9nWQfCmeN21J jpOQ== X-Gm-Message-State: AHPjjUjWumQGjB/GqzIgZfnll4S2AzqSA+H4fzSQKgJAIRmE37jQd0ji a840bmClKcp1auQFzqekeUIUkw== X-Google-Smtp-Source: AOwi7QB41GzAoPYQbghO5PT+yIIAK1eQh6ogvzIz6k0AbupEYa4BeccS1V0AQ2IGwynHUdHqqCqlyg== X-Received: by 10.223.176.132 with SMTP id i4mr1782134wra.13.1505998654719; Thu, 21 Sep 2017 05:57:34 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id k18sm1310238wmd.22.2017.09.21.05.57.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Sep 2017 05:57:33 -0700 (PDT) Date: Thu, 21 Sep 2017 13:57:31 +0100 From: Leif Lindholm To: Heyi Guo Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com Message-ID: <20170921125731.kesnfqddogo2g2ht@bivouac.eciton.net> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> <1505991597-52989-11-git-send-email-heyi.guo@linaro.org> MIME-Version: 1.0 In-Reply-To: <1505991597-52989-11-git-send-email-heyi.guo@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 12:54:29 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 21, 2017 at 06:59:49PM +0800, Heyi Guo wrote: > Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm > --- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++-------- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++-- > 2 files changed, 35 insertions(+), 17 deletions(-) > > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > index a970da6..e3d3988 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > @@ -1410,9 +1410,8 @@ SetResource( > Ptr->ResType = 1; > Ptr->GenFlag = 0; > Ptr->SpecificFlag = 0; > - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ > - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + > - (RootBridgeInstance->MemBase & 0xFFFFFFFF); > + /* PCIE Device Iobar address should be based on IoBase */ > + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; > Ptr->AddrRangeMax = 0; > Ptr->AddrTranslationOffset = \ > (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; > @@ -1429,9 +1428,13 @@ SetResource( > Ptr->GenFlag = 0; > Ptr->SpecificFlag = 0; > Ptr->AddrSpaceGranularity = 32; > - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ > - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + > - (RootBridgeInstance->MemBase & 0xFFFFFFFF); > + /* PCIE device Bar should be based on PciRegionBase */ > + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { > + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); > + return EFI_UNSUPPORTED; > + } > + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + > + RootBridgeInstance->PciRegionBase; > Ptr->AddrRangeMax = 0; > Ptr->AddrTranslationOffset = \ > (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; > @@ -1448,9 +1451,13 @@ SetResource( > Ptr->GenFlag = 0; > Ptr->SpecificFlag = 6; > Ptr->AddrSpaceGranularity = 32; > - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ > - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + > - (RootBridgeInstance->MemBase & 0xFFFFFFFF); > + /* PCIE device Bar should be based on PciRegionBase */ > + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { > + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); > + return EFI_UNSUPPORTED; > + } > + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + > + RootBridgeInstance->PciRegionBase; > Ptr->AddrRangeMax = 0; > Ptr->AddrTranslationOffset = \ > (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; > @@ -1467,9 +1474,9 @@ SetResource( > Ptr->GenFlag = 0; > Ptr->SpecificFlag = 0; > Ptr->AddrSpaceGranularity = 64; > - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ > - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + > - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); > + /* PCIE device Bar should be based on PciRegionBase */ > + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + > + RootBridgeInstance->PciRegionBase; > Ptr->AddrRangeMax = 0; > Ptr->AddrTranslationOffset = \ > (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; > @@ -1486,9 +1493,9 @@ SetResource( > Ptr->GenFlag = 0; > Ptr->SpecificFlag = 6; > Ptr->AddrSpaceGranularity = 64; > - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ > - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + > - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); > + /* PCIE device Bar should be based on PciRegionBase */ > + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + > + RootBridgeInstance->PciRegionBase; > Ptr->AddrRangeMax = 0; > Ptr->AddrTranslationOffset = \ > (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > index 03edcf1..10d766a 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( > PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); > for (Index = 0; Index < TypeMax; Index++) { > if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { > - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; > - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; > + switch (Index) { > + case TypeIo: > + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; > + break; > + case TypeBus: > + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; > + break; > + default: > + /* PCIE Device bar address should be base on PciRegionBase */ > + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase + > + PrivateData->PciRegionBase; > + } > + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; > Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; > } > } > -- > 1.9.1 >