From: Leif Lindholm <leif.lindholm@linaro.org>
To: Heyi Guo <heyi.guo@linaro.org>
Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org,
graeme.gregory@linaro.org, ard.biesheuvel@linaro.org,
guoheyi@huawei.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com
Subject: Re: [PATCH edk2-platforms v3 06/11] Hisilicon/D05/Pcie: fix bug of size definition
Date: Thu, 21 Sep 2017 14:04:05 +0100 [thread overview]
Message-ID: <20170921130405.p4gwmpzcwpjigy4p@bivouac.eciton.net> (raw)
In-Reply-To: <1505991597-52989-12-git-send-email-heyi.guo@linaro.org>
On Thu, Sep 21, 2017 at 06:59:50PM +0800, Heyi Guo wrote:
> From: huangming <huangming23@huawei.com>
>
> Fix bug of PcieRegion size definition and IO size definition.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <huangming23@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Hisilicon/D05/D05.dsc | 64 ++++++++++----------
> 1 file changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index aa61c0e..01defe0 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -310,37 +310,37 @@
> gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
>
> gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
> - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
> - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
> - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
> + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000
> gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
> - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
> - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
> + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000
> gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
> - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
> + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000
> gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
> - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
> + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000
> gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
> - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
> + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000
> gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
> - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
> - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
> - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
> + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
> gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
> - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
> - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
> + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
> gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
> - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
> + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
> gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
> - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000
> gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
> - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
> + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000
>
> gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
> gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
> @@ -377,52 +377,52 @@
> gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
>
> gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
> - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
> - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
> + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K
>
> gHisiTokenSpaceGuid.Pcdsoctype|0x1610
>
> --
> 1.9.1
>
next prev parent reply other threads:[~2017-09-21 13:01 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-21 10:59 [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 1/7] Hisilicon/D03/Net: Update Snp driver Heyi Guo
2017-09-21 12:51 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-21 13:01 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 02/11] Hisilicon/D03: " Heyi Guo
2017-09-21 13:02 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 2/7] Hisilicon/D03/Sas: Add SasPlatform Heyi Guo
2017-09-21 12:49 ` Leif Lindholm
[not found] ` <3A622B96E322004395454DF73A38DDFA75577DB2@dggemm508-mbx.china.huawei.com>
2017-09-23 16:52 ` 答复: " Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 3/7] Hisilicon/D03: Update binary file Heyi Guo
2017-09-21 12:54 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-21 13:03 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 4/7] Hisilicon/D05/Net: Update Snp driver Heyi Guo
2017-09-21 12:56 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 5/7] Hisilicon/D05/Sas: Add SasPlatform Heyi Guo
2017-09-21 13:00 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
2017-09-21 12:57 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-21 13:04 ` Leif Lindholm [this message]
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 6/7] Hisilicon/D05: Update binary file Heyi Guo
2017-09-21 12:59 ` Leif Lindholm
[not found] ` <3A622B96E322004395454DF73A38DDFA75577D70@dggemm508-mbx.china.huawei.com>
2017-09-22 9:55 ` 答复: " Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
2017-09-21 13:04 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 7/7] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-21 13:07 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-21 13:11 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-21 13:12 ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
2017-09-21 13:14 ` Leif Lindholm
2017-09-21 12:11 ` [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix graeme.gregory
2017-09-21 12:40 ` Leif Lindholm
2017-09-21 13:32 ` Ard Biesheuvel
2017-09-22 3:20 ` Heyi Guo
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