From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D75421E1B741 for ; Thu, 21 Sep 2017 06:01:50 -0700 (PDT) Received: by mail-wr0-x22b.google.com with SMTP id w12so4517271wrc.7 for ; Thu, 21 Sep 2017 06:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Cg0vbSJtgiFBTR3O+mW7jFsGtXBY+iqbBMVEf5frLrI=; b=CsYHBrRCdK4nh5oy07RjM1vHU1N+bnVUBZGR1EdKp00nVyfPIwzteOMr/EkwgSVgEe ptg4DQplcCCSzL3EJrV3sNUokvmDxREweUMYbz6nknH2/d4MYrRbMap5zBVRAv2JeU7b aj1ai6rR6Vl2mFIy+IMnVeSJrMI9kiqQGm6cs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Cg0vbSJtgiFBTR3O+mW7jFsGtXBY+iqbBMVEf5frLrI=; b=uiEbYhlGmZRDcMtW2S2lwnX39/k8vEQ0hGIoM9EvOrQgNro0qHmef0qetk13607M7B tz9+t9ewYcjmMxbdQHYwtbcxXXBsGjtdHh5a+SeFKbdM94m5KZ31RKLalo7UHtXnYqXW Xjx4ChN9yRBEvU+Tjk86KSF3TC4e7LWVYe2rHjMtldQ1HtLuZRNbM0yGIf7qNI9qelby NlDT1f/TdQTaDnQTkDRy88M9Ngrnd1UKYQHIcRLggrI6TptHe1LcwsKmb99hK2ZW4M0c yRVYu9pwqy+h/3YZqBigY95x0bUgGM9Fxp9K2S0ERlqODTBjbkL8dMQLDhNAs7QyrlJL pJ9A== X-Gm-Message-State: AHPjjUic2G4QCK3MNkiAi26raORmnRCBOTxSsaT3U9h+kMPCWB1vbWY0 Dg9DjebWqT/lx2jcl0ZekuIIig== X-Google-Smtp-Source: AOwi7QCaW/z10sIUVit3Vfk2ot6N5WFZRWgWZzScWpvrHYPsl0uCOnTa3AHImNCGlfH+6iSN+nJrtg== X-Received: by 10.223.181.131 with SMTP id c3mr1841444wre.129.1505999095957; Thu, 21 Sep 2017 06:04:55 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id z51sm1707974wrz.80.2017.09.21.06.04.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Sep 2017 06:04:54 -0700 (PDT) Date: Thu, 21 Sep 2017 14:04:52 +0100 From: Leif Lindholm To: Heyi Guo Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com Message-ID: <20170921130452.zfidcyt4cv3unhux@bivouac.eciton.net> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> <1505991597-52989-14-git-send-email-heyi.guo@linaro.org> MIME-Version: 1.0 In-Reply-To: <1505991597-52989-14-git-send-email-heyi.guo@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 13:01:50 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 21, 2017 at 06:59:52PM +0800, Heyi Guo wrote: > From: huangming > > On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are > 0x20000000 and 0x30000000 based. These addresses overlap with the DDR > memory range 0-1G. In this situation, on the inbound direction, our pcie > will drop the DDR address access that are located in the pci range window > and lead to a dataflow error. > > Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000 > and decrease PciRegion Size accordingly. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang Thanks - this patch is a lot cleaner when ordered after the previous one. Reviewed-by: Leif Lindholm > --- > Platform/Hisilicon/D05/D05.dsc | 12 ++++++------ > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- > 2 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc > index 01defe0..64101a7 100644 > --- a/Platform/Hisilicon/D05/D05.dsc > +++ b/Platform/Hisilicon/D05/D05.dsc > @@ -329,12 +329,12 @@ > gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 > gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 > gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 > - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 > - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 > + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 > + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 > gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 > gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 > - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 > - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 > + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 > + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 > gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 > gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 > gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 > @@ -352,9 +352,9 @@ > gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 > gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 > gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 > - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 > + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 > gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 > - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 > + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 > gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 > gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 > gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > index 79267e5..55c7f50 100644 > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl > @@ -646,10 +646,10 @@ Scope(_SB) > Cacheable, > ReadWrite, > 0x0, // Granularity > - 0x20000000, // Min Base Address > + 0x40000000, // Min Base Address > 0xefffffff, // Max Base Address > 0x65000000000, // Translate > - 0xd0000000 // Length > + 0xb0000000 // Length > ) > QWordIO ( > ResourceProducer, > @@ -766,10 +766,10 @@ Scope(_SB) > Cacheable, > ReadWrite, > 0x0, // Granularity > - 0x30000000, // Min Base Address > + 0x40000000, // Min Base Address > 0xefffffff, // Max Base Address > 0x75000000000, // Translate > - 0xc0000000 // Length > + 0xb0000000 // Length > ) > QWordIO ( > ResourceProducer, > -- > 1.9.1 >