From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22a.google.com (mail-wr0-x22a.google.com [IPv6:2a00:1450:400c:c0c::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9288221E1B775 for ; Thu, 21 Sep 2017 06:11:47 -0700 (PDT) Received: by mail-wr0-x22a.google.com with SMTP id z39so4535106wrb.8 for ; Thu, 21 Sep 2017 06:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=XrefEVMz/TIgyfpUPvMDk3Yp8eRNQgSH25XpaAQ1tK4=; b=McD4ghyUnkh6Tsl+kcgAsitSgKQE+4nxv0SJFyjayRC1ULnkwb6NRljDH+0GpDVZOf VjbfKhKn701ZKPb+HLQVC0b75xysnrHmLZ8Uj3unMrjnh2FZwnWkOai+kGeVi4i+XDJI WVCiGOskUxe+u70Vw8fy7D2gHnp55xU8WA5fI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=XrefEVMz/TIgyfpUPvMDk3Yp8eRNQgSH25XpaAQ1tK4=; b=MOJNTlhKvySnI8GObQAsvRQeQfW4kUwOowCD9gbXvV5glQQq717vWb8MmH16RYrDcu htdupa7Rr5EOSnaVJLEciVKGek4qTBNHI5nx5l/OYBPUQU92qgCNgYlNVKcw8HD2GJGz dr9jyRIHSeYIKd/OTFq+4fjiizHEOj5faGMhKdGBK2Fnv5Lni8Z//Fp1VCWXgPFuNfzj 6exgxGBRk2rZ/FOtew4f6OE2JmdyKslXqzm+/RUJ64atzMTpDgl4U2bd9+7tkSJWoDi9 4HHUQpMS7A1VRLSWfNIxuTI59OeaUUG/fHQ8o2BDbuqSKHgaslcDcerWhnvrsZQ2Udq1 JLew== X-Gm-Message-State: AHPjjUj1XpjlZUDQGdo7ZMWAxgXta3qXgeFwFera/kulMlQDboYpv52J L7mOji7iG4r5kG1kyof88NW7jw== X-Google-Smtp-Source: AOwi7QDjSYIiwIn+uaDKR+JVMwXSBXGE1yn5eCHCMGxV74AxKbq++XbjFWJ6YbkwvpWgQi7j0j1JZQ== X-Received: by 10.223.172.14 with SMTP id v14mr2077886wrc.142.1505999693038; Thu, 21 Sep 2017 06:14:53 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m64sm1722310wmb.0.2017.09.21.06.14.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Sep 2017 06:14:51 -0700 (PDT) Date: Thu, 21 Sep 2017 14:14:50 +0100 From: Leif Lindholm To: Heyi Guo Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com, Ming Huang Message-ID: <20170921131450.kshvdxp6lybmgtkw@bivouac.eciton.net> References: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> <1505991597-52989-19-git-send-email-heyi.guo@linaro.org> MIME-Version: 1.0 In-Reply-To: <1505991597-52989-19-git-send-email-heyi.guo@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v3 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 13:11:48 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 21, 2017 at 06:59:57PM +0800, Heyi Guo wrote: > From: Ming Huang > > 1. Because Hi161x chip doesn't support "ARI Forwarding Enable" > function, BIOS will enumerate 32 same devices (Device Number 0~31) > when attach a Non-ARI capable device in the RP. Hi161x chip will > not fix it, need BIOS patch. > 2. Just enlarge iatu for those root port with ARI capable device > attached, Non-ARI capable device's RP, keep iatu limitation. > 3. Remove previous temporary solution as below commit id: > "7d157da88852cc91df2b11b10ade2edbbfbe77da" > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jason zhang Please adjust + add email addresses. The content below is fine. / Leif > --- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++++++++++++++ > 3 files changed, 87 insertions(+) > > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > index e3d3988..9fa3f84 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > @@ -839,6 +839,7 @@ NotifyPhase( > > case EfiPciHostBridgeEndEnumeration: > PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); > + EnlargeAtuConfig0 (This); > break; > > case EfiPciHostBridgeBeginBusAllocation: > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h > index cddda6b..c04361f 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h > @@ -401,6 +401,9 @@ PreprocessController ( > #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL > #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL > > +#define INVALID_CAPABILITY_00 0x00 > +#define INVALID_CAPABILITY_FF 0xFF > +#define PCI_CAPABILITY_POINTER_MASK 0xFC > > // > // Driver Instance Data Prototypes > @@ -518,4 +521,8 @@ RootBridgeConstructor ( > IN UINT32 Seg > ); > > +VOID > +EnlargeAtuConfig0 ( > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This > + ); > #endif > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > index 10d766a..b57bd51 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > @@ -14,6 +14,7 @@ > **/ > > #include "PciHostBridge.h" > +#include > #include > #include > #include > @@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration ( > return EFI_SUCCESS; > } > > +BOOLEAN > +PcieCheckAriFwdEn ( > + UINTN PciBaseAddr > + ) > +{ > + UINT8 PciPrimaryStatus; > + UINT8 CapabilityOffset; > + UINT8 CapId; > + UINT8 TempData; > + > + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); > + > + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { > + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); > + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; > + > + while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) { > + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); > + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { > + break; > + } > + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); > + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; > + } > + } else { > + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); > + return FALSE; > + } > + > + if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) { > + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); > + return FALSE; > + } > + > + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + > + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); > + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; > + > + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { > + return TRUE; > + } else { > + return FALSE; > + } > +} > + > +VOID > +EnlargeAtuConfig0 ( > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This > + ) > +{ > + UINTN RbPciBase; > + UINT64 MemLimit; > + LIST_ENTRY *List; > + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; > + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; > + > + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); > + > + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); > + List = HostBridgeInstance->Head.ForwardLink; > + > + while (List != &HostBridgeInstance->Head) { > + PCIE_DEBUG ("HostBridge has data.\n"); > + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); > + > + RbPciBase = RootBridgeInstance->RbPciBar; > + > + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. > + if (PcieCheckAriFwdEn (RbPciBase)) { > + MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, > + RootBridgeInstance->BusBase + 2, 0, 0, 0) > + - 1; > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > + } > + List = List->ForwardLink; > + } > +} > -- > 1.9.1 >