From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 281B921EC8D0B for ; Wed, 27 Sep 2017 21:29:09 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 27 Sep 2017 21:32:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,448,1500966000"; d="scan'208";a="1224629824" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by fmsmga002.fm.intel.com with ESMTP; 27 Sep 2017 21:32:20 -0700 From: Hao Wu To: edk2-devel@lists.01.org Cc: Hao Wu , Steven Shi , Eric Dong , Paolo Bonzini , Michael Kinney , Liming Gao Date: Thu, 28 Sep 2017 12:32:11 +0800 Message-Id: <20170928043213.20776-4-hao.a.wu@intel.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170928043213.20776-1-hao.a.wu@intel.com> References: <20170928043213.20776-1-hao.a.wu@intel.com> Subject: [PATCH v3 3/5] MdeModulePkg/Tpl: Fix negative value left shift X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Sep 2017 04:29:09 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=695 Within function CoreRestoreTpl(), left shift a negative value -2 is used in: "while (((-2 << NewTpl) & gEventPending) != 0) {" which involves undefined behavior. According to the C11 spec, Section 6.5.7: > 4 The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated > bits are filled with zeros. If E1 has an unsigned type, the value > of the result is E1 * 2^E2 , reduced modulo one more than the > maximum value representable in the result type. If E1 has a signed > type and nonnegative value, and E1 * 2^E2 is representable in the > result type, then that is the resulting value; otherwise, the > behavior is undefined. This commit refines the code logic to avoid left shifting the negative value. Cc: Steven Shi Cc: Eric Dong Cc: Paolo Bonzini Cc: Michael Kinney Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu Reviewed-by: Star Zeng --- MdeModulePkg/Core/Dxe/Event/Tpl.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Core/Dxe/Event/Tpl.c b/MdeModulePkg/Core/Dxe/Event/Tpl.c index 8ad0a33701..e3caf832b8 100644 --- a/MdeModulePkg/Core/Dxe/Event/Tpl.c +++ b/MdeModulePkg/Core/Dxe/Event/Tpl.c @@ -1,7 +1,7 @@ /** @file Task priority (TPL) functions. -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -103,6 +103,7 @@ CoreRestoreTpl ( ) { EFI_TPL OldTpl; + EFI_TPL PendingTpl; OldTpl = gEfiCurrentTpl; if (NewTpl > OldTpl) { @@ -123,8 +124,13 @@ CoreRestoreTpl ( // // Dispatch any pending events // - while (((-2 << NewTpl) & gEventPending) != 0) { - gEfiCurrentTpl = (UINTN) HighBitSet64 (gEventPending); + while (gEventPending != 0) { + PendingTpl = (UINTN) HighBitSet64 (gEventPending); + if (PendingTpl <= NewTpl) { + break; + } + + gEfiCurrentTpl = PendingTpl; if (gEfiCurrentTpl < TPL_HIGH_LEVEL) { CoreSetInterruptState (TRUE); } -- 2.12.0.windows.1