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[82.12.0.119]) by smtp.gmail.com with ESMTPSA id c24sm11161871wrg.92.2017.10.04.01.12.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Oct 2017 01:12:34 -0700 (PDT) From: Leif Lindholm To: edk2-devel@lists.01.org Cc: ard.biesheuvel@linaro.org, Heyi Guo Date: Wed, 4 Oct 2017 09:12:33 +0100 Message-Id: <20171004081233.5095-1-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH] Platform/Hisilicon: fix D02 driver indentation errors X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Oct 2017 08:09:18 -0000 When building with a somewhat recent toolchain (GCC 6.3), the D02 platform fails due to (the implicit) -Werror=misleading-indentation. Cc: Heyi Guo Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c | 4 ++-- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c index d876565a7d..b18b56ddb2 100644 --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c +++ b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c @@ -497,8 +497,8 @@ STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat) !(dma_rx_status & DMA_RX_STATUS_BUSY)) break; - // Wait for status change in polling - NanoSecondDelay (100); + // Wait for status change in polling + NanoSecondDelay (100); } } diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c index 3581b41c90..3739a36e64 100644 --- a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c @@ -570,7 +570,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) if (pcs_local_status_checked) DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n")); - count = 0; + count = 0; do { MicroSecondDelay(1000); count ++; @@ -583,7 +583,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) if (hilink_status_checked) DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n")); - return EFI_SUCCESS; + return EFI_SUCCESS; } EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) @@ -616,7 +616,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) if (pcs_local_status_checked) DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); - count = 0; + count = 0; do { MicroSecondDelay(1000); RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status); @@ -627,7 +627,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) if (hilink_status_checked) DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); - return EFI_SUCCESS; + return EFI_SUCCESS; } VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port) @@ -777,7 +777,7 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, if (clock_status_checked) DEBUG((EFI_D_ERROR, "clock operation failed!\n")); - return EFI_SUCCESS; + return EFI_SUCCESS; } VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) -- 2.11.0