Re: [PATCH edk2-platforms] Platform/Hisilicon: fix D02 driver indentation errors

[Leif Lindholm <leif.lindholm@linaro.org>]

Note to self: --subject-prefix="PATCH edk2-platforms" goes on git
format-patch command line, not send-email.

Grabbing some coffee.

/
    Leif

On Wed, Oct 04, 2017 at 09:12:33AM +0100, Leif Lindholm wrote:
> When building with a somewhat recent toolchain (GCC 6.3), the D02
> platform fails due to (the implicit) -Werror=misleading-indentation.
> 
> Cc: Heyi Guo <heyi.guo@linaro.org>
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
>  Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c             |  4 ++--
>  Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 10 +++++-----
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c
> index d876565a7d..b18b56ddb2 100644
> --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c
> +++ b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c
> @@ -497,8 +497,8 @@ STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat)
>          !(dma_rx_status & DMA_RX_STATUS_BUSY))
>          break;
>  
> -        // Wait for status change in polling
> -        NanoSecondDelay (100);
> +      // Wait for status change in polling
> +      NanoSecondDelay (100);
>      }
>    }
>  
> diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
> index 3581b41c90..3739a36e64 100644
> --- a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
> +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c
> @@ -570,7 +570,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
>    if (pcs_local_status_checked)
>          DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n"));
>  
> -    count = 0;
> +  count = 0;
>    do {
>          MicroSecondDelay(1000);
>          count ++;
> @@ -583,7 +583,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port)
>    if (hilink_status_checked)
>          DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n"));
>  
> -    return EFI_SUCCESS;
> +  return EFI_SUCCESS;
>  }
>  
>  EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
> @@ -616,7 +616,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
>    if (pcs_local_status_checked)
>          DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
>  
> -    count = 0;
> +  count = 0;
>    do {
>          MicroSecondDelay(1000);
>          RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status);
> @@ -627,7 +627,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port)
>    if (hilink_status_checked)
>          DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n"));
>  
> -    return EFI_SUCCESS;
> +  return EFI_SUCCESS;
>  }
>  
>  VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port)
> @@ -777,7 +777,7 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port,
>    if (clock_status_checked)
>          DEBUG((EFI_D_ERROR, "clock operation failed!\n"));
>  
> -    return EFI_SUCCESS;
> +  return EFI_SUCCESS;
>  }
>  
>  VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
> -- 
> 2.11.0
>