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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 203sm325581wmm.22.2017.10.04.01.24.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Oct 2017 01:24:08 -0700 (PDT) Date: Wed, 4 Oct 2017 09:24:06 +0100 From: Leif Lindholm To: edk2-devel@lists.01.org Message-ID: <20171004082406.ufull7clghge2spz@bivouac.eciton.net> References: <20171004081233.5095-1-leif.lindholm@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171004081233.5095-1-leif.lindholm@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Platform/Hisilicon: fix D02 driver indentation errors X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Oct 2017 08:20:49 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Note to self: --subject-prefix="PATCH edk2-platforms" goes on git format-patch command line, not send-email. Grabbing some coffee. / Leif On Wed, Oct 04, 2017 at 09:12:33AM +0100, Leif Lindholm wrote: > When building with a somewhat recent toolchain (GCC 6.3), the D02 > platform fails due to (the implicit) -Werror=misleading-indentation. > > Cc: Heyi Guo > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leif Lindholm > --- > Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c | 4 ++-- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 10 +++++----- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > index d876565a7d..b18b56ddb2 100644 > --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > +++ b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > @@ -497,8 +497,8 @@ STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat) > !(dma_rx_status & DMA_RX_STATUS_BUSY)) > break; > > - // Wait for status change in polling > - NanoSecondDelay (100); > + // Wait for status change in polling > + NanoSecondDelay (100); > } > } > > diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > index 3581b41c90..3739a36e64 100644 > --- a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > @@ -570,7 +570,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) > if (pcs_local_status_checked) > DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n")); > > - count = 0; > + count = 0; > do { > MicroSecondDelay(1000); > count ++; > @@ -583,7 +583,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) > if (hilink_status_checked) > DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > @@ -616,7 +616,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > if (pcs_local_status_checked) > DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); > > - count = 0; > + count = 0; > do { > MicroSecondDelay(1000); > RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status); > @@ -627,7 +627,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > if (hilink_status_checked) > DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port) > @@ -777,7 +777,7 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, > if (clock_status_checked) > DEBUG((EFI_D_ERROR, "clock operation failed!\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) > -- > 2.11.0 >