* [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix
@ 2017-09-29 3:19 Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1710-platforms-v5
Note:
1. There may be some minor issue (or even in SoC IP) that causes D05/3 into exception,
which was just found when we updated edk2 and edk2-platforms. We will continue to investigate the issue.
It boot successfully by switch the VirtualEhciPciIo with old one.
2. The separate patch (Add AddressTranslationOffset support) is a prerequisite for this series
and it's source can also be found in above branch(rp-1710-platforms-v5).
Chenhui Sun (1):
Hisilicon/D03: Disable the function of PerfTuning
Heyi Guo (4):
Hisilicon/D05: Modify dsc and fdf file
Hisilicon/D03: Modify dsc and fdf file
Hisilicon: Fix the drivers use the same GUID issue
Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
Jason zhang (1):
Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
Ming Huang (5):
Hisilicon D03/D05: get firmware version from FIRMWARE_VER
Hisilicon/D05/Pcie: fix bug of size definition
D05/PCIe: Modify PcieRegionBase of secondary chip
D05/ACPI: Disable D05 SAS0 and SAS2
D05/ACPI: Modify I2C device
Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +-
Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +-
Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +-
Platform/Hisilicon/D03/D03.dsc | 12 ++-
Platform/Hisilicon/D03/D03.fdf | 4 +-
Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +-
Platform/Hisilicon/D05/D05.dsc | 83 +++++++++--------
Platform/Hisilicon/D05/D05.fdf | 4 +-
Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +-
Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++----
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++-
Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 -----------
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +----
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +-
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++
Silicon/Hisilicon/HisiPkg.dec | 1 -
Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +-
Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +-
26 files changed, 203 insertions(+), 157 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 02/11] Hisilicon/D03: " Heyi Guo
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
1. Add Drivers/SasPlatform;
2. Add Drivers/Net/SnpPlatform;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D05/D05.dsc | 5 -----
Platform/Hisilicon/D05/D05.fdf | 4 +++-
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 3cdb1b1..7cd5758 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -538,11 +538,6 @@
Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf
-
MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index b6d0e42..a5e6546 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -247,7 +247,8 @@ READ_LOCK_STATUS = TRUE
#Network
#
- INF Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf
+ INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
+ INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
@@ -292,6 +293,7 @@ READ_LOCK_STATUS = TRUE
#
INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf
INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
#
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 02/11] Hisilicon/D03: Modify dsc and fdf file
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
1. Add Drivers/SasPlatform;
2. Add Drivers/Net/SnpPlatform;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 5 -----
Platform/Hisilicon/D03/D03.fdf | 4 +++-
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index afea162..7e25ffb 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -418,11 +418,6 @@
Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
- #
- #network
- #
- Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf
-
MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index b62b908..37a7e28 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -242,7 +242,8 @@ READ_LOCK_STATUS = TRUE
#Network
#
- INF Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf
+ INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
+ INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
@@ -271,6 +272,7 @@ READ_LOCK_STATUS = TRUE
#
INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf
+ INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
#
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 02/11] Hisilicon/D03: " Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
The drivers build from separate sources, their GUID should
be different.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +-
Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +-
Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +-
Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +-
Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +-
Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +-
Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +-
Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +-
14 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
index 5506a58..3f3f81c 100644
--- a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
+++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = EarlyConfigPeim
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+ FILE_GUID = ECAE8400-9CCE-4BA5-9B44-74CAABE4DA79
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = EarlyConfigEntry
diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
index c952414..e881899 100644
--- a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
+++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FdtUpdateLib
- FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+ FILE_GUID = 0F9ADE24-46B4-4506-8802-60C519B56133
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = FdtUpdateLib
diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
index 4d2dbba..ab3b62b 100644
--- a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
+++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+ FILE_GUID = 128F1E1E-A921-4277-A796-A4A47B96B7D2
MODULE_TYPE = BASE
VERSION_STRING = 1.0
diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
index df5adf1..4c5955f 100644
--- a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
+++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = OemNicConfig
- FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+ FILE_GUID = BF422A22-CA90-4C34-95B9-3D147AF09E70
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = OemNicConfigEntry
diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
index 9569b91..2d9d53d 100755
--- a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
+++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FdtUpdateLib
- FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9
+ FILE_GUID = B80B9FF1-FAB9-4BE5-B602-5ABAA6B7A3D4
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = FdtUpdateLib
diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
index 9d8ea7e..0f6b68d 100644
--- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
@@ -17,7 +17,7 @@
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = EarlyConfigPeimD05
- FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+ FILE_GUID = 13525B94-06F0-41AC-8CAF-724B149FD259
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = EarlyConfigEntry
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
index 4fe7ac6..bf44ff7 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = OemMiscLibHi1616Evb
- FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
+ FILE_GUID = 751C7627-D5F8-499C-AEEEE-C87858759612
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = OemMiscLib
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
index cd64193..21bb33a 100644
--- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
+++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = PlatformPciLib
- FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+ FILE_GUID = B94B8A3A-AD7D-4F26-B140-1E699682176B
MODULE_TYPE = BASE
VERSION_STRING = 1.0
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
index 174e967..89447cc 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IoInitDxe
- FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400
+ FILE_GUID = 28C9B7DE-AAD6-4E9B-811B-050AD3DAB9A3
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
index 686d041..ee9dbed 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -17,7 +17,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PcieInitDxe
- FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97
+ FILE_GUID = 8EB6E216-BA47-4B30-B68A-2B371F7232A6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = PcieInitEntry
diff --git a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
index 6faefb1..17d59ee 100644
--- a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+++ b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
@@ -20,7 +20,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DS3231RealTimeClockLib
- FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D
+ FILE_GUID = 5FD8127D-11E1-488F-8CF1-A143157D6BF0
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RealTimeClockLib
diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
index d7957ea..df65d4b 100644
--- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
+++ b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
@@ -17,7 +17,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Dw8250SerialPortLib
- FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+ FILE_GUID = 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = SerialPortLib
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
index 7f95124..9bca88f 100644
--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = I2CLib
- FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ FILE_GUID = 162F2DF1-DBF8-41E6-9792-92A96ADEAB40
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = I2CLib
diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
index 4990072..1bb4f5c 100644
--- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
@@ -16,7 +16,7 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = I2CLibRuntime
- FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ FILE_GUID = 2E602B32-9203-44A4-BF28-1FF98BD89523
MODULE_TYPE = DXE_RUNTIME_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = I2CLib
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (2 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Ming Huang, Heyi Guo
From: Ming Huang <waip23@foxmail.com>
Value of the environment variable FIRMWARE_VER is GIT SHA by default,
and you can add the environment variable FIRMWARE_VER to EXTRA_OPTIONS
at build time to specify something else, eg. "16.12-<commit id>".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 6 +++++-
Platform/Hisilicon/D05/D05.dsc | 6 +++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 7e25ffb..fca6781 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -170,7 +170,11 @@
gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release"
+ !ifdef $(FIRMWARE_VER)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+ !else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D03 UEFI 17.10 Release"
+ !endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 7cd5758..aa61c0e 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -188,7 +188,11 @@
gHisiTokenSpaceGuid.PcdIsMPBoot|1
gHisiTokenSpaceGuid.PcdSocketMask|0x3
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release"
+ !ifdef $(FIRMWARE_VER)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+ !else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D05 UEFI 17.10 Release"
+ !endif
gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (3 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++--------
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++--
2 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
index a970da6..e3d3988 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -1410,9 +1410,8 @@ SetResource(
Ptr->ResType = 1;
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE Device Iobar address should be based on IoBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->IoBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1429,9 +1428,13 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
Ptr->AddrSpaceGranularity = 32;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
+ DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1448,9 +1451,13 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 6;
Ptr->AddrSpaceGranularity = 32;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
+ DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1467,9 +1474,9 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
Ptr->AddrSpaceGranularity = 64;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1486,9 +1493,9 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 6;
Ptr->AddrSpaceGranularity = 64;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 03edcf1..10d766a 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration (
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
for (Index = 0; Index < TypeMax; Index++) {
if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
- Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
- Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
+ switch (Index) {
+ case TypeIo:
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase;
+ break;
+ case TypeBus:
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
+ break;
+ default:
+ /* PCIE Device bar address should be base on PciRegionBase */
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase +
+ PrivateData->PciRegionBase;
+ }
+ Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1;
Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
}
}
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (4 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
From: Ming Huang <huangming23@huawei.com>
Fix bug of PcieRegion size definition and IO size definition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D05/D05.dsc | 64 ++++++++++----------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index aa61c0e..01defe0 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -310,37 +310,37 @@
gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
- gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
- gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
- gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000
gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
- gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
- gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
+ gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000
gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
- gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
+ gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000
gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
- gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
+ gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000
gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
- gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
+ gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
- gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
- gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
- gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
+ gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
- gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
- gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
+ gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
@@ -377,52 +377,52 @@
gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K
gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
- gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
+ gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K
gHisiTokenSpaceGuid.Pcdsoctype|0x1610
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (5 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
From: Ming Huang <huangming23@huawei.com>
On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.
Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D05/D05.dsc | 12 ++++++------
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 01defe0..64101a7 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -329,12 +329,12 @@
gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
@@ -352,9 +352,9 @@
gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000
gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000
gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 79267e5..55c7f50 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -646,10 +646,10 @@ Scope(_SB)
Cacheable,
ReadWrite,
0x0, // Granularity
- 0x20000000, // Min Base Address
+ 0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x65000000000, // Translate
- 0xd0000000 // Length
+ 0xb0000000 // Length
)
QWordIO (
ResourceProducer,
@@ -766,10 +766,10 @@ Scope(_SB)
Cacheable,
ReadWrite,
0x0, // Granularity
- 0x30000000, // Min Base Address
+ 0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x75000000000, // Translate
- 0xc0000000 // Length
+ 0xb0000000 // Length
)
QWordIO (
ResourceProducer,
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (6 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Chenhui Sun, Heyi Guo
From: Chenhui Sun <chenhui.sun@linaro.org>
The PerTuning function is not stable, it will cause the
LSI SAS 3008/3108 crash, disable this function first.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 1 -
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 -
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 --------------------
Silicon/Hisilicon/HisiPkg.dec | 1 -
4 files changed, 53 deletions(-)
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index fca6781..f2a120e 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -112,7 +112,6 @@
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
- gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE
[PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03"
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
index ee9dbed..61b091f 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -55,7 +55,6 @@
[FeaturePcd]
gHisiTokenSpaceGuid.PcdIsItsSupported
- gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable
[depex]
TRUE
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 8ab7fa3..f420c91 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -315,50 +315,6 @@ PcieEnableItssm (
}
-STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
-{
- UINT32 Value;
- UINTN RegSegmentOffset;
-
- if (Port >= PCIE_MAX_ROOTBRIDGE) {
- DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port));
- return EFI_INVALID_PARAMETER;
- }
-
- RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET;
-
- //Enable SMMU bypass for translation
- RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
- //BIT13: controller master read SMMU bypass
- //BIT12: controller master write SMMU bypass
- //BIT10: SMMU bypass enable
- Value |= (BIT13 | BIT12 | BIT10);
- RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
-
- //Switch strongly order (SO) to relaxed order (RO) for write transaction
- RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
- //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge
- Value |= (BIT13 | BIT12);
- //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction
- Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17);
- RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
-
- //Force streamID for controller read operation
- RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
- //Force using streamID in PCIE_SYS_CTRL54_REG
- Value &= ~(BIT30);
- //Set streamID to 0, bit[0:15] is for request ID and should be kept
- Value &= ~(0xff << 16);
- RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
-
- //Enable read and write snoopy
- RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
- Value |= (BIT30 | BIT28);
- RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
-
- return EFI_SUCCESS;
-}
-
EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
{
PCIE_CTRL_7_U pcie_ctrl7;
@@ -1141,12 +1097,6 @@ PciePortInit (
DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType);
/* assert LTSSM enable */
(VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg);
- if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
- //PCIe will still work even if performance tuning fails,
- //and there is warning message inside the function to print
- //detailed error if there is.
- (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
- }
PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex);
/*
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 2c02e14..81ba3be 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -274,7 +274,6 @@
[PcdsFeatureFlag]
gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065
- gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (7 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device Heyi Guo
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
From: Ming Huang <huangming23@huawei.com>
There is no interface from SAS0 or SAS2 controller on D05,
so SAS0 and SAS2 can't be used.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
index 93beb95..6455130 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
@@ -88,6 +88,11 @@ Scope(_SB)
Store(0x7ffff, CLK)
Sleep(1)
}
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
}
Device(SAS1) {
@@ -239,6 +244,11 @@ Scope(_SB)
Store(0x7ffff, CLK)
Sleep(1)
}
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0)
+ }
}
}
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (8 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
From: Ming Huang <huangming23@huawei.com>
1. Disable I2C0 device avoiding access conflict in OS, for it is used
by UEFI to access DS3231 RTC chip and provide time services;
2. Modify _HID of I2C2 for matching the string in OS driver;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
index eb906ef..3cc60d1 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
@@ -18,26 +18,8 @@
Scope(_SB)
{
- Device(I2C0) {
- Name(_HID, "APMC0D0F")
- Name(_CID, "APMC0D0F")
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
- })
- Name (_DSD, Package () {
- ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package () {"clock-frequency", 100000},
- Package () {"i2c-sda-falling-time-ns", 913},
- Package () {"i2c-scl-falling-time-ns", 303},
- Package () {"i2c-sda-hold-time-ns", 0x9c2},
- }
- })
- }
-
Device(I2C2) {
- Name(_HID, "APMC0D0F")
+ Name(_HID, "HISI02A1")
Name(_CID, "APMC0D0F")
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (9 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device Heyi Guo
@ 2017-09-29 3:19 ` Heyi Guo
2017-09-29 19:19 ` [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-10-05 12:54 ` Leif Lindholm
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 3:19 UTC (permalink / raw)
To: leif.lindholm, linaro-uefi, edk2-devel, graeme.gregory
Cc: ard.biesheuvel, guoheyi, wanghuiqiang, huangming23, zhangjinsong2,
mengfanrong, waip23, Heyi Guo
From: Jason zhang <zhangjinsong2@huawei.com>
1. Because Hi161x chip doesn't support "ARI Forwarding Enable"
function, BIOS will enumerate 32 same devices (Device Number 0~31)
when a Non-ARI capable device attached in the RP. Hi161x chip will
not fix it, need BIOS patch.
2. Just enlarge iatu for those root port with ARI capable device
attached, Non-ARI capable device's RP, keep iatu limitation.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 +
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++++++++++++++
3 files changed, 87 insertions(+)
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
index e3d3988..9fa3f84 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -839,6 +839,7 @@ NotifyPhase(
case EfiPciHostBridgeEndEnumeration:
PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");
+ EnlargeAtuConfig0 (This);
break;
case EfiPciHostBridgeBeginBusAllocation:
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
index cddda6b..c04361f 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
@@ -401,6 +401,9 @@ PreprocessController (
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define INVALID_CAPABILITY_00 0x00
+#define INVALID_CAPABILITY_FF 0xFF
+#define PCI_CAPABILITY_POINTER_MASK 0xFC
//
// Driver Instance Data Prototypes
@@ -518,4 +521,8 @@ RootBridgeConstructor (
IN UINT32 Seg
);
+VOID
+EnlargeAtuConfig0 (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
+ );
#endif
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 10d766a..b57bd51 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -14,6 +14,7 @@
**/
#include "PciHostBridge.h"
+#include <IndustryStandard/PciExpress30.h>
#include <Library/DevicePathLib.h>
#include <Library/DmaLib.h>
#include <Library/PciExpressLib.h>
@@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration (
return EFI_SUCCESS;
}
+BOOLEAN
+PcieCheckAriFwdEn (
+ UINTN PciBaseAddr
+ )
+{
+ UINT8 PciPrimaryStatus;
+ UINT8 CapabilityOffset;
+ UINT8 CapId;
+ UINT8 TempData;
+
+ PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET);
+
+ if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) {
+ CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET);
+ CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
+
+ while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) {
+ CapId = MmioRead8 (PciBaseAddr + CapabilityOffset);
+ if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) {
+ break;
+ }
+ CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1);
+ CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
+ }
+ } else {
+ PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
+ return FALSE;
+ }
+
+ if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) {
+ PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
+ return FALSE;
+ }
+
+ TempData = MmioRead16 (PciBaseAddr + CapabilityOffset +
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET);
+ TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING;
+
+ if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+VOID
+EnlargeAtuConfig0 (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
+ )
+{
+ UINTN RbPciBase;
+ UINT64 MemLimit;
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+
+ PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n");
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ PCIE_DEBUG ("HostBridge has data.\n");
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+
+ RbPciBase = RootBridgeInstance->RbPciBar;
+
+ // Those ARI FWD Enable Root Bridge, need enlarge iatu window.
+ if (PcieCheckAriFwdEn (RbPciBase)) {
+ MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam,
+ RootBridgeInstance->BusBase + 2, 0, 0, 0)
+ - 1;
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ }
+ List = List->ForwardLink;
+ }
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (10 preceding siblings ...)
2017-09-29 3:19 ` [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
@ 2017-09-29 19:19 ` Heyi Guo
2017-10-05 12:54 ` Leif Lindholm
12 siblings, 0 replies; 14+ messages in thread
From: Heyi Guo @ 2017-09-29 19:19 UTC (permalink / raw)
To: Leif Lindholm, Linaro UEFI Mailman List, edk2-devel@lists.01.org,
G Gregory
Cc: Ard Biesheuvel, Guoheyi, wanghuiqiang, Ming Huang, Jason Zhang,
Mengfanrong, waip23
On 2017/9/29 11:19, Heyi Guo wrote:
Code can also be found in
github:https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1710-platforms-v5
Note:
1. There may be some minor issue (or even in SoC IP) that causes D05/3
into exception,
which was just found when we updated edk2 and edk2-platforms. We will
continue to investigate the issue.
This issue might be caused by below code:
---
a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c
+++
b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c
@@ -465,6 +465,10 @@ PciIoPciRead (
Address = (UINT8 *)&Dev->ConfigSpace + Offset;
Length = Count << ((UINTN)Width & 0x3);
+ if (Offset > sizeof (Dev->ConfigSpace)) {
+ Special process and return;
+ }
+
if (Offset + Length > sizeof (Dev->ConfigSpace)) {
//
// Read all zeroes for config space accesses beyond the first
If the input Offset is larger than sizeof (Dev->ConfigSpace), we should not
go on the following code, or else the memory between Buffer + sizeof
(Dev->ConfigSpace) - Offset ~ Buffer will be seriously corrupted.
The bug will be triggered when the PCD PcdTurnOffUsbLegacySupport is true
and HcCapParams contains some value larger than 0x40, for EHCI controller.
We'd better also turn off this PCD for our platforms, since there are no
real ExtendCap registers for our EHCI controller.
However, even after fixing this, we still got another exception for
alignment fault, which needs addtional time to investigate.
Regards,
Heyi
It boot successfully by switch the VirtualEhciPciIo with old one.
2. The separate patch (Add AddressTranslationOffset support) is a
prerequisite for this series
and it's source can also be found in above branch(rp-1710-platforms-v5).
Chenhui Sun (1):
Hisilicon/D03: Disable the function of PerfTuning
Heyi Guo (4):
Hisilicon/D05: Modify dsc and fdf file
Hisilicon/D03: Modify dsc and fdf file
Hisilicon: Fix the drivers use the same GUID issue
Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
Jason zhang (1):
Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
Ming Huang (5):
Hisilicon D03/D05: get firmware version from FIRMWARE_VER
Hisilicon/D05/Pcie: fix bug of size definition
D05/PCIe: Modify PcieRegionBase of secondary chip
D05/ACPI: Disable D05 SAS0 and SAS2
D05/ACPI: Modify I2C device
Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf
| 2 +-
Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf
| 2 +-
Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf
| 2 +-
Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf
| 2 +-
Platform/Hisilicon/D03/D03.dsc
| 12 ++-
Platform/Hisilicon/D03/D03.fdf
| 4 +-
Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf
| 2 +-
Platform/Hisilicon/D05/D05.dsc
| 83 +++++++++--------
Platform/Hisilicon/D05/D05.fdf
| 4 +-
Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
| 2 +-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
| 2 +-
Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
| 2 +-
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
| 38 ++++----
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
| 7 ++
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
| 94 +++++++++++++++++++-
Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
| 2 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
| 3 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
| 50 -----------
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
| 20 +----
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
| 8 +-
Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
| 10 +++
Silicon/Hisilicon/HisiPkg.dec
| 1 -
Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
| 2 +-
Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
| 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
| 2 +-
Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
| 2 +-
26 files changed, 203 insertions(+), 157 deletions(-)
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
` (11 preceding siblings ...)
2017-09-29 19:19 ` [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
@ 2017-10-05 12:54 ` Leif Lindholm
12 siblings, 0 replies; 14+ messages in thread
From: Leif Lindholm @ 2017-10-05 12:54 UTC (permalink / raw)
To: Heyi Guo
Cc: linaro-uefi, edk2-devel, graeme.gregory, ard.biesheuvel, guoheyi,
wanghuiqiang, huangming23, zhangjinsong2, mengfanrong, waip23
On Fri, Sep 29, 2017 at 11:19:39AM +0800, Heyi Guo wrote:
> Code can also be found in github:
> https://github.com/hisilicon/OpenPlatformPkg.git
> branch: rp-1710-platforms-v5
Series:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Pushed as 6b95ac45c6..a4591fe0b0
(with Yan's AddressTranslationOffset patch and my D02 indentation
fixup on top)
> Note:
> 1. There may be some minor issue (or even in SoC IP) that causes D05/3 into exception,
> which was just found when we updated edk2 and edk2-platforms. We will continue to investigate the issue.
> It boot successfully by switch the VirtualEhciPciIo with old one.
>
> 2. The separate patch (Add AddressTranslationOffset support) is a prerequisite for this series
> and it's source can also be found in above branch(rp-1710-platforms-v5).
>
> Chenhui Sun (1):
> Hisilicon/D03: Disable the function of PerfTuning
>
> Heyi Guo (4):
> Hisilicon/D05: Modify dsc and fdf file
> Hisilicon/D03: Modify dsc and fdf file
> Hisilicon: Fix the drivers use the same GUID issue
> Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
>
> Jason zhang (1):
> Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
>
> Ming Huang (5):
> Hisilicon D03/D05: get firmware version from FIRMWARE_VER
> Hisilicon/D05/Pcie: fix bug of size definition
> D05/PCIe: Modify PcieRegionBase of secondary chip
> D05/ACPI: Disable D05 SAS0 and SAS2
> D05/ACPI: Modify I2C device
>
> Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +-
> Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +-
> Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
> Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +-
> Platform/Hisilicon/D03/D03.dsc | 12 ++-
> Platform/Hisilicon/D03/D03.fdf | 4 +-
> Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +-
> Platform/Hisilicon/D05/D05.dsc | 83 +++++++++--------
> Platform/Hisilicon/D05/D05.fdf | 4 +-
> Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +-
> Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +-
> Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +-
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++----
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++
> Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++-
> Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +-
> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 +-
> Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 -----------
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +----
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +-
> Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++
> Silicon/Hisilicon/HisiPkg.dec | 1 -
> Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +-
> Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +-
> Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +-
> Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +-
> 26 files changed, 203 insertions(+), 157 deletions(-)
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-10-05 12:51 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 02/11] Hisilicon/D03: " Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
2017-09-29 19:19 ` [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-10-05 12:54 ` Leif Lindholm
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