From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::22d; helo=mail-wm0-x22d.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x22d.google.com (mail-wm0-x22d.google.com [IPv6:2a00:1450:400c:c09::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A523321E78217 for ; Fri, 6 Oct 2017 13:38:37 -0700 (PDT) Received: by mail-wm0-x22d.google.com with SMTP id b189so9700540wmd.4 for ; Fri, 06 Oct 2017 13:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Pd1VU6vIbjLWo7vHgyScO7i09y1ouI4Y8H/hxKpTQy8=; b=HlFEDmA0BsdBelcU4o14Q3cd9R7HXlQm18SCv0j1g9WmZyVdK5CpHjFs5P40SkliDS BxlDp8ZxAEmZSl9/yD+iII6G0jZoNvXyHwgzWeFRXNPKjTbREYpciXJ5D1lKZYeEekKb TABtY+tMFQrN8tpaXohk5bnADWSfbyQjYmx/8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Pd1VU6vIbjLWo7vHgyScO7i09y1ouI4Y8H/hxKpTQy8=; b=oG6Cga0NAncn4qMXLASJ3g9ucj1g8TCyz6PaNdSLAcihgCSwz7FdMQFcuUBxYtazCo lnuFAYDdJ1oEYLTtQJoCCCx3o9o4YUlMeVpOFbH1kPUQJDwbLuDx7qgu7hs/xjfCHFTP benmyd3P0lZDZy9WcNf6GAq2Vkz4ZszFMSgY3jOsD2YqvWuQ/ehWlOUkkcHAGeyK4jQ4 OKyG7E1GEMIuAa93l6e1LbU1inC35HWO2RtY+pQRrQl+zLR119u4mys7KfYrVgLN8Hzs ILEP/OCHx1iKnJsQEW/mGq5O5s9QVrDegdzb+mUAZ0GcEbZqB+dkKKvVZQmy3VVpNFOP lQzQ== X-Gm-Message-State: AMCzsaWuwu6dbYcuO4CokWA+lGNqscnm1qwvjfPMXvg7jYmw285OfM0z S8judrojQ29X0sVOWhF+Ao6LgIWRutQ= X-Google-Smtp-Source: AOwi7QAPzWIPV2VtM4dehttz0+RHbUHylf9oRQj6EgIMTsCuZMsm03zNspTJfmr+/0IiJaBb6SL0QQ== X-Received: by 10.28.57.4 with SMTP id g4mr2447556wma.92.1507322519853; Fri, 06 Oct 2017 13:41:59 -0700 (PDT) Received: from localhost.localdomain ([154.150.7.171]) by smtp.gmail.com with ESMTPSA id n191sm5600164wmd.7.2017.10.06.13.41.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 13:41:58 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Fri, 6 Oct 2017 21:41:52 +0100 Message-Id: <20171006204152.19376-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH] ArmPkg/ArmSmcPsciResetSystemLib: add support for warm reboot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Oct 2017 20:38:38 -0000 PSCI SYSTEM_RESET is specified as a cold reboot, which does not preserve the contents of DRAM. In version 1.1, a new reset method was introduced that allows a warm reboot to be requested. This is especially relevant for capsule update, given that it will invoke a warm reboot before processing the capsule, under the assumption that the capsule will still be in memory when the PEI phase is reentered. So wire up the [rather inaccurately named] EnterS3WithImmediateWake() entry point that the capsule update runtime uses to the new PSCI 1.1 warm reboot. Note that many PSCI implementations will not support this yet, so fall back to a cold reboot if warm reboot fails. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- I don't actually need this code for Synquacer, but given that I had already wrote it, we may just as well merge it. ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 10 +++++++--- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 14 ++++++++++++-- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h index 593a3ce729ce..41b086947eaa 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -57,10 +57,12 @@ #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32 0x84000005 #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x84000008 #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x84000009 +#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xc4000012 +#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH32 0x84000012 -/* The current PSCI version is: 0.2 */ -#define ARM_SMC_PSCI_VERSION_MAJOR 0 -#define ARM_SMC_PSCI_VERSION_MINOR 2 +/* The current PSCI version is: 1.1 */ +#define ARM_SMC_PSCI_VERSION_MAJOR 1 +#define ARM_SMC_PSCI_VERSION_MINOR 1 #define ARM_SMC_PSCI_VERSION \ ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR) @@ -93,4 +95,6 @@ #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING 2 +#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_WARM 0 + #endif diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index d6d26bce5009..ffd726554c0f 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -55,7 +55,17 @@ ResetWarm ( VOID ) { - // Map a warm reset into a cold reset + ARM_SMC_ARGS ArmSmcArgs; + +#if defined(MDE_CPU_AARCH64) + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64; +#else + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH32; +#endif + ArmSmcArgs.Arg1 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_WARM; + ArmCallSmc (&ArmSmcArgs); + + // Fall back to cold reset if unsupported ResetCold (); } @@ -89,7 +99,7 @@ EnterS3WithImmediateWake ( VOID ) { - // Not implemented + ResetWarm (); } /** -- 2.11.0