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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id w79sm5939333wrb.86.2017.10.10.07.44.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 07:44:01 -0700 (PDT) Date: Tue, 10 Oct 2017 15:43:59 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171010144359.z57jipw6hdlkyjxj@bivouac.eciton.net> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> <1507568462-28775-5-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1507568462-28775-5-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Oct 2017 14:40:37 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Oct 09, 2017 at 07:00:53PM +0200, Marcin Wojtas wrote: > From: Ard Biesheuvel > > To prevent cache coherency issues when chainloading via U-Boot, clean > and invalidate the FV image in the caches before re-enabling the MMU. Is this only relevant for chainloading (which is not the expected normal usage) or is it also important for warm-reset - for example for capsule update (at least from within OS)? If the former, I would prefer for this to be conditionalised, and not included by default. If the latter, please update the commit message. / Leif > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++++++++++++ > Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 +++ > 2 files changed, 18 insertions(+) > > diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S > index 72f8cfc..7544361 100644 > --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S > +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S > @@ -17,6 +17,21 @@ > > ASM_FUNC(ArmPlatformPeiBootAction) > mov x29, xzr > + > + MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress)) > + MOV32 (x3, FixedPcdGet32 (PcdFvSize)) > + add x3, x3, x0 > + > + mrs x1, ctr_el0 > + and x1, x1, #0xf // Dminline > + mov x2, #4 > + lsl x1, x2, x1 // by-VA stride for D-cache maintenance > + > +0:dc civac, x0 > + add x0, x0, x1 > + cmp x0, x3 > + b.lt 0b > + > ret > > //UINTN > diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > index 2e198c3..6966683 100644 > --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > @@ -67,5 +67,8 @@ > gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > gArmTokenSpaceGuid.PcdArmPrimaryCore > > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdFvSize > + > [Ppis] > gArmMpCoreInfoPpiGuid > -- > 1.8.3.1 >