[platforms: PATCH 00/13] Armada 7k/8k - misc improvements

[platforms: PATCH 00/13] Armada 7k/8k - misc improvements

[Marcin Wojtas]

Hi,

This patchset is a first part of general platform support improvements.
It consists of a series of short changes, maybe except for the
initialization phase DXE driver.

The patches are available in the github (from now on pushed as a branch):
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/misc-upstream-r20171009

I'm looking forward to your comments or remarks.

Best regards,
Marcin

Ard Biesheuvel (11):
  Marvell/Armada: Switch to dynamic PCDs
  Marvell/Armada: Armada70x0Lib: Terminate call stack list at entry
  Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot
  Marvell/Armada: Use 4k/64k aligned sections for DXE/DXE-rt modules
  Marvell/Armada: Switch to generic BDS
  Marvell/Armada: Re-enable driver model diagnostics PCDs
  Marvell/Armada: Modify GICC alias
  Marvell/Armada: Disable PerformanceLibrary
  Marvell/Armada: Switch to unicore PrePi
  Marvell/Armada: Remove outdated SEC alignment override
  Marvell/Armada: Add the UefiPxeBcDxe driver

Marcin Wojtas (2):
  Marvell/Armada: Introduce platform initialization driver
  Marvell/Documentation: Follow EDK2 coding style in the PortingGuide

 Platform/Marvell/Armada/Armada.dsc.inc                                    |  55 +-
 Platform/Marvell/Armada/Armada70x0.fdf                                    |  23 +-
 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c                 |  44 ++
 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf               |  44 ++
 Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S |  16 +
 Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c             |  11 -
 Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf           |   3 +
 Platform/Marvell/Marvell.dec                                              |   5 +
 Silicon/Marvell/Documentation/PortingGuide.txt                            | 800 ++++++++++----------
 9 files changed, 566 insertions(+), 435 deletions(-)
 create mode 100644 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
 create mode 100644 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf

-- 
1.8.3.1

[platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

In order to enable modification of dynamic PCD's for the libraries
and DXE drivers, this patch introduces new driver. It is
executed prior to other drivers. Mpp, ComPhy and Utmi libraries
initialization were moved from PrePi stage to DXE.

To force the correct driver dispatch sequence, introduce a protocol GUID
and install the protocol as a NULL protocol when PlatInitDxe executes.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Armada/Armada.dsc.inc                        |  3 ++
 Platform/Marvell/Armada/Armada70x0.fdf                        |  5 +++
 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c     | 44 ++++++++++++++++++++
 Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf   | 44 ++++++++++++++++++++
 Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 -----
 Platform/Marvell/Marvell.dec                                  |  5 +++
 6 files changed, 101 insertions(+), 11 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 89fb7e7..417bb0c 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -378,6 +378,9 @@
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
 
+  # Platform Initialization
+  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
+
   # Platform drivers
   Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
   MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index c861e78..763d76a 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -89,6 +89,11 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
 
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
 
+  #
+  # Platform Initialization
+  #
+  INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
+
   # PI DXE Drivers producing Architectural Protocols (EFI Services)
   INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
new file mode 100644
index 0000000..919454b
--- /dev/null
+++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
@@ -0,0 +1,44 @@
+/** @file
+  Copyright (C) Marvell International Ltd. and its affiliates
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/MppLib.h>
+#include <Library/MvComPhyLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UtmiPhyLib.h>
+
+EFI_STATUS
+EFIAPI
+ArmadaPlatInitDxeEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS    Status;
+
+  DEBUG ((DEBUG_ERROR, "\nArmada Platform Init\n\n"));
+
+  Status = gBS->InstallProtocolInterface (&ImageHandle,
+                  &gMarvellPlatformInitCompleteProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  MvComPhyInit ();
+  UtmiPhyInit ();
+  MppInitialize ();
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
new file mode 100644
index 0000000..29abcaf
--- /dev/null
+++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
@@ -0,0 +1,44 @@
+#/* @file
+#  Copyright (C) Marvell International Ltd. and its affiliates
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = PlatInitDxe
+  FILE_GUID                      = 8c66f65b-08a6-4c91-b993-ff81e0adf818
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = ArmadaPlatInitDxeEntryPoint
+
+[Sources]
+  PlatInitDxe.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/Marvell/Marvell.dec
+
+[LibraryClasses]
+  ComPhyLib
+  DebugLib
+  MppLib
+  PcdLib
+  TimerLib
+  UefiDriverEntryPoint
+  UtmiPhyLib
+
+[Protocols]
+  gMarvellPlatformInitCompleteProtocolGuid    ## PRODUCES
+
+[Depex]
+  TRUE
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
index 0ed310f..968d28f 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
@@ -15,12 +15,8 @@
 
 #include <Library/ArmLib.h>
 #include <Library/ArmPlatformLib.h>
-#include <Library/MppLib.h>
-#include <Library/MvComPhyLib.h>
-#include <Library/UtmiPhyLib.h>
 #include <Ppi/ArmMpCoreInfo.h>
 
-
 ARM_CORE_INFO mArmada7040MpCoreInfoTable[] = {
   {
     // Cluster 0, Core 0
@@ -90,13 +86,6 @@ ArmPlatformInitialize (
   IN  UINTN                     MpId
   )
 {
-  if (!ArmPlatformIsPrimaryCore (MpId)) {
-    return RETURN_SUCCESS;
-  }
-
-  MvComPhyInit ();
-  UtmiPhyInit ();
-  MppInitialize ();
   return RETURN_SUCCESS;
 }
 
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 0902086..e7d7c2c 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -56,6 +56,11 @@
   gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }
   gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
 
+[Protocols]
+  # installed as a protocol by PlatInitDxe to force ordering between DXE drivers
+  # that depend on the lowlevel platform initialization having been completed
+  gMarvellPlatformInitCompleteProtocolGuid = { 0x465b8cf7, 0x016f, 0x4ba6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } }
+
 [PcdsFixedAtBuild.common]
 #MPP
   gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001
-- 
1.8.3.1

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
> In order to enable modification of dynamic PCD's for the libraries
> and DXE drivers, this patch introduces new driver. It is
> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
> initialization were moved from PrePi stage to DXE.
> 
> To force the correct driver dispatch sequence, introduce a protocol GUID
> and install the protocol as a NULL protocol when PlatInitDxe executes.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

What does Ard's Signed-off-by signify here?
(I know the authorship on some of these is a bit blurred, since you've
been working together, but I'd like to be clear.)

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc                        |  3 ++
>  Platform/Marvell/Armada/Armada70x0.fdf                        |  5 +++
>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c     | 44 ++++++++++++++++++++
>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf   | 44 ++++++++++++++++++++
>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 -----
>  Platform/Marvell/Marvell.dec                                  |  5 +++
>  6 files changed, 101 insertions(+), 11 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 89fb7e7..417bb0c 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -378,6 +378,9 @@
>    ArmPkg/Drivers/TimerDxe/TimerDxe.inf
>    ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
>  
> +  # Platform Initialization
> +  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> +
>    # Platform drivers
>    Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
>    MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index c861e78..763d76a 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -89,6 +89,11 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>  
>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>  
> +  #
> +  # Platform Initialization
> +  #
> +  INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> +
>    # PI DXE Drivers producing Architectural Protocols (EFI Services)
>    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
>    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
> new file mode 100644
> index 0000000..919454b
> --- /dev/null
> +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
> @@ -0,0 +1,44 @@
> +/** @file
> +  Copyright (C) Marvell International Ltd. and its affiliates

We normally need a year here as well.
If Ard has co-authored parts, I guess we should have Linaro copyright
notice on affected files as well.

Content of the patch is fine.

/
    Leif

> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/MppLib.h>
> +#include <Library/MvComPhyLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UtmiPhyLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaPlatInitDxeEntryPoint (
> +  IN EFI_HANDLE         ImageHandle,
> +  IN EFI_SYSTEM_TABLE   *SystemTable
> +  )
> +{
> +  EFI_STATUS    Status;
> +
> +  DEBUG ((DEBUG_ERROR, "\nArmada Platform Init\n\n"));
> +
> +  Status = gBS->InstallProtocolInterface (&ImageHandle,
> +                  &gMarvellPlatformInitCompleteProtocolGuid,
> +                  EFI_NATIVE_INTERFACE,
> +                  NULL);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  MvComPhyInit ();
> +  UtmiPhyInit ();
> +  MppInitialize ();
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> new file mode 100644
> index 0000000..29abcaf
> --- /dev/null
> +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> @@ -0,0 +1,44 @@
> +#/* @file
> +#  Copyright (C) Marvell International Ltd. and its affiliates
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#*/
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = PlatInitDxe
> +  FILE_GUID                      = 8c66f65b-08a6-4c91-b993-ff81e0adf818
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +
> +  ENTRY_POINT                    = ArmadaPlatInitDxeEntryPoint
> +
> +[Sources]
> +  PlatInitDxe.c
> +
> +[Packages]
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  Platform/Marvell/Marvell.dec
> +
> +[LibraryClasses]
> +  ComPhyLib
> +  DebugLib
> +  MppLib
> +  PcdLib
> +  TimerLib
> +  UefiDriverEntryPoint
> +  UtmiPhyLib
> +
> +[Protocols]
> +  gMarvellPlatformInitCompleteProtocolGuid    ## PRODUCES
> +
> +[Depex]
> +  TRUE
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
> index 0ed310f..968d28f 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c
> @@ -15,12 +15,8 @@
>  
>  #include <Library/ArmLib.h>
>  #include <Library/ArmPlatformLib.h>
> -#include <Library/MppLib.h>
> -#include <Library/MvComPhyLib.h>
> -#include <Library/UtmiPhyLib.h>
>  #include <Ppi/ArmMpCoreInfo.h>
>  
> -
>  ARM_CORE_INFO mArmada7040MpCoreInfoTable[] = {
>    {
>      // Cluster 0, Core 0
> @@ -90,13 +86,6 @@ ArmPlatformInitialize (
>    IN  UINTN                     MpId
>    )
>  {
> -  if (!ArmPlatformIsPrimaryCore (MpId)) {
> -    return RETURN_SUCCESS;
> -  }
> -
> -  MvComPhyInit ();
> -  UtmiPhyInit ();
> -  MppInitialize ();
>    return RETURN_SUCCESS;
>  }
>  
> diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
> index 0902086..e7d7c2c 100644
> --- a/Platform/Marvell/Marvell.dec
> +++ b/Platform/Marvell/Marvell.dec
> @@ -56,6 +56,11 @@
>    gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }
>    gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
>  
> +[Protocols]
> +  # installed as a protocol by PlatInitDxe to force ordering between DXE drivers
> +  # that depend on the lowlevel platform initialization having been completed
> +  gMarvellPlatformInitCompleteProtocolGuid = { 0x465b8cf7, 0x016f, 0x4ba6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } }
> +
>  [PcdsFixedAtBuild.common]
>  #MPP
>    gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001
> -- 
> 1.8.3.1
> 

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

Hi Leif,

2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
>> In order to enable modification of dynamic PCD's for the libraries
>> and DXE drivers, this patch introduces new driver. It is
>> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>> initialization were moved from PrePi stage to DXE.
>>
>> To force the correct driver dispatch sequence, introduce a protocol GUID
>> and install the protocol as a NULL protocol when PlatInitDxe executes.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> What does Ard's Signed-off-by signify here?
> (I know the authorship on some of these is a bit blurred, since you've
> been working together, but I'd like to be clear.)

These were the lines, introducing/installing protocol GUID stuff. It
was in a small separate patch, but I squashed it into bigger one.

>
>> ---
>>  Platform/Marvell/Armada/Armada.dsc.inc                        |  3 ++
>>  Platform/Marvell/Armada/Armada70x0.fdf                        |  5 +++
>>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c     | 44 ++++++++++++++++++++
>>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf   | 44 ++++++++++++++++++++
>>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 -----
>>  Platform/Marvell/Marvell.dec                                  |  5 +++
>>  6 files changed, 101 insertions(+), 11 deletions(-)
>>
>> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
>> index 89fb7e7..417bb0c 100644
>> --- a/Platform/Marvell/Armada/Armada.dsc.inc
>> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
>> @@ -378,6 +378,9 @@
>>    ArmPkg/Drivers/TimerDxe/TimerDxe.inf
>>    ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
>>
>> +  # Platform Initialization
>> +  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
>> +
>>    # Platform drivers
>>    Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
>>    MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
>> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
>> index c861e78..763d76a 100644
>> --- a/Platform/Marvell/Armada/Armada70x0.fdf
>> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
>> @@ -89,6 +89,11 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>>
>>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>>
>> +  #
>> +  # Platform Initialization
>> +  #
>> +  INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
>> +
>>    # PI DXE Drivers producing Architectural Protocols (EFI Services)
>>    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
>>    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
>> diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
>> new file mode 100644
>> index 0000000..919454b
>> --- /dev/null
>> +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
>> @@ -0,0 +1,44 @@
>> +/** @file
>> +  Copyright (C) Marvell International Ltd. and its affiliates
>
> We normally need a year here as well.
> If Ard has co-authored parts, I guess we should have Linaro copyright
> notice on affected files as well.

I have no problem with that, if you find it appropriate, given my
explanation above.

>
> Content of the patch is fine.
>

Ok, thanks!
Marcin

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Leif Lindholm]

On Tue, Oct 10, 2017 at 04:45:10PM +0200, Marcin Wojtas wrote:
> Hi Leif,
> 
> 2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> > On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
> >> In order to enable modification of dynamic PCD's for the libraries
> >> and DXE drivers, this patch introduces new driver. It is
> >> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
> >> initialization were moved from PrePi stage to DXE.
> >>
> >> To force the correct driver dispatch sequence, introduce a protocol GUID
> >> and install the protocol as a NULL protocol when PlatInitDxe executes.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >
> > What does Ard's Signed-off-by signify here?
> > (I know the authorship on some of these is a bit blurred, since you've
> > been working together, but I'd like to be clear.)
> 
> These were the lines, introducing/installing protocol GUID stuff. It
> was in a small separate patch, but I squashed it into bigger one.

Personally, I would in this instance do:
<me>
Ard
<me>

It's verbose, but reasonably clear.

> >
> >> ---
> >>  Platform/Marvell/Armada/Armada.dsc.inc                        |  3 ++
> >>  Platform/Marvell/Armada/Armada70x0.fdf                        |  5 +++
> >>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c     | 44 ++++++++++++++++++++
> >>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf   | 44 ++++++++++++++++++++
> >>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 -----
> >>  Platform/Marvell/Marvell.dec                                  |  5 +++
> >>  6 files changed, 101 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> >> index 89fb7e7..417bb0c 100644
> >> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> >> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> >> @@ -378,6 +378,9 @@
> >>    ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> >>    ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> >>
> >> +  # Platform Initialization
> >> +  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> >> +
> >>    # Platform drivers
> >>    Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
> >>    MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
> >> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> >> index c861e78..763d76a 100644
> >> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> >> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> >> @@ -89,6 +89,11 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
> >>
> >>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
> >>
> >> +  #
> >> +  # Platform Initialization
> >> +  #
> >> +  INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
> >> +
> >>    # PI DXE Drivers producing Architectural Protocols (EFI Services)
> >>    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> >>    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> >> diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
> >> new file mode 100644
> >> index 0000000..919454b
> >> --- /dev/null
> >> +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
> >> @@ -0,0 +1,44 @@
> >> +/** @file
> >> +  Copyright (C) Marvell International Ltd. and its affiliates
> >
> > We normally need a year here as well.
> > If Ard has co-authored parts, I guess we should have Linaro copyright
> > notice on affected files as well.
> 
> I have no problem with that, if you find it appropriate, given my
> explanation above.

Personally I dont mind much, but I think it would be more correct.

/
    Leif

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

2017-10-10 17:03 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Tue, Oct 10, 2017 at 04:45:10PM +0200, Marcin Wojtas wrote:
>> Hi Leif,
>>
>> 2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> > On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
>> >> In order to enable modification of dynamic PCD's for the libraries
>> >> and DXE drivers, this patch introduces new driver. It is
>> >> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>> >> initialization were moved from PrePi stage to DXE.
>> >>
>> >> To force the correct driver dispatch sequence, introduce a protocol GUID
>> >> and install the protocol as a NULL protocol when PlatInitDxe executes.
>> >>
>> >> Contributed-under: TianoCore Contribution Agreement 1.1
>> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >
>> > What does Ard's Signed-off-by signify here?
>> > (I know the authorship on some of these is a bit blurred, since you've
>> > been working together, but I'd like to be clear.)
>>
>> These were the lines, introducing/installing protocol GUID stuff. It
>> was in a small separate patch, but I squashed it into bigger one.
>
> Personally, I would in this instance do:
> <me>
> Ard
> <me>
>
> It's verbose, but reasonably clear.
>

How about:

In order to enable modification of dynamic PCD's for the libraries
and DXE drivers, this patch introduces new driver. It is
executed prior to other drivers. Mpp, ComPhy and Utmi libraries
initialization were moved from PrePi stage to DXE.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>

To force the correct driver dispatch sequence, introduce a protocol GUID
and install the protocol as a NULL protocol when PlatInitDxe executes.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

?

Was that, what you meant?

>> >
>> >> ---
>> >>  Platform/Marvell/Armada/Armada.dsc.inc                        |  3 ++
>> >>  Platform/Marvell/Armada/Armada70x0.fdf                        |  5 +++
>> >>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c     | 44 ++++++++++++++++++++
>> >>  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf   | 44 ++++++++++++++++++++
>> >>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 -----
>> >>  Platform/Marvell/Marvell.dec                                  |  5 +++
>> >>  6 files changed, 101 insertions(+), 11 deletions(-)
>> >>
>> >> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
>> >> index 89fb7e7..417bb0c 100644
>> >> --- a/Platform/Marvell/Armada/Armada.dsc.inc
>> >> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
>> >> @@ -378,6 +378,9 @@
>> >>    ArmPkg/Drivers/TimerDxe/TimerDxe.inf
>> >>    ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
>> >>
>> >> +  # Platform Initialization
>> >> +  Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
>> >> +
>> >>    # Platform drivers
>> >>    Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
>> >>    MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
>> >> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
>> >> index c861e78..763d76a 100644
>> >> --- a/Platform/Marvell/Armada/Armada70x0.fdf
>> >> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
>> >> @@ -89,6 +89,11 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>> >>
>> >>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>> >>
>> >> +  #
>> >> +  # Platform Initialization
>> >> +  #
>> >> +  INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
>> >> +
>> >>    # PI DXE Drivers producing Architectural Protocols (EFI Services)
>> >>    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
>> >>    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
>> >> diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
>> >> new file mode 100644
>> >> index 0000000..919454b
>> >> --- /dev/null
>> >> +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c
>> >> @@ -0,0 +1,44 @@
>> >> +/** @file
>> >> +  Copyright (C) Marvell International Ltd. and its affiliates
>> >
>> > We normally need a year here as well.
>> > If Ard has co-authored parts, I guess we should have Linaro copyright
>> > notice on affected files as well.
>>
>> I have no problem with that, if you find it appropriate, given my
>> explanation above.
>
> Personally I dont mind much, but I think it would be more correct.
>

Ok, will add it in v2.

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Leif Lindholm]

On Tue, Oct 10, 2017 at 05:06:42PM +0200, Marcin Wojtas wrote:
> 2017-10-10 17:03 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> > On Tue, Oct 10, 2017 at 04:45:10PM +0200, Marcin Wojtas wrote:
> >> Hi Leif,
> >>
> >> 2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> >> > On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
> >> >> In order to enable modification of dynamic PCD's for the libraries
> >> >> and DXE drivers, this patch introduces new driver. It is
> >> >> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
> >> >> initialization were moved from PrePi stage to DXE.
> >> >>
> >> >> To force the correct driver dispatch sequence, introduce a protocol GUID
> >> >> and install the protocol as a NULL protocol when PlatInitDxe executes.
> >> >>
> >> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> >
> >> > What does Ard's Signed-off-by signify here?
> >> > (I know the authorship on some of these is a bit blurred, since you've
> >> > been working together, but I'd like to be clear.)
> >>
> >> These were the lines, introducing/installing protocol GUID stuff. It
> >> was in a small separate patch, but I squashed it into bigger one.
> >
> > Personally, I would in this instance do:
> > <me>
> > Ard
> > <me>
> >
> > It's verbose, but reasonably clear.
> >
> 
> How about:
> 
> In order to enable modification of dynamic PCD's for the libraries
> and DXE drivers, this patch introduces new driver. It is
> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
> initialization were moved from PrePi stage to DXE.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> 
> To force the correct driver dispatch sequence, introduce a protocol GUID
> and install the protocol as a NULL protocol when PlatInitDxe executes.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> 
> ?
> 
> Was that, what you meant?

I think Contibuted-under: still needs to come first.

I don't think we have an explicit policy for how to deal with
multi-contributor patches. The ones we do see tend to just keep a
single commit message and list the contributors.

In Linux. it would be something like
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
[Introduce protocol GUID to force correct driver dispatch order]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

I would be quite happy to use the same format here.

/
    Leif

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Ard Biesheuvel]

On 10 October 2017 at 16:26, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Tue, Oct 10, 2017 at 05:06:42PM +0200, Marcin Wojtas wrote:
>> 2017-10-10 17:03 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> > On Tue, Oct 10, 2017 at 04:45:10PM +0200, Marcin Wojtas wrote:
>> >> Hi Leif,
>> >>
>> >> 2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> >> > On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
>> >> >> In order to enable modification of dynamic PCD's for the libraries
>> >> >> and DXE drivers, this patch introduces new driver. It is
>> >> >> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>> >> >> initialization were moved from PrePi stage to DXE.
>> >> >>
>> >> >> To force the correct driver dispatch sequence, introduce a protocol GUID
>> >> >> and install the protocol as a NULL protocol when PlatInitDxe executes.
>> >> >>
>> >> >> Contributed-under: TianoCore Contribution Agreement 1.1
>> >> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> >
>> >> > What does Ard's Signed-off-by signify here?
>> >> > (I know the authorship on some of these is a bit blurred, since you've
>> >> > been working together, but I'd like to be clear.)
>> >>
>> >> These were the lines, introducing/installing protocol GUID stuff. It
>> >> was in a small separate patch, but I squashed it into bigger one.
>> >
>> > Personally, I would in this instance do:
>> > <me>
>> > Ard
>> > <me>
>> >
>> > It's verbose, but reasonably clear.
>> >
>>
>> How about:
>>
>> In order to enable modification of dynamic PCD's for the libraries
>> and DXE drivers, this patch introduces new driver. It is
>> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>> initialization were moved from PrePi stage to DXE.
>>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>
>> To force the correct driver dispatch sequence, introduce a protocol GUID
>> and install the protocol as a NULL protocol when PlatInitDxe executes.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>
>> ?
>>
>> Was that, what you meant?
>
> I think Contibuted-under: still needs to come first.
>
> I don't think we have an explicit policy for how to deal with
> multi-contributor patches. The ones we do see tend to just keep a
> single commit message and list the contributors.
>
> In Linux. it would be something like
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> [Introduce protocol GUID to force correct driver dispatch order]
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>
> I would be quite happy to use the same format here.
>

Well, Tianocore still conflates authorship with a statement regarding
the origin of the contribution. I wonder how this is supposed to work
when Linaro engineers such as myself contribute code that was authored
by engineers working in member companies, e.g., Socionext. The license
and the contract that company has with Linaro give me the right to
contribute that code, but that does not make me the author, and I
cannot add a Signed-off-by that wasn't present when we received the
code (even if I knew the name of the author)

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

2017-10-10 22:36 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> On 10 October 2017 at 16:26, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>> On Tue, Oct 10, 2017 at 05:06:42PM +0200, Marcin Wojtas wrote:
>>> 2017-10-10 17:03 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>>> > On Tue, Oct 10, 2017 at 04:45:10PM +0200, Marcin Wojtas wrote:
>>> >> Hi Leif,
>>> >>
>>> >> 2017-10-10 16:37 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>>> >> > On Mon, Oct 09, 2017 at 07:00:50PM +0200, Marcin Wojtas wrote:
>>> >> >> In order to enable modification of dynamic PCD's for the libraries
>>> >> >> and DXE drivers, this patch introduces new driver. It is
>>> >> >> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>>> >> >> initialization were moved from PrePi stage to DXE.
>>> >> >>
>>> >> >> To force the correct driver dispatch sequence, introduce a protocol GUID
>>> >> >> and install the protocol as a NULL protocol when PlatInitDxe executes.
>>> >> >>
>>> >> >> Contributed-under: TianoCore Contribution Agreement 1.1
>>> >> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>> >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>> >> >
>>> >> > What does Ard's Signed-off-by signify here?
>>> >> > (I know the authorship on some of these is a bit blurred, since you've
>>> >> > been working together, but I'd like to be clear.)
>>> >>
>>> >> These were the lines, introducing/installing protocol GUID stuff. It
>>> >> was in a small separate patch, but I squashed it into bigger one.
>>> >
>>> > Personally, I would in this instance do:
>>> > <me>
>>> > Ard
>>> > <me>
>>> >
>>> > It's verbose, but reasonably clear.
>>> >
>>>
>>> How about:
>>>
>>> In order to enable modification of dynamic PCD's for the libraries
>>> and DXE drivers, this patch introduces new driver. It is
>>> executed prior to other drivers. Mpp, ComPhy and Utmi libraries
>>> initialization were moved from PrePi stage to DXE.
>>>
>>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>>
>>> To force the correct driver dispatch sequence, introduce a protocol GUID
>>> and install the protocol as a NULL protocol when PlatInitDxe executes.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>>
>>> ?
>>>
>>> Was that, what you meant?
>>
>> I think Contibuted-under: still needs to come first.
>>
>> I don't think we have an explicit policy for how to deal with
>> multi-contributor patches. The ones we do see tend to just keep a
>> single commit message and list the contributors.
>>
>> In Linux. it would be something like
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> [Introduce protocol GUID to force correct driver dispatch order]
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>
>> I would be quite happy to use the same format here.
>>
>
> Well, Tianocore still conflates authorship with a statement regarding
> the origin of the contribution. I wonder how this is supposed to work
> when Linaro engineers such as myself contribute code that was authored
> by engineers working in member companies, e.g., Socionext. The license
> and the contract that company has with Linaro give me the right to
> contribute that code, but that does not make me the author, and I
> cannot add a Signed-off-by that wasn't present when we received the
> code (even if I knew the name of the author)

I think it's fairly easy thing, needlessly twisted... How does above
reflect the requirement to add contributor sign-off to someone else's
patch (with his authorship and original sign-off - should they be
removed?)?

Anyway, let's make a quick decision here - should I submit patch with
linux-like signatures and description? Or should I split the patches?

Best regards,
Marcin

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Leif Lindholm]

On Wed, Oct 11, 2017 at 06:53:05AM +0200, Marcin Wojtas wrote:
> >> I think Contibuted-under: still needs to come first.
> >>
> >> I don't think we have an explicit policy for how to deal with
> >> multi-contributor patches. The ones we do see tend to just keep a
> >> single commit message and list the contributors.
> >>
> >> In Linux. it would be something like
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> [Introduce protocol GUID to force correct driver dispatch order]
> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >>
> >> I would be quite happy to use the same format here.
> >>
> >
> > Well, Tianocore still conflates authorship with a statement regarding
> > the origin of the contribution. I wonder how this is supposed to work
> > when Linaro engineers such as myself contribute code that was authored
> > by engineers working in member companies, e.g., Socionext. The license
> > and the contract that company has with Linaro give me the right to
> > contribute that code, but that does not make me the author, and I
> > cannot add a Signed-off-by that wasn't present when we received the
> > code (even if I knew the name of the author)
> 
> I think it's fairly easy thing, needlessly twisted... How does above
> reflect the requirement to add contributor sign-off to someone else's
> patch (with his authorship and original sign-off - should they be
> removed?)?

Well, we're not debating this because it's critical for this one
patch, but because it would be useful to have a precedent.

> Anyway, let's make a quick decision here - should I submit patch with
> linux-like signatures and description? Or should I split the patches?

Let's put it this way - if you split the patches, you remove this
series from abovementioned discussion :)

/
    Leif

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

Leif,

2017-10-11 10:32 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Wed, Oct 11, 2017 at 06:53:05AM +0200, Marcin Wojtas wrote:
>> >> I think Contibuted-under: still needs to come first.
>> >>
>> >> I don't think we have an explicit policy for how to deal with
>> >> multi-contributor patches. The ones we do see tend to just keep a
>> >> single commit message and list the contributors.
>> >>
>> >> In Linux. it would be something like
>> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> [Introduce protocol GUID to force correct driver dispatch order]
>> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >>
>> >> I would be quite happy to use the same format here.
>> >>
>> >
>> > Well, Tianocore still conflates authorship with a statement regarding
>> > the origin of the contribution. I wonder how this is supposed to work
>> > when Linaro engineers such as myself contribute code that was authored
>> > by engineers working in member companies, e.g., Socionext. The license
>> > and the contract that company has with Linaro give me the right to
>> > contribute that code, but that does not make me the author, and I
>> > cannot add a Signed-off-by that wasn't present when we received the
>> > code (even if I knew the name of the author)
>>
>> I think it's fairly easy thing, needlessly twisted... How does above
>> reflect the requirement to add contributor sign-off to someone else's
>> patch (with his authorship and original sign-off - should they be
>> removed?)?
>
> Well, we're not debating this because it's critical for this one
> patch, but because it would be useful to have a precedent.
>

I'm totally fine with precedences, it's rather your call, whether it's
accepted or not :) My three arugments are:
- I have still a lot patches ahead and it's very likely such situation
may occur again.
- Needless to say, it may happen again in the development of other platforms.
- Artificially splitting patches seems to me as not really needed and
I'm not convinced to its justification.

>> Anyway, let's make a quick decision here - should I submit patch with
>> linux-like signatures and description? Or should I split the patches?
>
> Let's put it this way - if you split the patches, you remove this
> series from abovementioned discussion :)
>

If you're ok with it, I'd go with single patch, but I can do it either
way - I think I'm not to decide, what's best from maintainers' point
of view :)

Best regards,
Marcin

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Leif Lindholm]

On Wed, Oct 11, 2017 at 10:43:14AM +0200, Marcin Wojtas wrote:
> >> I think it's fairly easy thing, needlessly twisted... How does above
> >> reflect the requirement to add contributor sign-off to someone else's
> >> patch (with his authorship and original sign-off - should they be
> >> removed?)?
> >
> > Well, we're not debating this because it's critical for this one
> > patch, but because it would be useful to have a precedent.
> 
> I'm totally fine with precedences, it's rather your call, whether it's
> accepted or not :) My three arugments are:
> - I have still a lot patches ahead and it's very likely such situation
> may occur again.
> - Needless to say, it may happen again in the development of other platforms.
> - Artificially splitting patches seems to me as not really needed and
> I'm not convinced to its justification.
> 
> >> Anyway, let's make a quick decision here - should I submit patch with
> >> linux-like signatures and description? Or should I split the patches?
> >
> > Let's put it this way - if you split the patches, you remove this
> > series from abovementioned discussion :)
> 
> If you're ok with it, I'd go with single patch, but I can do it either
> way - I think I'm not to decide, what's best from maintainers' point
> of view :)

For now, I would take the single patch with Linux-style description,
like the example I sent earlier.

/
    Leif

Re: [platforms: PATCH 01/13] Marvell/Armada: Introduce platform initialization driver

[Marcin Wojtas]

2017-10-11 11:14 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Wed, Oct 11, 2017 at 10:43:14AM +0200, Marcin Wojtas wrote:
>> >> I think it's fairly easy thing, needlessly twisted... How does above
>> >> reflect the requirement to add contributor sign-off to someone else's
>> >> patch (with his authorship and original sign-off - should they be
>> >> removed?)?
>> >
>> > Well, we're not debating this because it's critical for this one
>> > patch, but because it would be useful to have a precedent.
>>
>> I'm totally fine with precedences, it's rather your call, whether it's
>> accepted or not :) My three arugments are:
>> - I have still a lot patches ahead and it's very likely such situation
>> may occur again.
>> - Needless to say, it may happen again in the development of other platforms.
>> - Artificially splitting patches seems to me as not really needed and
>> I'm not convinced to its justification.
>>
>> >> Anyway, let's make a quick decision here - should I submit patch with
>> >> linux-like signatures and description? Or should I split the patches?
>> >
>> > Let's put it this way - if you split the patches, you remove this
>> > series from abovementioned discussion :)
>>
>> If you're ok with it, I'd go with single patch, but I can do it either
>> way - I think I'm not to decide, what's best from maintainers' point
>> of view :)
>
> For now, I would take the single patch with Linux-style description,
> like the example I sent earlier.
>

Great, will send it in v2.

Thanks,
Marcin

[platforms: PATCH 02/13] Marvell/Armada: Switch to dynamic PCDs

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

For full functionality, including HII forms wired to non-volatile UEFI
variables, we need dynamic PCDs as well. So let's enable those.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 10 +++++++---
 Platform/Marvell/Armada/Armada70x0.fdf |  1 +
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 417bb0c..433892e 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -67,8 +67,7 @@
   UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
   UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
 
-  # Assume everything is fixed at build. do not use runtime PCD feature
-  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
 
   BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
 
@@ -150,6 +149,7 @@
   PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
   PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
   ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
 
 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
   MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
@@ -368,10 +368,14 @@
   # DXE
   MdeModulePkg/Core/Dxe/DxeMain.inf {
     <LibraryClasses>
-      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
       NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
   }
 
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
   # Architectural Protocols DXE
   ArmPkg/Drivers/CpuDxe/CpuDxe.inf
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index 763d76a..b3d1c60 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -95,6 +95,7 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
   INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
 
   # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
   INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
-- 
1.8.3.1

Re: [platforms: PATCH 02/13] Marvell/Armada: Switch to dynamic PCDs

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:51PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> For full functionality, including HII forms wired to non-volatile UEFI
> variables, we need dynamic PCDs as well. So let's enable those.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 10 +++++++---
>  Platform/Marvell/Armada/Armada70x0.fdf |  1 +
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 417bb0c..433892e 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -67,8 +67,7 @@
>    UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
>    UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>  
> -  # Assume everything is fixed at build. do not use runtime PCD feature
> -  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>  
>    BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
>  
> @@ -150,6 +149,7 @@
>    PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
>    PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
>    ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
> +  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>  
>  [LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
>    MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> @@ -368,10 +368,14 @@
>    # DXE
>    MdeModulePkg/Core/Dxe/DxeMain.inf {
>      <LibraryClasses>
> -      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>        NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
>    }
>  
> +  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +
>    # Architectural Protocols DXE
>    ArmPkg/Drivers/CpuDxe/CpuDxe.inf
>    ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index 763d76a..b3d1c60 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -95,6 +95,7 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>    INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf
>  
>    # PI DXE Drivers producing Architectural Protocols (EFI Services)
> +  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>    INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
>    INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
>    INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> -- 
> 1.8.3.1
> 

[platforms: PATCH 03/13] Marvell/Armada: Armada70x0Lib: Terminate call stack list at entry

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

To avoid dereferencing junk when walking the call stack in exception
handlers (which may prevent us from getting a full backtrace), set
the frame pointer to 0x0 when first entering UEFI.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
index 9265636..72f8cfc 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
@@ -16,6 +16,7 @@
 #include <Library/ArmLib.h>
 
 ASM_FUNC(ArmPlatformPeiBootAction)
+  mov   x29, xzr
   ret
 
 //UINTN
-- 
1.8.3.1

Re: [platforms: PATCH 03/13] Marvell/Armada: Armada70x0Lib: Terminate call stack list at entry

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:52PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> To avoid dereferencing junk when walking the call stack in exception
> handlers (which may prevent us from getting a full backtrace), set
> the frame pointer to 0x0 when first entering UEFI.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> index 9265636..72f8cfc 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> @@ -16,6 +16,7 @@
>  #include <Library/ArmLib.h>
>  
>  ASM_FUNC(ArmPlatformPeiBootAction)
> +  mov   x29, xzr
>    ret
>  
>  //UINTN
> -- 
> 1.8.3.1
> 

[platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

To prevent cache coherency issues when chainloading via U-Boot, clean
and invalidate the FV image in the caches before re-enabling the MMU.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++++++++++++
 Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf           |  3 +++
 2 files changed, 18 insertions(+)

diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
index 72f8cfc..7544361 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
@@ -17,6 +17,21 @@
 
 ASM_FUNC(ArmPlatformPeiBootAction)
   mov   x29, xzr
+
+  MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress))
+  MOV32 (x3, FixedPcdGet32 (PcdFvSize))
+  add   x3, x3, x0
+
+  mrs   x1, ctr_el0
+  and   x1, x1, #0xf      // Dminline
+  mov   x2, #4
+  lsl   x1, x2, x1        // by-VA stride for D-cache maintenance
+
+0:dc    civac, x0
+  add   x0, x0, x1
+  cmp   x0, x3
+  b.lt  0b
+
   ret
 
 //UINTN
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
index 2e198c3..6966683 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
@@ -67,5 +67,8 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
   gArmTokenSpaceGuid.PcdArmPrimaryCore
 
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdFvSize
+
 [Ppis]
   gArmMpCoreInfoPpiGuid
-- 
1.8.3.1

Re: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:53PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> To prevent cache coherency issues when chainloading via U-Boot, clean
> and invalidate the FV image in the caches before re-enabling the MMU.

Is this only relevant for chainloading (which is not the expected
normal usage) or is it also important for warm-reset - for example for
capsule update (at least from within OS)?

If the former, I would prefer for this to be conditionalised, and not
included by default.

If the latter, please update the commit message.

/
    Leif

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++++++++++++
>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf           |  3 +++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> index 72f8cfc..7544361 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
> @@ -17,6 +17,21 @@
>  
>  ASM_FUNC(ArmPlatformPeiBootAction)
>    mov   x29, xzr
> +
> +  MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress))
> +  MOV32 (x3, FixedPcdGet32 (PcdFvSize))
> +  add   x3, x3, x0
> +
> +  mrs   x1, ctr_el0
> +  and   x1, x1, #0xf      // Dminline
> +  mov   x2, #4
> +  lsl   x1, x2, x1        // by-VA stride for D-cache maintenance
> +
> +0:dc    civac, x0
> +  add   x0, x0, x1
> +  cmp   x0, x3
> +  b.lt  0b
> +
>    ret
>  
>  //UINTN
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> index 2e198c3..6966683 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> @@ -67,5 +67,8 @@
>    gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>    gArmTokenSpaceGuid.PcdArmPrimaryCore
>  
> +  gArmTokenSpaceGuid.PcdFvBaseAddress
> +  gArmTokenSpaceGuid.PcdFvSize
> +
>  [Ppis]
>    gArmMpCoreInfoPpiGuid
> -- 
> 1.8.3.1
> 

Re: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot

[Marcin Wojtas]

2017-10-10 16:43 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Mon, Oct 09, 2017 at 07:00:53PM +0200, Marcin Wojtas wrote:
>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>
>> To prevent cache coherency issues when chainloading via U-Boot, clean
>> and invalidate the FV image in the caches before re-enabling the MMU.
>
> Is this only relevant for chainloading (which is not the expected
> normal usage) or is it also important for warm-reset - for example for
> capsule update (at least from within OS)?

Initially it was done for chainloading purpose - I don't use it
anymore, but just thought the patch itself is worth keeping. About
capsule update - I haven't tried it, it's been not the top priority
for me recently.

>
> If the former, I would prefer for this to be conditionalised, and not
> included by default.

How can we detect, that uefi is being chain-loaded?

>
> If the latter, please update the commit message.
>

I'm considering keeping this patch aside, until it may become
necessary for capsule update, as I cannot guarantee now it's needed at
all. What's your recommendation?

Best regards,
Marcin

> /
>     Leif
>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>>  Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++++++++++++
>>  Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf           |  3 +++
>>  2 files changed, 18 insertions(+)
>>
>> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
>> index 72f8cfc..7544361 100644
>> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
>> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S
>> @@ -17,6 +17,21 @@
>>
>>  ASM_FUNC(ArmPlatformPeiBootAction)
>>    mov   x29, xzr
>> +
>> +  MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress))
>> +  MOV32 (x3, FixedPcdGet32 (PcdFvSize))
>> +  add   x3, x3, x0
>> +
>> +  mrs   x1, ctr_el0
>> +  and   x1, x1, #0xf      // Dminline
>> +  mov   x2, #4
>> +  lsl   x1, x2, x1        // by-VA stride for D-cache maintenance
>> +
>> +0:dc    civac, x0
>> +  add   x0, x0, x1
>> +  cmp   x0, x3
>> +  b.lt  0b
>> +
>>    ret
>>
>>  //UINTN
>> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
>> index 2e198c3..6966683 100644
>> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
>> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
>> @@ -67,5 +67,8 @@
>>    gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>>    gArmTokenSpaceGuid.PcdArmPrimaryCore
>>
>> +  gArmTokenSpaceGuid.PcdFvBaseAddress
>> +  gArmTokenSpaceGuid.PcdFvSize
>> +
>>  [Ppis]
>>    gArmMpCoreInfoPpiGuid
>> --
>> 1.8.3.1
>>

Re: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot

[Leif Lindholm]

On Tue, Oct 10, 2017 at 04:50:04PM +0200, Marcin Wojtas wrote:
> 2017-10-10 16:43 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> > On Mon, Oct 09, 2017 at 07:00:53PM +0200, Marcin Wojtas wrote:
> >> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >>
> >> To prevent cache coherency issues when chainloading via U-Boot, clean
> >> and invalidate the FV image in the caches before re-enabling the MMU.
> >
> > Is this only relevant for chainloading (which is not the expected
> > normal usage) or is it also important for warm-reset - for example for
> > capsule update (at least from within OS)?
> 
> Initially it was done for chainloading purpose - I don't use it
> anymore, but just thought the patch itself is worth keeping. About
> capsule update - I haven't tried it, it's been not the top priority
> for me recently.
> 
> > If the former, I would prefer for this to be conditionalised, and not
> > included by default.
> 
> How can we detect, that uefi is being chain-loaded?

Oh, I meant compile time. Hence "not included by default".

It has been a useful debug feature, but I don't think anyone is
expecting to be routinely run either EDK2 on top of U-Boot or U-Boot
on top of EDK2 on this platform.

> > If the latter, please update the commit message.
> 
> I'm considering keeping this patch aside, until it may become
> necessary for capsule update, as I cannot guarantee now it's needed at
> all. What's your recommendation?

I'll wait to see what Ard has to say.
So yes, it may make sense to move it out of the series for now.

Regards,

Leif

Re: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot

[Ard Biesheuvel]

On 10 October 2017 at 16:29, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Tue, Oct 10, 2017 at 04:50:04PM +0200, Marcin Wojtas wrote:
>> 2017-10-10 16:43 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> > On Mon, Oct 09, 2017 at 07:00:53PM +0200, Marcin Wojtas wrote:
>> >> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >>
>> >> To prevent cache coherency issues when chainloading via U-Boot, clean
>> >> and invalidate the FV image in the caches before re-enabling the MMU.
>> >
>> > Is this only relevant for chainloading (which is not the expected
>> > normal usage) or is it also important for warm-reset - for example for
>> > capsule update (at least from within OS)?
>>
>> Initially it was done for chainloading purpose - I don't use it
>> anymore, but just thought the patch itself is worth keeping. About
>> capsule update - I haven't tried it, it's been not the top priority
>> for me recently.
>>
>> > If the former, I would prefer for this to be conditionalised, and not
>> > included by default.
>>
>> How can we detect, that uefi is being chain-loaded?
>
> Oh, I meant compile time. Hence "not included by default".
>
> It has been a useful debug feature, but I don't think anyone is
> expecting to be routinely run either EDK2 on top of U-Boot or U-Boot
> on top of EDK2 on this platform.
>
>> > If the latter, please update the commit message.
>>
>> I'm considering keeping this patch aside, until it may become
>> necessary for capsule update, as I cannot guarantee now it's needed at
>> all. What's your recommendation?
>
> I'll wait to see what Ard has to say.
> So yes, it may make sense to move it out of the series for now.
>

We don't need this patch, I think. I don't remember the details, but
the FV should simply be cleaned to the PoC before entering UEFI.

[platforms: PATCH 05/13] Marvell/Armada: Use 4k/64k aligned sections for DXE/DXE-rt modules

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Enable strict memory protection at boot time and under the OS, by using
4 KB section alignment for DXE_DRIVER, UEFI_DRIVER and UEFI_APPLICATION
modules, and 64 KB alignment for DXE_RUNTIME_DRIVER modules. Note that
the latter is mandated by the UEFI spec.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 433892e..1b4e713 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -486,6 +486,12 @@
       gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
   }
 
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x10000
+
 ################################################################################
 #
 # Defines - platform description macros
-- 
1.8.3.1

Re: [platforms: PATCH 05/13] Marvell/Armada: Use 4k/64k aligned sections for DXE/DXE-rt modules

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:54PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> Enable strict memory protection at boot time and under the OS, by using
> 4 KB section alignment for DXE_DRIVER, UEFI_DRIVER and UEFI_APPLICATION
> modules, and 64 KB alignment for DXE_RUNTIME_DRIVER modules. Note that
> the latter is mandated by the UEFI spec.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 433892e..1b4e713 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -486,6 +486,12 @@
>        gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
>    }
>  
> +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
> +  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> +  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x10000
> +
>  ################################################################################
>  #
>  # Defines - platform description macros
> -- 
> 1.8.3.1
> 

[platforms: PATCH 06/13] Marvell/Armada: Switch to generic BDS

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Switch from the Intel BDS to the generic BDS, which is preferred for
ARM platforms given that it is completely legacy free.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 19 ++++++++++++++++---
 Platform/Marvell/Armada/Armada70x0.fdf |  3 ++-
 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 1b4e713..e920461 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -126,8 +126,9 @@
 
   # BDS Libraries
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
-  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
-  PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
   CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
 
@@ -350,6 +351,12 @@
   # Shell.
   gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
 
+  # GUID of the generic BDS UiApp
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  # use the 'TTYTERM' terminal type for optimal compatibility with Linux terminal emulators
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
   # ARM Pcds
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
@@ -459,7 +466,13 @@
   MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
 
   # UEFI application (Shell Embedded Boot Loader)
   ShellPkg/Application/Shell/Shell.inf {
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index b3d1c60..999b968 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -175,7 +175,8 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
   INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
   INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
 
 
 # PEI phase firmware volume
-- 
1.8.3.1

Re: [platforms: PATCH 06/13] Marvell/Armada: Switch to generic BDS

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:55PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> Switch from the Intel BDS to the generic BDS, which is preferred for
> ARM platforms given that it is completely legacy free.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 19 ++++++++++++++++---
>  Platform/Marvell/Armada/Armada70x0.fdf |  3 ++-
>  2 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 1b4e713..e920461 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -126,8 +126,9 @@
>  
>    # BDS Libraries
>    CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> -  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
> -  PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
> +  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
>    CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
>    FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
>  
> @@ -350,6 +351,12 @@
>    # Shell.
>    gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
>  
> +  # GUID of the generic BDS UiApp
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> +
> +  # use the 'TTYTERM' terminal type for optimal compatibility with Linux terminal emulators
> +  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
>    # ARM Pcds
>    gArmTokenSpaceGuid.PcdSystemMemoryBase|0
>    gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
> @@ -459,7 +466,13 @@
>    MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
>    MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
>    MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> -  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  MdeModulePkg/Application/UiApp/UiApp.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> +  }
>  
>    # UEFI application (Shell Embedded Boot Loader)
>    ShellPkg/Application/Shell/Shell.inf {
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index b3d1c60..999b968 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -175,7 +175,8 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>    INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
>    INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
>    INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> -  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  INF MdeModulePkg/Application/UiApp/UiApp.inf
>  
>  
>  # PEI phase firmware volume
> -- 
> 1.8.3.1
> 

[platforms: PATCH 07/13] Marvell/Armada: Re-enable driver model diagnostics PCDs

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

For some reason, one of the early ARM platforms disabled all the
diagnostics related to the UEFI driver model, resulting in the
output of UEFI shell utilities such as 'devices' or 'drivers' to
become completely useless. Armada's shared .DSC include file
inherited this for no good reason, so let's revert it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index e920461..5071bd5 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -207,10 +207,6 @@
 ################################################################################
 
 [PcdsFeatureFlag.common]
-  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
-  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
 
   #
   # Control what commands are supported from the UI
-- 
1.8.3.1

Re: [platforms: PATCH 07/13] Marvell/Armada: Re-enable driver model diagnostics PCDs

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:56PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> For some reason, one of the early ARM platforms disabled all the
> diagnostics related to the UEFI driver model, resulting in the
> output of UEFI shell utilities such as 'devices' or 'drivers' to
> become completely useless. Armada's shared .DSC include file
> inherited this for no good reason, so let's revert it.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index e920461..5071bd5 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -207,10 +207,6 @@
>  ################################################################################
>  
>  [PcdsFeatureFlag.common]
> -  gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
> -  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> -  gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> -  gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
>  
>    #
>    # Control what commands are supported from the UI
> -- 
> 1.8.3.1
> 

[platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The GIC architecture mandates that the CPU interface, which consists
of 2 consecutive 4 KB frames, can be mapped using separate mappings.
Since this is problematic on 64 KB pages, the MMU-400 aliases each
frame 16 times, and the two consecutive frames can be found at offset
0xf000. This patch is intended to expose correct GICC alias via
MADT, once ACPI support is added.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 5071bd5..bd2336f 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -263,7 +263,14 @@
 
   # ARM Generic Interrupt Controller
   gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000
+
+  #
+  # NOTE: the GIC architecture mandates that the CPU interface, which consists
+  # of 2 consecutive 4 KB frames, can be mapped using separate mappings.
+  # Since this is problematic on 64 KB pages, the MMU-400 aliases each frame
+  # 16 times, and the two consecutive frames can be found at offset 0xf000
+  #
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000
 
   # ARM Architectural Timer Support
   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000
-- 
1.8.3.1

Re: [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:57PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> The GIC architecture mandates that the CPU interface, which consists
> of 2 consecutive 4 KB frames, can be mapped using separate mappings.
> Since this is problematic on 64 KB pages, the MMU-400 aliases each
> frame 16 times, and the two consecutive frames can be found at offset
> 0xf000. This patch is intended to expose correct GICC alias via
> MADT, once ACPI support is added.

I'm afraid I don't quite understand this message.

The change seems to be that the InterfaceBase moves from the first 4KB
alias inside a 64KB page to the last alias within the same page.
That seems valid, but I don't see how it resolves anything described
in this message?

/
    Leif

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 5071bd5..bd2336f 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -263,7 +263,14 @@
>  
>    # ARM Generic Interrupt Controller
>    gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000
> -  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000
> +
> +  #
> +  # NOTE: the GIC architecture mandates that the CPU interface, which consists
> +  # of 2 consecutive 4 KB frames, can be mapped using separate mappings.
> +  # Since this is problematic on 64 KB pages, the MMU-400 aliases each frame
> +  # 16 times, and the two consecutive frames can be found at offset 0xf000
> +  #
> +  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000
>  
>    # ARM Architectural Timer Support
>    gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000
> -- 
> 1.8.3.1
> 

Re: [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias

[Marcin Wojtas]

Hi Ard,

2017-10-10 16:53 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Mon, Oct 09, 2017 at 07:00:57PM +0200, Marcin Wojtas wrote:
>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>
>> The GIC architecture mandates that the CPU interface, which consists
>> of 2 consecutive 4 KB frames, can be mapped using separate mappings.
>> Since this is problematic on 64 KB pages, the MMU-400 aliases each
>> frame 16 times, and the two consecutive frames can be found at offset
>> 0xf000. This patch is intended to expose correct GICC alias via
>> MADT, once ACPI support is added.
>
> I'm afraid I don't quite understand this message.
>
> The change seems to be that the InterfaceBase moves from the first 4KB
> alias inside a 64KB page to the last alias within the same page.
> That seems valid, but I don't see how it resolves anything described
> in this message?
>

Can you recall what issue was fixed thanks to this patch?

Best regards,
Marcin

Re: [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias

[Ard Biesheuvel]

On 10 October 2017 at 15:56, Marcin Wojtas <mw@semihalf.com> wrote:
> Hi Ard,
>
> 2017-10-10 16:53 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
>> On Mon, Oct 09, 2017 at 07:00:57PM +0200, Marcin Wojtas wrote:
>>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>>
>>> The GIC architecture mandates that the CPU interface, which consists
>>> of 2 consecutive 4 KB frames, can be mapped using separate mappings.
>>> Since this is problematic on 64 KB pages, the MMU-400 aliases each
>>> frame 16 times, and the two consecutive frames can be found at offset
>>> 0xf000. This patch is intended to expose correct GICC alias via
>>> MADT, once ACPI support is added.
>>
>> I'm afraid I don't quite understand this message.
>>
>> The change seems to be that the InterfaceBase moves from the first 4KB
>> alias inside a 64KB page to the last alias within the same page.
>> That seems valid, but I don't see how it resolves anything described
>> in this message?
>>

Because now, GICC + 4 KB will point at the second frame, and so the
two frames appear adjacently, and precisely 4 KB apart. And at the
same time, they are still covered by distinct 64 KB pages so it even
works when running the OS with 64k pages.

Re: [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias

[Leif Lindholm]

On Tue, Oct 10, 2017 at 09:45:29PM +0100, Ard Biesheuvel wrote:
> On 10 October 2017 at 15:56, Marcin Wojtas <mw@semihalf.com> wrote:
> > Hi Ard,
> >
> > 2017-10-10 16:53 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> >> On Mon, Oct 09, 2017 at 07:00:57PM +0200, Marcin Wojtas wrote:
> >>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >>>
> >>> The GIC architecture mandates that the CPU interface, which consists
> >>> of 2 consecutive 4 KB frames, can be mapped using separate mappings.
> >>> Since this is problematic on 64 KB pages, the MMU-400 aliases each
> >>> frame 16 times, and the two consecutive frames can be found at offset
> >>> 0xf000. This patch is intended to expose correct GICC alias via
> >>> MADT, once ACPI support is added.
> >>
> >> I'm afraid I don't quite understand this message.
> >>
> >> The change seems to be that the InterfaceBase moves from the first 4KB
> >> alias inside a 64KB page to the last alias within the same page.
> >> That seems valid, but I don't see how it resolves anything described
> >> in this message?
> >>
> 
> Because now, GICC + 4 KB will point at the second frame, and so the
> two frames appear adjacently, and precisely 4 KB apart. And at the
> same time, they are still covered by distinct 64 KB pages so it even
> works when running the OS with 64k pages.

Right, I was thinking it might be something like that, but I didn't
get that from the patch - commit message _or_ comment.

Maybe add something like "Use the last alias from the first series of
aliases as the base address, so that the first frame from the second
series becomes directly adjacent, whilst remaining covered by a
separate 64kB page"?

/
    Leif

[platforms: PATCH 09/13] Marvell/Armada: Disable PerformanceLibrary

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Remove the gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask
setting so it reverts to its default of 0, and disables performance
profiling.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index bd2336f..b718c60 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -251,7 +251,6 @@
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
   gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
-  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
   gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
   gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
   gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
-- 
1.8.3.1

Re: [platforms: PATCH 09/13] Marvell/Armada: Disable PerformanceLibrary

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:58PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> Remove the gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask
> setting so it reverts to its default of 0, and disables performance
> profiling.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index bd2336f..b718c60 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -251,7 +251,6 @@
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
>    gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> -  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
>    gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
>    gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>    gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1
> -- 
> 1.8.3.1
> 

[platforms: PATCH 10/13] Marvell/Armada: Switch to unicore PrePi

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

There is no point in using the MPCore PrePi, given that only the primary
core will enter UEFI at EL2, and the secondaries will be held in EL3
until summoned by the OS. So use the unicore flavour instead.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 2 +-
 Platform/Marvell/Armada/Armada70x0.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index b718c60..5a5fde9 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -372,7 +372,7 @@
 [Components.common]
 
   # PEI Phase modules
-  ArmPlatformPkg/PrePi/PeiMPCore.inf
+  ArmPlatformPkg/PrePi/PeiUniCore.inf
 
   # DXE
   MdeModulePkg/Core/Dxe/DxeMain.inf {
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index 999b968..2c3efe0 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -199,7 +199,7 @@ READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
-  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
 
   FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
     SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
-- 
1.8.3.1

Re: [platforms: PATCH 10/13] Marvell/Armada: Switch to unicore PrePi

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:00:59PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> There is no point in using the MPCore PrePi, given that only the primary
> core will enter UEFI at EL2, and the secondaries will be held in EL3
> until summoned by the OS. So use the unicore flavour instead.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 2 +-
>  Platform/Marvell/Armada/Armada70x0.fdf | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index b718c60..5a5fde9 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -372,7 +372,7 @@
>  [Components.common]
>  
>    # PEI Phase modules
> -  ArmPlatformPkg/PrePi/PeiMPCore.inf
> +  ArmPlatformPkg/PrePi/PeiUniCore.inf
>  
>    # DXE
>    MdeModulePkg/Core/Dxe/DxeMain.inf {
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index 999b968..2c3efe0 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -199,7 +199,7 @@ READ_STATUS        = TRUE
>  READ_LOCK_CAP      = TRUE
>  READ_LOCK_STATUS   = TRUE
>  
> -  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
> +  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
>  
>    FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
>      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> -- 
> 1.8.3.1
> 

[platforms: PATCH 11/13] Marvell/Armada: Remove outdated SEC alignment override

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

The FDFs no longer require explicit alignment for sections containing
aligned objects, so change it to 'Auto' and FIXED (which allows some
padding to be removed), and remove some other cruft while at it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada70x0.fdf | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index 2c3efe0..15ae52b 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -235,16 +235,9 @@ READ_LOCK_STATUS   = TRUE
 #
 ############################################################################
 
-[Rule.ARM.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
-  }
-
-# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
-# It is the reason 4K is used instead of 2K for the module alignment.
 [Rule.AARCH64.SEC]
-  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
-    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+    TE  TE    Align = Auto                $(INF_OUTPUT)/$(MODULE_NAME).efi
   }
 
 [Rule.Common.PEI_CORE]
-- 
1.8.3.1

Re: [platforms: PATCH 11/13] Marvell/Armada: Remove outdated SEC alignment override

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:01:00PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> The FDFs no longer require explicit alignment for sections containing
> aligned objects, so change it to 'Auto' and FIXED (which allows some
> padding to be removed), and remove some other cruft while at it.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Platform/Marvell/Armada/Armada70x0.fdf | 11 ++---------
>  1 file changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index 2c3efe0..15ae52b 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -235,16 +235,9 @@ READ_LOCK_STATUS   = TRUE
>  #
>  ############################################################################
>  
> -[Rule.ARM.SEC]
> -  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> -    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
> -  }
> -
> -# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
> -# It is the reason 4K is used instead of 2K for the module alignment.
>  [Rule.AARCH64.SEC]
> -  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> -    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
> +    TE  TE    Align = Auto                $(INF_OUTPUT)/$(MODULE_NAME).efi

This does appear to arbitrarily increase indentation of the last entry
on the line by 2, shifting it out of alignment with later entries in
the file?

/
    Leif

>    }
>  
>  [Rule.Common.PEI_CORE]
> -- 
> 1.8.3.1
> 

Re: [platforms: PATCH 11/13] Marvell/Armada: Remove outdated SEC alignment override

[Marcin Wojtas]

2017-10-10 16:58 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Mon, Oct 09, 2017 at 07:01:00PM +0200, Marcin Wojtas wrote:
>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>
>> The FDFs no longer require explicit alignment for sections containing
>> aligned objects, so change it to 'Auto' and FIXED (which allows some
>> padding to be removed), and remove some other cruft while at it.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>>  Platform/Marvell/Armada/Armada70x0.fdf | 11 ++---------
>>  1 file changed, 2 insertions(+), 9 deletions(-)
>>
>> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
>> index 2c3efe0..15ae52b 100644
>> --- a/Platform/Marvell/Armada/Armada70x0.fdf
>> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
>> @@ -235,16 +235,9 @@ READ_LOCK_STATUS   = TRUE
>>  #
>>  ############################################################################
>>
>> -[Rule.ARM.SEC]
>> -  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
>> -    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
>> -  }
>> -
>> -# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
>> -# It is the reason 4K is used instead of 2K for the module alignment.
>>  [Rule.AARCH64.SEC]
>> -  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
>> -    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
>> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
>> +    TE  TE    Align = Auto                $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> This does appear to arbitrarily increase indentation of the last entry
> on the line by 2, shifting it out of alignment with later entries in
> the file?
>

I'll correct indentation in v2.

Thanks,
Marcin

> /
>     Leif
>
>>    }
>>
>>  [Rule.Common.PEI_CORE]
>> --
>> 1.8.3.1
>>

[platforms: PATCH 12/13] Marvell/Armada: Add the UefiPxeBcDxe driver

[Marcin Wojtas]

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

This driver allows automatic booting via the network.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Armada/Armada.dsc.inc | 1 +
 Platform/Marvell/Armada/Armada70x0.fdf | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 5a5fde9..1aa485c 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -412,6 +412,7 @@
   MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
   MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
   MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
   Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
   Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
   Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index 15ae52b..bf54c6e 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -125,6 +125,7 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
   INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
   INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
   INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
   INF Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
   INF Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
   INF Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
-- 
1.8.3.1

Re: [platforms: PATCH 12/13] Marvell/Armada: Add the UefiPxeBcDxe driver

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:01:01PM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> 
> This driver allows automatic booting via the network.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/Marvell/Armada/Armada.dsc.inc | 1 +
>  Platform/Marvell/Armada/Armada70x0.fdf | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 5a5fde9..1aa485c 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -412,6 +412,7 @@
>    MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
>    MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
>    MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
>    Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
>    Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
>    Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index 15ae52b..bf54c6e 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -125,6 +125,7 @@ FvNameGuid         = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
>    INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
>    INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
>    INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
>    INF Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
>    INF Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf
>    INF Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
> -- 
> 1.8.3.1
> 

[platforms: PATCH 13/13] Marvell/Documentation: Follow EDK2 coding style in the PortingGuide

[Marcin Wojtas]

This patch removes tabs and wrong line endings in the file, maiking
it acceptable to the PatchCheck.py script.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Documentation/PortingGuide.txt | 800 ++++++++++----------
 1 file changed, 400 insertions(+), 400 deletions(-)

diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt
index f0da515..66ec918 100644
--- a/Silicon/Marvell/Documentation/PortingGuide.txt
+++ b/Silicon/Marvell/Documentation/PortingGuide.txt
@@ -1,400 +1,400 @@
-UEFI Porting Guide
-==================
-
-This document provides instructions for adding support for new Marvell Armada
-board. For the sake of simplicity new Marvell board will be called "new_board".
-
-1. Create configuration files for new target
-	1.1 Create FDF file for new board
-
-	 - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf to
-	   edk2-platforms/Platform/Marvell/Armada/new_board.fdf
-	 - Change the first no-comment line:
-	   [FD.Armada70x0_EFI] to [FD.{new_board}_EFI]
-
-	1.2 Create DSC file for new board
-
-	 - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada directory
-	 - Insert following [Defines] section to new_board.dsc:
-
-			[Defines]
-			  PLATFORM_NAME                  = {new_board}
-			  PLATFORM_GUID                  = {newly_generated_GUID}
-			  PLATFORM_VERSION               = 0.1
-			  DSC_SPECIFICATION              = 0x00010019
-			  OUTPUT_DIRECTORY               = {output_directory}
-			  SUPPORTED_ARCHITECTURES        = AARCH64
-			  BUILD_TARGETS                  = DEBUG|RELEASE
-			  SKUID_IDENTIFIER               = DEFAULT
-			  FLASH_DEFINITION               = {path_to_fdf_file}
-
-	 - Add "!include Armada.dsc.inc" entry to new_board.dsc
-
-2. Driver support
- - According to content of files from
-   edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt
-   insert PCD entries into new_board.dsc for every needed interface (as listed below).
-
-3. Compilation
- - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change
-   {platform} to new_board in order to point build system to newly created DSC file.
-
-4. Output file
- - Output files (and among others FD file, which may be used by ATF) are
-   generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
-
-
-COMPHY configuration
-====================
-In order to configure ComPhy library, following PCDs are available:
-
-  - gMarvellTokenSpaceGuid.PcdComPhyDevices
-
-This array indicates, which ones of the ComPhy chips defined in
-MVHW_COMPHY_DESC template will be configured.
-
-Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
-important, but configuration will be set for first PcdComPhyChipCount chips).
-
-Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
-settings for this chip. Their format is array of up to 10 values reflecting
-defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
-
-  OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
-
-  - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
-	(Array of types - currently supported are:
-
-	CP_UNCONNECTED                      0x0
-	CP_PCIE0                            0x1
-	CP_PCIE1                            0x2
-	CP_PCIE2                            0x3
-	CP_PCIE3                            0x4
-	CP_SATA0                            0x5
-	CP_SATA1                            0x6
-	CP_SATA2                            0x7
-	CP_SATA3                            0x8
-	CP_SGMII0                           0x9
-	CP_SGMII1                           0xA
-	CP_SGMII2                           0xB
-	CP_SGMII3                           0xC
-	CP_QSGMII                           0xD
-	CP_USB3_HOST0                       0xE
-	CP_USB3_HOST1                       0xF
-	CP_USB3_DEVICE                      0x10
-	CP_XAUI0                            0x11
-	CP_XAUI1                            0x12
-	CP_XAUI2                            0x13
-	CP_XAUI3                            0x14
-	CP_RXAUI0                           0x15
-	CP_RXAUI1                           0x16
-	CP_SFI                              0x17 )
-
-  - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
-	(Array of speeds - currently supported are:
-
-	CP_1_25G                            0x1
-	CP_1_5G                             0x2
-	CP_2_5G                             0x3
-	CP_3G                               0x4
-	CP_3_125G                           0x5
-	CP_5G                               0x6
-	CP_5_15625G                         0x7
-	CP_6G                               0x8
-	CP_6_25G                            0x9
-	CP_10_3125G                         0xA )
-
-  - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
-	(Array of lane inversion types - currently supported are:
-
-	CP_NO_INVERT                        0x0
-	CP_TXD_INVERT                       0x1
-	CP_RXD_INVERT                       0x2
-	CP_ALL_INVERT                       0x3 )
-
-Example
--------
-
-		  #ComPhy
-		  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
-		  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
-		  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
-
-
-PHY Driver configuration
-========================
-MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
-Currently only 1518 series PHYs are supported. Following PCDs are required:
-
-  - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
-	(boolean - if true, driver waits for autonegotiation on startup)
-  - gMarvellTokenSpaceGuid.PcdPhyDeviceIds
-	(list of values corresponding to MV_PHY_DEVICE_ID enum)
-  - gMarvellTokenSpaceGuid.PcdPhySmiAddresses
-	(addresses of PHY devices)
-  - gMarvellTokenSpaceGuid.PcdPhy2MdioController
-	(Array specifying, which Mdio controller the PHY is attached to)
-
-
-MV_PHY_DEVICE_ID:
-
-		typedef enum {
-			0    MV_PHY_DEVICE_1512,
-		} MV_PHY_DEVICE_ID;
-
-It should be extended when adding support for other PHY models.
-
-Disable autonegotiation:
-
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
-
-assuming, that PHY models are 1512:
-
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
-
-
-MDIO configuration
-==================
-MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
-EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
-
-  - gMarvellTokenSpaceGuid.PcdMdioControllers
-	(Array with used controllers
-	 Set to 0x1 for enabled, 0x0 for disabled)
-
-
-I2C configuration
-=================
-In order to enable driver on a new platform, following steps need to be taken:
- - add following line to .dsc file:
-   edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
- - add following line to .fdf file:
-   INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
- - add PCDs with relevant values to .dsc file:
-	- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
-		(addresses of I2C slave devices on bus)
-	- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
-		(buses to which accoring slaves are attached)
-	- gMarvellTokenSpaceGuid.PcdI2cBusCount|2
-		(number of SoC's I2C buses)
-	- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
-		(array with used controllers)
-	- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
-		(I2C host controller clock frequency)
-	- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
-		(baud rate used in I2C transmission)
-
-
-PciEmulation configuration
-==========================
-Installation of various NonDiscoverable devices via PciEmulation driver is performed
-via set of PCDs. Following are available:
-
-  - gMarvellTokenSpaceGuid.PcdPciEXhci
-	(Indicates, which Xhci devices are used)
-
-  - gMarvellTokenSpaceGuid.PcdPciEAhci
-	(Indicates, which Ahci devices are used)
-
-  - gMarvellTokenSpaceGuid.PcdPciESdhci
-	(Indicates, which Sdhci devices are used)
-
-All above PCD's correspond to hardware description in a dedicated structure:
-
-STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
-
-in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device
-count, base addresses, register region size and DMA-coherency type.
-
-Example
--------
-
-Assuming we want to enable second XHCI port and one SDHCI port on Armada
-70x0 board, following needs to be declared:
-
-		gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
-		gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
-
-
-SATA configuration
-==================
-There is one additional PCD for AHCI:
-
-  - gMarvellTokenSpaceGuid.PcdSataBaseAddress
-	(Base address of SATA controller register space - used in SATA ComPhy init
-	 sequence)
-
-
-Pp2Dxe configuration
-====================
-Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
-are required to operate:
-
-  - gMarvellTokenSpaceGuid.PcdPp2Controllers
-	(Array with used controllers
-	 Set to 0x1 for enabled, 0x0 for disabled)
-
-  - gMarvellTokenSpaceGuid.PcdPp2Port2Controller
-	(Array specifying, to which controller the port belongs to)
-
-  - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
-	(Indicates speed of the network interface:
-
-	PHY_RGMII                        0x0
-	PHY_RGMII_ID                     0x1
-	PHY_RGMII_TXID                   0x2
-	PHY_RGMII_RXID                   0x3
-	PHY_SGMII                        0x4
-	PHY_RTBI                         0x5
-	PHY_XAUI                         0x6
-	PHY_RXAUI                        0x7
-	PHY_SFI                          0x8 )
-
-  - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
-	(Array specifying, to which PHY from
-	 gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
-	 e.g. in 10G SFI in-band link detection, 0xFF value must
-	 be specified)
-
-  - gMarvellTokenSpaceGuid.PcdPp2PortIds
-	(Identificators of PP2 ports)
-
-  - gMarvellTokenSpaceGuid.PcdPp2GopIndexes
-	(Indexes used in GOP operation)
-
-  - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
-	(Set to 0x1 for always-up interface, 0x0 otherwise)
-
-  - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
-	(Indicates speed of the network interface:
-
-	PHY_SPEED_10                     0x1
-	PHY_SPEED_100                    0x2
-	PHY_SPEED_1000                   0x3
-	PHY_SPEED_2500                   0x4
-	PHY_SPEED_10000                  0x5 )
-
-
-UTMI PHY configuration
-======================
-In order to configure UTMI, following PCDs are available:
-
-  - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
-	(Array with used controllers
-	 Set to 0x1 for enabled, 0x0 for disabled)
-
-  - gMarvellTokenSpaceGuid.PcdUtmiPortType
-	(Indicates type of the connected USB port:
-
-	UTMI_USB_HOST0                     0x0
-	UTMI_USB_HOST1                     0x1
-	UTMI_USB_DEVICE0                   0x2 )
-
-Example
--------
-
-		# UtmiPhy
-		  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
-		  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
-
-
-SPI driver configuration
-========================
-Following PCDs are available for configuration of spi driver:
-
-  - gMarvellTokenSpaceGuid.PcdSpiClockFrequency
-	(Frequency (in Hz) of SPI clock)
-
-  - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
-	(Max SCLK line frequency (in Hz) (max transfer frequency) )
-
-SpiFlash configuration
-======================
-Folowing PCDs for spi flash driver configuration must be set properly:
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
-	(Size of SPI flash address in bytes (3 or 4) )
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
-	(Size of minimal erase block in bytes)
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
-	(Size of SPI flash page)
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize
-	(Size of SPI flash sector, 65536 bytes by default)
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashId
-	(Id of SPI flash)
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
-	(Spi flash polling flag)
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashMode
-	(Default SCLK mode (see SPI_MODE enum in file
-	 edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
-
-  - gMarvellTokenSpaceGuid.PcdSpiFlashCs
-	(Chip select used for communication with the Flash)
-
-MPP configuration
-=================
-Multi-Purpose Ports (MPP) are configurable through platform PCDs.
-In order to set desired pin multiplexing, .dsc file needs to be modified.
-(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer to
-Documentation/Build.txt for currently supported {platftorm_name} )
-Following PCDs are available:
-
-  - gMarvellTokenSpaceGuid.PcdMppChipCount
-	(Indicates how many different chips are placed on board. So far up to 4 chips
-	 are supported)
-
-Every MPP PCD has <Num> part where
- <Num> stands for chip ID (order is not important, but configuration will be
- set for first PcdMppChipCount chips).
-
-Below is example for the first chip (Chip0).
-
-  - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
-	(Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
-
-  - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
-	(This is base address for MPP configuration register)
-
-  - gMarvellTokenSpaceGuid.PcdChip0MppPinCount
-	(Defines how many MPP pins are available)
-
-  - gMarvellTokenSpaceGuid.PcdChip0MppSel0
-  - gMarvellTokenSpaceGuid.PcdChip0MppSel1
-  - gMarvellTokenSpaceGuid.PcdChip0MppSel2
-	(This registers defines functions of 10 pins in ascending order)
-
-Examples
---------
-
-		# APN806-A0 MPP SET
-		 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
-		 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
-		 gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
-		 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
-		 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
-
-Set pin 6 and 7 to 0xa function:
-		 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
-
-
-MarvellResetSystemLib configuration
-===================================
-This simple library allows to mask given bits in given reg at UEFI 'reset'
-command call. These variables are configurable through PCDs:
-
-  - gMarvellTokenSpaceGuid.PcdResetRegAddress
-  - gMarvellTokenSpaceGuid.PcdResetRegMask
-
-
-Ramdisk configuration
-=====================
-There is one PCD available for Ramdisk configuration
-
-  - gMarvellTokenSpaceGuid.PcdRamDiskSize
-	(Defines size of Ramdisk)
+UEFI Porting Guide
+==================
+
+This document provides instructions for adding support for new Marvell Armada
+board. For the sake of simplicity new Marvell board will be called "new_board".
+
+1. Create configuration files for new target
+        1.1 Create FDF file for new board
+
+         - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf to
+           edk2-platforms/Platform/Marvell/Armada/new_board.fdf
+         - Change the first no-comment line:
+           [FD.Armada70x0_EFI] to [FD.{new_board}_EFI]
+
+        1.2 Create DSC file for new board
+
+         - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada directory
+         - Insert following [Defines] section to new_board.dsc:
+
+                        [Defines]
+                          PLATFORM_NAME                  = {new_board}
+                          PLATFORM_GUID                  = {newly_generated_GUID}
+                          PLATFORM_VERSION               = 0.1
+                          DSC_SPECIFICATION              = 0x00010019
+                          OUTPUT_DIRECTORY               = {output_directory}
+                          SUPPORTED_ARCHITECTURES        = AARCH64
+                          BUILD_TARGETS                  = DEBUG|RELEASE
+                          SKUID_IDENTIFIER               = DEFAULT
+                          FLASH_DEFINITION               = {path_to_fdf_file}
+
+         - Add "!include Armada.dsc.inc" entry to new_board.dsc
+
+2. Driver support
+ - According to content of files from
+   edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt
+   insert PCD entries into new_board.dsc for every needed interface (as listed below).
+
+3. Compilation
+ - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change
+   {platform} to new_board in order to point build system to newly created DSC file.
+
+4. Output file
+ - Output files (and among others FD file, which may be used by ATF) are
+   generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
+
+
+COMPHY configuration
+====================
+In order to configure ComPhy library, following PCDs are available:
+
+  - gMarvellTokenSpaceGuid.PcdComPhyDevices
+
+This array indicates, which ones of the ComPhy chips defined in
+MVHW_COMPHY_DESC template will be configured.
+
+Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
+important, but configuration will be set for first PcdComPhyChipCount chips).
+
+Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
+settings for this chip. Their format is array of up to 10 values reflecting
+defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
+
+  OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
+
+  - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+        (Array of types - currently supported are:
+
+        CP_UNCONNECTED                      0x0
+        CP_PCIE0                            0x1
+        CP_PCIE1                            0x2
+        CP_PCIE2                            0x3
+        CP_PCIE3                            0x4
+        CP_SATA0                            0x5
+        CP_SATA1                            0x6
+        CP_SATA2                            0x7
+        CP_SATA3                            0x8
+        CP_SGMII0                           0x9
+        CP_SGMII1                           0xA
+        CP_SGMII2                           0xB
+        CP_SGMII3                           0xC
+        CP_QSGMII                           0xD
+        CP_USB3_HOST0                       0xE
+        CP_USB3_HOST1                       0xF
+        CP_USB3_DEVICE                      0x10
+        CP_XAUI0                            0x11
+        CP_XAUI1                            0x12
+        CP_XAUI2                            0x13
+        CP_XAUI3                            0x14
+        CP_RXAUI0                           0x15
+        CP_RXAUI1                           0x16
+        CP_SFI                              0x17 )
+
+  - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+        (Array of speeds - currently supported are:
+
+        CP_1_25G                            0x1
+        CP_1_5G                             0x2
+        CP_2_5G                             0x3
+        CP_3G                               0x4
+        CP_3_125G                           0x5
+        CP_5G                               0x6
+        CP_5_15625G                         0x7
+        CP_6G                               0x8
+        CP_6_25G                            0x9
+        CP_10_3125G                         0xA )
+
+  - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+        (Array of lane inversion types - currently supported are:
+
+        CP_NO_INVERT                        0x0
+        CP_TXD_INVERT                       0x1
+        CP_RXD_INVERT                       0x2
+        CP_ALL_INVERT                       0x3 )
+
+Example
+-------
+
+                  #ComPhy
+                  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+                  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+                  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+
+
+PHY Driver configuration
+========================
+MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
+Currently only 1518 series PHYs are supported. Following PCDs are required:
+
+  - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+        (boolean - if true, driver waits for autonegotiation on startup)
+  - gMarvellTokenSpaceGuid.PcdPhyDeviceIds
+        (list of values corresponding to MV_PHY_DEVICE_ID enum)
+  - gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+        (addresses of PHY devices)
+  - gMarvellTokenSpaceGuid.PcdPhy2MdioController
+        (Array specifying, which Mdio controller the PHY is attached to)
+
+
+MV_PHY_DEVICE_ID:
+
+                typedef enum {
+                        0    MV_PHY_DEVICE_1512,
+                } MV_PHY_DEVICE_ID;
+
+It should be extended when adding support for other PHY models.
+
+Disable autonegotiation:
+
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+assuming, that PHY models are 1512:
+
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+
+
+MDIO configuration
+==================
+MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
+EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
+
+  - gMarvellTokenSpaceGuid.PcdMdioControllers
+        (Array with used controllers
+         Set to 0x1 for enabled, 0x0 for disabled)
+
+
+I2C configuration
+=================
+In order to enable driver on a new platform, following steps need to be taken:
+ - add following line to .dsc file:
+   edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add following line to .fdf file:
+   INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add PCDs with relevant values to .dsc file:
+        - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
+                (addresses of I2C slave devices on bus)
+        - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+                (buses to which accoring slaves are attached)
+        - gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+                (number of SoC's I2C buses)
+        - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
+                (array with used controllers)
+        - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
+                (I2C host controller clock frequency)
+        - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+                (baud rate used in I2C transmission)
+
+
+PciEmulation configuration
+==========================
+Installation of various NonDiscoverable devices via PciEmulation driver is performed
+via set of PCDs. Following are available:
+
+  - gMarvellTokenSpaceGuid.PcdPciEXhci
+        (Indicates, which Xhci devices are used)
+
+  - gMarvellTokenSpaceGuid.PcdPciEAhci
+        (Indicates, which Ahci devices are used)
+
+  - gMarvellTokenSpaceGuid.PcdPciESdhci
+        (Indicates, which Sdhci devices are used)
+
+All above PCD's correspond to hardware description in a dedicated structure:
+
+STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
+
+in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device
+count, base addresses, register region size and DMA-coherency type.
+
+Example
+-------
+
+Assuming we want to enable second XHCI port and one SDHCI port on Armada
+70x0 board, following needs to be declared:
+
+                gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
+                gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
+
+
+SATA configuration
+==================
+There is one additional PCD for AHCI:
+
+  - gMarvellTokenSpaceGuid.PcdSataBaseAddress
+        (Base address of SATA controller register space - used in SATA ComPhy init
+         sequence)
+
+
+Pp2Dxe configuration
+====================
+Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
+are required to operate:
+
+  - gMarvellTokenSpaceGuid.PcdPp2Controllers
+        (Array with used controllers
+         Set to 0x1 for enabled, 0x0 for disabled)
+
+  - gMarvellTokenSpaceGuid.PcdPp2Port2Controller
+        (Array specifying, to which controller the port belongs to)
+
+  - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
+        (Indicates speed of the network interface:
+
+        PHY_RGMII                        0x0
+        PHY_RGMII_ID                     0x1
+        PHY_RGMII_TXID                   0x2
+        PHY_RGMII_RXID                   0x3
+        PHY_SGMII                        0x4
+        PHY_RTBI                         0x5
+        PHY_XAUI                         0x6
+        PHY_RXAUI                        0x7
+        PHY_SFI                          0x8 )
+
+  - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
+        (Array specifying, to which PHY from
+         gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
+         e.g. in 10G SFI in-band link detection, 0xFF value must
+         be specified)
+
+  - gMarvellTokenSpaceGuid.PcdPp2PortIds
+        (Identificators of PP2 ports)
+
+  - gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+        (Indexes used in GOP operation)
+
+  - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+        (Set to 0x1 for always-up interface, 0x0 otherwise)
+
+  - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+        (Indicates speed of the network interface:
+
+        PHY_SPEED_10                     0x1
+        PHY_SPEED_100                    0x2
+        PHY_SPEED_1000                   0x3
+        PHY_SPEED_2500                   0x4
+        PHY_SPEED_10000                  0x5 )
+
+
+UTMI PHY configuration
+======================
+In order to configure UTMI, following PCDs are available:
+
+  - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
+        (Array with used controllers
+         Set to 0x1 for enabled, 0x0 for disabled)
+
+  - gMarvellTokenSpaceGuid.PcdUtmiPortType
+        (Indicates type of the connected USB port:
+
+        UTMI_USB_HOST0                     0x0
+        UTMI_USB_HOST1                     0x1
+        UTMI_USB_DEVICE0                   0x2 )
+
+Example
+-------
+
+                # UtmiPhy
+                  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+                  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+
+SPI driver configuration
+========================
+Following PCDs are available for configuration of spi driver:
+
+  - gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+        (Frequency (in Hz) of SPI clock)
+
+  - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+        (Max SCLK line frequency (in Hz) (max transfer frequency) )
+
+SpiFlash configuration
+======================
+Folowing PCDs for spi flash driver configuration must be set properly:
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
+        (Size of SPI flash address in bytes (3 or 4) )
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
+        (Size of minimal erase block in bytes)
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
+        (Size of SPI flash page)
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize
+        (Size of SPI flash sector, 65536 bytes by default)
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashId
+        (Id of SPI flash)
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
+        (Spi flash polling flag)
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashMode
+        (Default SCLK mode (see SPI_MODE enum in file
+         edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
+
+  - gMarvellTokenSpaceGuid.PcdSpiFlashCs
+        (Chip select used for communication with the Flash)
+
+MPP configuration
+=================
+Multi-Purpose Ports (MPP) are configurable through platform PCDs.
+In order to set desired pin multiplexing, .dsc file needs to be modified.
+(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer to
+Documentation/Build.txt for currently supported {platftorm_name} )
+Following PCDs are available:
+
+  - gMarvellTokenSpaceGuid.PcdMppChipCount
+        (Indicates how many different chips are placed on board. So far up to 4 chips
+         are supported)
+
+Every MPP PCD has <Num> part where
+ <Num> stands for chip ID (order is not important, but configuration will be
+ set for first PcdMppChipCount chips).
+
+Below is example for the first chip (Chip0).
+
+  - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+        (Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
+
+  - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+        (This is base address for MPP configuration register)
+
+  - gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+        (Defines how many MPP pins are available)
+
+  - gMarvellTokenSpaceGuid.PcdChip0MppSel0
+  - gMarvellTokenSpaceGuid.PcdChip0MppSel1
+  - gMarvellTokenSpaceGuid.PcdChip0MppSel2
+        (This registers defines functions of 10 pins in ascending order)
+
+Examples
+--------
+
+                # APN806-A0 MPP SET
+                 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+                 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+                 gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
+                 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
+                 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+Set pin 6 and 7 to 0xa function:
+                 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
+
+
+MarvellResetSystemLib configuration
+===================================
+This simple library allows to mask given bits in given reg at UEFI 'reset'
+command call. These variables are configurable through PCDs:
+
+  - gMarvellTokenSpaceGuid.PcdResetRegAddress
+  - gMarvellTokenSpaceGuid.PcdResetRegMask
+
+
+Ramdisk configuration
+=====================
+There is one PCD available for Ramdisk configuration
+
+  - gMarvellTokenSpaceGuid.PcdRamDiskSize
+        (Defines size of Ramdisk)
-- 
1.8.3.1

Re: [platforms: PATCH 13/13] Marvell/Documentation: Follow EDK2 coding style in the PortingGuide

[Leif Lindholm]

On Mon, Oct 09, 2017 at 07:01:02PM +0200, Marcin Wojtas wrote:
> This patch removes tabs and wrong line endings in the file, maiking
> it acceptable to the PatchCheck.py script.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Much obliged :)

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Silicon/Marvell/Documentation/PortingGuide.txt | 800 ++++++++++----------
>  1 file changed, 400 insertions(+), 400 deletions(-)
> 
> diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt
> index f0da515..66ec918 100644
> --- a/Silicon/Marvell/Documentation/PortingGuide.txt
> +++ b/Silicon/Marvell/Documentation/PortingGuide.txt
> @@ -1,400 +1,400 @@
> -UEFI Porting Guide
> -==================
> -
> -This document provides instructions for adding support for new Marvell Armada
> -board. For the sake of simplicity new Marvell board will be called "new_board".
> -
> -1. Create configuration files for new target
> -	1.1 Create FDF file for new board
> -
> -	 - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf to
> -	   edk2-platforms/Platform/Marvell/Armada/new_board.fdf
> -	 - Change the first no-comment line:
> -	   [FD.Armada70x0_EFI] to [FD.{new_board}_EFI]
> -
> -	1.2 Create DSC file for new board
> -
> -	 - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada directory
> -	 - Insert following [Defines] section to new_board.dsc:
> -
> -			[Defines]
> -			  PLATFORM_NAME                  = {new_board}
> -			  PLATFORM_GUID                  = {newly_generated_GUID}
> -			  PLATFORM_VERSION               = 0.1
> -			  DSC_SPECIFICATION              = 0x00010019
> -			  OUTPUT_DIRECTORY               = {output_directory}
> -			  SUPPORTED_ARCHITECTURES        = AARCH64
> -			  BUILD_TARGETS                  = DEBUG|RELEASE
> -			  SKUID_IDENTIFIER               = DEFAULT
> -			  FLASH_DEFINITION               = {path_to_fdf_file}
> -
> -	 - Add "!include Armada.dsc.inc" entry to new_board.dsc
> -
> -2. Driver support
> - - According to content of files from
> -   edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt
> -   insert PCD entries into new_board.dsc for every needed interface (as listed below).
> -
> -3. Compilation
> - - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change
> -   {platform} to new_board in order to point build system to newly created DSC file.
> -
> -4. Output file
> - - Output files (and among others FD file, which may be used by ATF) are
> -   generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
> -
> -
> -COMPHY configuration
> -====================
> -In order to configure ComPhy library, following PCDs are available:
> -
> -  - gMarvellTokenSpaceGuid.PcdComPhyDevices
> -
> -This array indicates, which ones of the ComPhy chips defined in
> -MVHW_COMPHY_DESC template will be configured.
> -
> -Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
> -important, but configuration will be set for first PcdComPhyChipCount chips).
> -
> -Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
> -settings for this chip. Their format is array of up to 10 values reflecting
> -defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
> -
> -  OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
> -	(Array of types - currently supported are:
> -
> -	CP_UNCONNECTED                      0x0
> -	CP_PCIE0                            0x1
> -	CP_PCIE1                            0x2
> -	CP_PCIE2                            0x3
> -	CP_PCIE3                            0x4
> -	CP_SATA0                            0x5
> -	CP_SATA1                            0x6
> -	CP_SATA2                            0x7
> -	CP_SATA3                            0x8
> -	CP_SGMII0                           0x9
> -	CP_SGMII1                           0xA
> -	CP_SGMII2                           0xB
> -	CP_SGMII3                           0xC
> -	CP_QSGMII                           0xD
> -	CP_USB3_HOST0                       0xE
> -	CP_USB3_HOST1                       0xF
> -	CP_USB3_DEVICE                      0x10
> -	CP_XAUI0                            0x11
> -	CP_XAUI1                            0x12
> -	CP_XAUI2                            0x13
> -	CP_XAUI3                            0x14
> -	CP_RXAUI0                           0x15
> -	CP_RXAUI1                           0x16
> -	CP_SFI                              0x17 )
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
> -	(Array of speeds - currently supported are:
> -
> -	CP_1_25G                            0x1
> -	CP_1_5G                             0x2
> -	CP_2_5G                             0x3
> -	CP_3G                               0x4
> -	CP_3_125G                           0x5
> -	CP_5G                               0x6
> -	CP_5_15625G                         0x7
> -	CP_6G                               0x8
> -	CP_6_25G                            0x9
> -	CP_10_3125G                         0xA )
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
> -	(Array of lane inversion types - currently supported are:
> -
> -	CP_NO_INVERT                        0x0
> -	CP_TXD_INVERT                       0x1
> -	CP_RXD_INVERT                       0x2
> -	CP_ALL_INVERT                       0x3 )
> -
> -Example
> --------
> -
> -		  #ComPhy
> -		  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
> -		  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
> -		  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
> -
> -
> -PHY Driver configuration
> -========================
> -MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
> -Currently only 1518 series PHYs are supported. Following PCDs are required:
> -
> -  - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
> -	(boolean - if true, driver waits for autonegotiation on startup)
> -  - gMarvellTokenSpaceGuid.PcdPhyDeviceIds
> -	(list of values corresponding to MV_PHY_DEVICE_ID enum)
> -  - gMarvellTokenSpaceGuid.PcdPhySmiAddresses
> -	(addresses of PHY devices)
> -  - gMarvellTokenSpaceGuid.PcdPhy2MdioController
> -	(Array specifying, which Mdio controller the PHY is attached to)
> -
> -
> -MV_PHY_DEVICE_ID:
> -
> -		typedef enum {
> -			0    MV_PHY_DEVICE_1512,
> -		} MV_PHY_DEVICE_ID;
> -
> -It should be extended when adding support for other PHY models.
> -
> -Disable autonegotiation:
> -
> - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> -
> -assuming, that PHY models are 1512:
> -
> - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
> -
> -
> -MDIO configuration
> -==================
> -MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
> -EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
> -
> -  - gMarvellTokenSpaceGuid.PcdMdioControllers
> -	(Array with used controllers
> -	 Set to 0x1 for enabled, 0x0 for disabled)
> -
> -
> -I2C configuration
> -=================
> -In order to enable driver on a new platform, following steps need to be taken:
> - - add following line to .dsc file:
> -   edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
> - - add following line to .fdf file:
> -   INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
> - - add PCDs with relevant values to .dsc file:
> -	- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
> -		(addresses of I2C slave devices on bus)
> -	- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
> -		(buses to which accoring slaves are attached)
> -	- gMarvellTokenSpaceGuid.PcdI2cBusCount|2
> -		(number of SoC's I2C buses)
> -	- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
> -		(array with used controllers)
> -	- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
> -		(I2C host controller clock frequency)
> -	- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
> -		(baud rate used in I2C transmission)
> -
> -
> -PciEmulation configuration
> -==========================
> -Installation of various NonDiscoverable devices via PciEmulation driver is performed
> -via set of PCDs. Following are available:
> -
> -  - gMarvellTokenSpaceGuid.PcdPciEXhci
> -	(Indicates, which Xhci devices are used)
> -
> -  - gMarvellTokenSpaceGuid.PcdPciEAhci
> -	(Indicates, which Ahci devices are used)
> -
> -  - gMarvellTokenSpaceGuid.PcdPciESdhci
> -	(Indicates, which Sdhci devices are used)
> -
> -All above PCD's correspond to hardware description in a dedicated structure:
> -
> -STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
> -
> -in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device
> -count, base addresses, register region size and DMA-coherency type.
> -
> -Example
> --------
> -
> -Assuming we want to enable second XHCI port and one SDHCI port on Armada
> -70x0 board, following needs to be declared:
> -
> -		gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
> -		gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
> -
> -
> -SATA configuration
> -==================
> -There is one additional PCD for AHCI:
> -
> -  - gMarvellTokenSpaceGuid.PcdSataBaseAddress
> -	(Base address of SATA controller register space - used in SATA ComPhy init
> -	 sequence)
> -
> -
> -Pp2Dxe configuration
> -====================
> -Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
> -are required to operate:
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2Controllers
> -	(Array with used controllers
> -	 Set to 0x1 for enabled, 0x0 for disabled)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2Port2Controller
> -	(Array specifying, to which controller the port belongs to)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
> -	(Indicates speed of the network interface:
> -
> -	PHY_RGMII                        0x0
> -	PHY_RGMII_ID                     0x1
> -	PHY_RGMII_TXID                   0x2
> -	PHY_RGMII_RXID                   0x3
> -	PHY_SGMII                        0x4
> -	PHY_RTBI                         0x5
> -	PHY_XAUI                         0x6
> -	PHY_RXAUI                        0x7
> -	PHY_SFI                          0x8 )
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
> -	(Array specifying, to which PHY from
> -	 gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
> -	 e.g. in 10G SFI in-band link detection, 0xFF value must
> -	 be specified)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2PortIds
> -	(Identificators of PP2 ports)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2GopIndexes
> -	(Indexes used in GOP operation)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
> -	(Set to 0x1 for always-up interface, 0x0 otherwise)
> -
> -  - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
> -	(Indicates speed of the network interface:
> -
> -	PHY_SPEED_10                     0x1
> -	PHY_SPEED_100                    0x2
> -	PHY_SPEED_1000                   0x3
> -	PHY_SPEED_2500                   0x4
> -	PHY_SPEED_10000                  0x5 )
> -
> -
> -UTMI PHY configuration
> -======================
> -In order to configure UTMI, following PCDs are available:
> -
> -  - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
> -	(Array with used controllers
> -	 Set to 0x1 for enabled, 0x0 for disabled)
> -
> -  - gMarvellTokenSpaceGuid.PcdUtmiPortType
> -	(Indicates type of the connected USB port:
> -
> -	UTMI_USB_HOST0                     0x0
> -	UTMI_USB_HOST1                     0x1
> -	UTMI_USB_DEVICE0                   0x2 )
> -
> -Example
> --------
> -
> -		# UtmiPhy
> -		  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
> -		  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> -
> -
> -SPI driver configuration
> -========================
> -Following PCDs are available for configuration of spi driver:
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiClockFrequency
> -	(Frequency (in Hz) of SPI clock)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
> -	(Max SCLK line frequency (in Hz) (max transfer frequency) )
> -
> -SpiFlash configuration
> -======================
> -Folowing PCDs for spi flash driver configuration must be set properly:
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
> -	(Size of SPI flash address in bytes (3 or 4) )
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
> -	(Size of minimal erase block in bytes)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
> -	(Size of SPI flash page)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize
> -	(Size of SPI flash sector, 65536 bytes by default)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashId
> -	(Id of SPI flash)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
> -	(Spi flash polling flag)
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashMode
> -	(Default SCLK mode (see SPI_MODE enum in file
> -	 edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
> -
> -  - gMarvellTokenSpaceGuid.PcdSpiFlashCs
> -	(Chip select used for communication with the Flash)
> -
> -MPP configuration
> -=================
> -Multi-Purpose Ports (MPP) are configurable through platform PCDs.
> -In order to set desired pin multiplexing, .dsc file needs to be modified.
> -(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer to
> -Documentation/Build.txt for currently supported {platftorm_name} )
> -Following PCDs are available:
> -
> -  - gMarvellTokenSpaceGuid.PcdMppChipCount
> -	(Indicates how many different chips are placed on board. So far up to 4 chips
> -	 are supported)
> -
> -Every MPP PCD has <Num> part where
> - <Num> stands for chip ID (order is not important, but configuration will be
> - set for first PcdMppChipCount chips).
> -
> -Below is example for the first chip (Chip0).
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
> -	(Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
> -	(This is base address for MPP configuration register)
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0MppPinCount
> -	(Defines how many MPP pins are available)
> -
> -  - gMarvellTokenSpaceGuid.PcdChip0MppSel0
> -  - gMarvellTokenSpaceGuid.PcdChip0MppSel1
> -  - gMarvellTokenSpaceGuid.PcdChip0MppSel2
> -	(This registers defines functions of 10 pins in ascending order)
> -
> -Examples
> ---------
> -
> -		# APN806-A0 MPP SET
> -		 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> -		 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> -		 gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
> -		 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
> -		 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> -
> -Set pin 6 and 7 to 0xa function:
> -		 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
> -
> -
> -MarvellResetSystemLib configuration
> -===================================
> -This simple library allows to mask given bits in given reg at UEFI 'reset'
> -command call. These variables are configurable through PCDs:
> -
> -  - gMarvellTokenSpaceGuid.PcdResetRegAddress
> -  - gMarvellTokenSpaceGuid.PcdResetRegMask
> -
> -
> -Ramdisk configuration
> -=====================
> -There is one PCD available for Ramdisk configuration
> -
> -  - gMarvellTokenSpaceGuid.PcdRamDiskSize
> -	(Defines size of Ramdisk)
> +UEFI Porting Guide
> +==================
> +
> +This document provides instructions for adding support for new Marvell Armada
> +board. For the sake of simplicity new Marvell board will be called "new_board".
> +
> +1. Create configuration files for new target
> +        1.1 Create FDF file for new board
> +
> +         - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf to
> +           edk2-platforms/Platform/Marvell/Armada/new_board.fdf
> +         - Change the first no-comment line:
> +           [FD.Armada70x0_EFI] to [FD.{new_board}_EFI]
> +
> +        1.2 Create DSC file for new board
> +
> +         - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada directory
> +         - Insert following [Defines] section to new_board.dsc:
> +
> +                        [Defines]
> +                          PLATFORM_NAME                  = {new_board}
> +                          PLATFORM_GUID                  = {newly_generated_GUID}
> +                          PLATFORM_VERSION               = 0.1
> +                          DSC_SPECIFICATION              = 0x00010019
> +                          OUTPUT_DIRECTORY               = {output_directory}
> +                          SUPPORTED_ARCHITECTURES        = AARCH64
> +                          BUILD_TARGETS                  = DEBUG|RELEASE
> +                          SKUID_IDENTIFIER               = DEFAULT
> +                          FLASH_DEFINITION               = {path_to_fdf_file}
> +
> +         - Add "!include Armada.dsc.inc" entry to new_board.dsc
> +
> +2. Driver support
> + - According to content of files from
> +   edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt
> +   insert PCD entries into new_board.dsc for every needed interface (as listed below).
> +
> +3. Compilation
> + - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change
> +   {platform} to new_board in order to point build system to newly created DSC file.
> +
> +4. Output file
> + - Output files (and among others FD file, which may be used by ATF) are
> +   generated under directory pointed by "OUTPUT_DIRECTORY" entry (see point 1.2).
> +
> +
> +COMPHY configuration
> +====================
> +In order to configure ComPhy library, following PCDs are available:
> +
> +  - gMarvellTokenSpaceGuid.PcdComPhyDevices
> +
> +This array indicates, which ones of the ComPhy chips defined in
> +MVHW_COMPHY_DESC template will be configured.
> +
> +Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
> +important, but configuration will be set for first PcdComPhyChipCount chips).
> +
> +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
> +settings for this chip. Their format is array of up to 10 values reflecting
> +defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
> +
> +  OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
> +        (Array of types - currently supported are:
> +
> +        CP_UNCONNECTED                      0x0
> +        CP_PCIE0                            0x1
> +        CP_PCIE1                            0x2
> +        CP_PCIE2                            0x3
> +        CP_PCIE3                            0x4
> +        CP_SATA0                            0x5
> +        CP_SATA1                            0x6
> +        CP_SATA2                            0x7
> +        CP_SATA3                            0x8
> +        CP_SGMII0                           0x9
> +        CP_SGMII1                           0xA
> +        CP_SGMII2                           0xB
> +        CP_SGMII3                           0xC
> +        CP_QSGMII                           0xD
> +        CP_USB3_HOST0                       0xE
> +        CP_USB3_HOST1                       0xF
> +        CP_USB3_DEVICE                      0x10
> +        CP_XAUI0                            0x11
> +        CP_XAUI1                            0x12
> +        CP_XAUI2                            0x13
> +        CP_XAUI3                            0x14
> +        CP_RXAUI0                           0x15
> +        CP_RXAUI1                           0x16
> +        CP_SFI                              0x17 )
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
> +        (Array of speeds - currently supported are:
> +
> +        CP_1_25G                            0x1
> +        CP_1_5G                             0x2
> +        CP_2_5G                             0x3
> +        CP_3G                               0x4
> +        CP_3_125G                           0x5
> +        CP_5G                               0x6
> +        CP_5_15625G                         0x7
> +        CP_6G                               0x8
> +        CP_6_25G                            0x9
> +        CP_10_3125G                         0xA )
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
> +        (Array of lane inversion types - currently supported are:
> +
> +        CP_NO_INVERT                        0x0
> +        CP_TXD_INVERT                       0x1
> +        CP_RXD_INVERT                       0x2
> +        CP_ALL_INVERT                       0x3 )
> +
> +Example
> +-------
> +
> +                  #ComPhy
> +                  gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
> +                  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
> +                  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
> +
> +
> +PHY Driver configuration
> +========================
> +MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
> +Currently only 1518 series PHYs are supported. Following PCDs are required:
> +
> +  - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
> +        (boolean - if true, driver waits for autonegotiation on startup)
> +  - gMarvellTokenSpaceGuid.PcdPhyDeviceIds
> +        (list of values corresponding to MV_PHY_DEVICE_ID enum)
> +  - gMarvellTokenSpaceGuid.PcdPhySmiAddresses
> +        (addresses of PHY devices)
> +  - gMarvellTokenSpaceGuid.PcdPhy2MdioController
> +        (Array specifying, which Mdio controller the PHY is attached to)
> +
> +
> +MV_PHY_DEVICE_ID:
> +
> +                typedef enum {
> +                        0    MV_PHY_DEVICE_1512,
> +                } MV_PHY_DEVICE_ID;
> +
> +It should be extended when adding support for other PHY models.
> +
> +Disable autonegotiation:
> +
> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> +
> +assuming, that PHY models are 1512:
> +
> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
> +
> +
> +MDIO configuration
> +==================
> +MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
> +EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
> +
> +  - gMarvellTokenSpaceGuid.PcdMdioControllers
> +        (Array with used controllers
> +         Set to 0x1 for enabled, 0x0 for disabled)
> +
> +
> +I2C configuration
> +=================
> +In order to enable driver on a new platform, following steps need to be taken:
> + - add following line to .dsc file:
> +   edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
> + - add following line to .fdf file:
> +   INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
> + - add PCDs with relevant values to .dsc file:
> +        - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
> +                (addresses of I2C slave devices on bus)
> +        - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
> +                (buses to which accoring slaves are attached)
> +        - gMarvellTokenSpaceGuid.PcdI2cBusCount|2
> +                (number of SoC's I2C buses)
> +        - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
> +                (array with used controllers)
> +        - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
> +                (I2C host controller clock frequency)
> +        - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
> +                (baud rate used in I2C transmission)
> +
> +
> +PciEmulation configuration
> +==========================
> +Installation of various NonDiscoverable devices via PciEmulation driver is performed
> +via set of PCDs. Following are available:
> +
> +  - gMarvellTokenSpaceGuid.PcdPciEXhci
> +        (Indicates, which Xhci devices are used)
> +
> +  - gMarvellTokenSpaceGuid.PcdPciEAhci
> +        (Indicates, which Ahci devices are used)
> +
> +  - gMarvellTokenSpaceGuid.PcdPciESdhci
> +        (Indicates, which Sdhci devices are used)
> +
> +All above PCD's correspond to hardware description in a dedicated structure:
> +
> +STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
> +
> +in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device
> +count, base addresses, register region size and DMA-coherency type.
> +
> +Example
> +-------
> +
> +Assuming we want to enable second XHCI port and one SDHCI port on Armada
> +70x0 board, following needs to be declared:
> +
> +                gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
> +                gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
> +
> +
> +SATA configuration
> +==================
> +There is one additional PCD for AHCI:
> +
> +  - gMarvellTokenSpaceGuid.PcdSataBaseAddress
> +        (Base address of SATA controller register space - used in SATA ComPhy init
> +         sequence)
> +
> +
> +Pp2Dxe configuration
> +====================
> +Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
> +are required to operate:
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2Controllers
> +        (Array with used controllers
> +         Set to 0x1 for enabled, 0x0 for disabled)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2Port2Controller
> +        (Array specifying, to which controller the port belongs to)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
> +        (Indicates speed of the network interface:
> +
> +        PHY_RGMII                        0x0
> +        PHY_RGMII_ID                     0x1
> +        PHY_RGMII_TXID                   0x2
> +        PHY_RGMII_RXID                   0x3
> +        PHY_SGMII                        0x4
> +        PHY_RTBI                         0x5
> +        PHY_XAUI                         0x6
> +        PHY_RXAUI                        0x7
> +        PHY_SFI                          0x8 )
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
> +        (Array specifying, to which PHY from
> +         gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
> +         e.g. in 10G SFI in-band link detection, 0xFF value must
> +         be specified)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2PortIds
> +        (Identificators of PP2 ports)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2GopIndexes
> +        (Indexes used in GOP operation)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
> +        (Set to 0x1 for always-up interface, 0x0 otherwise)
> +
> +  - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
> +        (Indicates speed of the network interface:
> +
> +        PHY_SPEED_10                     0x1
> +        PHY_SPEED_100                    0x2
> +        PHY_SPEED_1000                   0x3
> +        PHY_SPEED_2500                   0x4
> +        PHY_SPEED_10000                  0x5 )
> +
> +
> +UTMI PHY configuration
> +======================
> +In order to configure UTMI, following PCDs are available:
> +
> +  - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
> +        (Array with used controllers
> +         Set to 0x1 for enabled, 0x0 for disabled)
> +
> +  - gMarvellTokenSpaceGuid.PcdUtmiPortType
> +        (Indicates type of the connected USB port:
> +
> +        UTMI_USB_HOST0                     0x0
> +        UTMI_USB_HOST1                     0x1
> +        UTMI_USB_DEVICE0                   0x2 )
> +
> +Example
> +-------
> +
> +                # UtmiPhy
> +                  gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
> +                  gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> +
> +
> +SPI driver configuration
> +========================
> +Following PCDs are available for configuration of spi driver:
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiClockFrequency
> +        (Frequency (in Hz) of SPI clock)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
> +        (Max SCLK line frequency (in Hz) (max transfer frequency) )
> +
> +SpiFlash configuration
> +======================
> +Folowing PCDs for spi flash driver configuration must be set properly:
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
> +        (Size of SPI flash address in bytes (3 or 4) )
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
> +        (Size of minimal erase block in bytes)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
> +        (Size of SPI flash page)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize
> +        (Size of SPI flash sector, 65536 bytes by default)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashId
> +        (Id of SPI flash)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
> +        (Spi flash polling flag)
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashMode
> +        (Default SCLK mode (see SPI_MODE enum in file
> +         edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
> +
> +  - gMarvellTokenSpaceGuid.PcdSpiFlashCs
> +        (Chip select used for communication with the Flash)
> +
> +MPP configuration
> +=================
> +Multi-Purpose Ports (MPP) are configurable through platform PCDs.
> +In order to set desired pin multiplexing, .dsc file needs to be modified.
> +(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer to
> +Documentation/Build.txt for currently supported {platftorm_name} )
> +Following PCDs are available:
> +
> +  - gMarvellTokenSpaceGuid.PcdMppChipCount
> +        (Indicates how many different chips are placed on board. So far up to 4 chips
> +         are supported)
> +
> +Every MPP PCD has <Num> part where
> + <Num> stands for chip ID (order is not important, but configuration will be
> + set for first PcdMppChipCount chips).
> +
> +Below is example for the first chip (Chip0).
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
> +        (Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
> +        (This is base address for MPP configuration register)
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0MppPinCount
> +        (Defines how many MPP pins are available)
> +
> +  - gMarvellTokenSpaceGuid.PcdChip0MppSel0
> +  - gMarvellTokenSpaceGuid.PcdChip0MppSel1
> +  - gMarvellTokenSpaceGuid.PcdChip0MppSel2
> +        (This registers defines functions of 10 pins in ascending order)
> +
> +Examples
> +--------
> +
> +                # APN806-A0 MPP SET
> +                 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> +                 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> +                 gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
> +                 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
> +                 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> +
> +Set pin 6 and 7 to 0xa function:
> +                 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
> +
> +
> +MarvellResetSystemLib configuration
> +===================================
> +This simple library allows to mask given bits in given reg at UEFI 'reset'
> +command call. These variables are configurable through PCDs:
> +
> +  - gMarvellTokenSpaceGuid.PcdResetRegAddress
> +  - gMarvellTokenSpaceGuid.PcdResetRegMask
> +
> +
> +Ramdisk configuration
> +=====================
> +There is one PCD available for Ramdisk configuration
> +
> +  - gMarvellTokenSpaceGuid.PcdRamDiskSize
> +        (Defines size of Ramdisk)
> -- 
> 1.8.3.1
>