From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::229; helo=mail-wm0-x229.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4547821F3C1AE for ; Tue, 10 Oct 2017 07:50:29 -0700 (PDT) Received: by mail-wm0-x229.google.com with SMTP id l68so6126455wmd.5 for ; Tue, 10 Oct 2017 07:53:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=C9+sKFoAvr/YGr3W+kOejpJz9x1PR/1aE3hE5423DsM=; b=fWijVza31OSzPB1xX6FtZqBmEF/azq3sCGe+FTEQJ7G+FEivsLKoGkDRSuM3N000Jj KHpcyox651+xRiBiauZ6VjhqqAQbo3fYqwsphsun5xNc4PDuNl+NjX7TEQsszZhneutu 3MMsuQX/oK5CfvMKzqwqN265nHOy+1sbAkT5o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=C9+sKFoAvr/YGr3W+kOejpJz9x1PR/1aE3hE5423DsM=; b=EEd3EomTyRZseWo8DwgW9zzOl8KROlwpa7Wr91LJqpG3v2sMWysRbjhYWRx5NtKoig hIZdCJXPMIRe7tFDfrUzKR/P2cindj4VDf6l9OkIhujl1Mffc2BtPSfjpGjNqtNEAkPd S6e6Y2+8IoEyX+PdqLhCXX3xDcH1AwZanwz4KCiwWw5hL1Rodnt2Y+eE2NTyqxzZkOMc WsSY/S99DnKpELSZEwWil4/3TZTX5WmR0o2kSUJdOEKO0MAjU8DCm3/OCYZ1GwoDz5mG AARJrTfPRk6npHfSUUtUzhZHoWdiRTr3INOVj4nn5Fz+sqKmSry27smkXKLXuLfI5Ee1 yYzw== X-Gm-Message-State: AMCzsaWRs4UabfBvUa1FZehGGhBDuScTho+ad5nTJexXOj7BFhszJY9N kUj2ldRFL3W1KBCzwfVicQV6ew== X-Google-Smtp-Source: AOwi7QCFSbHLhxtrBc9JXERFIk1ks7tyhr2fNV9wjLmppicDLYcFtTcjoCGafMUEmB2ENjMDH8Pcsw== X-Received: by 10.28.212.65 with SMTP id l62mr10375786wmg.77.1507647236109; Tue, 10 Oct 2017 07:53:56 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l19sm6719118wre.26.2017.10.10.07.53.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 07:53:54 -0700 (PDT) Date: Tue, 10 Oct 2017 15:53:53 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171010145353.do7b6msel3d25pyu@bivouac.eciton.net> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> <1507568462-28775-9-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1507568462-28775-9-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 08/13] Marvell/Armada: Modify GICC alias X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Oct 2017 14:50:29 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Oct 09, 2017 at 07:00:57PM +0200, Marcin Wojtas wrote: > From: Ard Biesheuvel > > The GIC architecture mandates that the CPU interface, which consists > of 2 consecutive 4 KB frames, can be mapped using separate mappings. > Since this is problematic on 64 KB pages, the MMU-400 aliases each > frame 16 times, and the two consecutive frames can be found at offset > 0xf000. This patch is intended to expose correct GICC alias via > MADT, once ACPI support is added. I'm afraid I don't quite understand this message. The change seems to be that the InterfaceBase moves from the first 4KB alias inside a 64KB page to the last alias within the same page. That seems valid, but I don't see how it resolves anything described in this message? / Leif > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc > index 5071bd5..bd2336f 100644 > --- a/Platform/Marvell/Armada/Armada.dsc.inc > +++ b/Platform/Marvell/Armada/Armada.dsc.inc > @@ -263,7 +263,14 @@ > > # ARM Generic Interrupt Controller > gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 > - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 > + > + # > + # NOTE: the GIC architecture mandates that the CPU interface, which consists > + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. > + # Since this is problematic on 64 KB pages, the MMU-400 aliases each frame > + # 16 times, and the two consecutive frames can be found at offset 0xf000 > + # > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 > > # ARM Architectural Timer Support > gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 > -- > 1.8.3.1 >