From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::22e; helo=mail-wm0-x22e.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com [IPv6:2a00:1450:400c:c09::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFA1E21F7D4E4 for ; Wed, 11 Oct 2017 09:53:28 -0700 (PDT) Received: by mail-wm0-x22e.google.com with SMTP id l68so6563079wmd.5 for ; Wed, 11 Oct 2017 09:56:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=k9aaQoiz8/+4Rhb0oyYGqsy5RXLla8fJtcWT6e7dDiw=; b=UOi+/EILPj2p/i208rrOHO47RmwZ4v9ziNJZ5no5D+5e7UrImbR22VNneFjT2kSCEV LKx/Rcu58vxq1zQ+yF3F6UMMs5hl87BM+ml48K3cmbfUb0Tgno8RVkeOCtLVP/20cBRC C7n4/fDjVs7htD6a3qaKMHGStDQRdxKq+x5RI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=k9aaQoiz8/+4Rhb0oyYGqsy5RXLla8fJtcWT6e7dDiw=; b=f20SjVv9dNlQkWRssb1C0w7yFozanLU+GnsShKDY4+GIiuoignnjuVYsVWP2KpjlXQ nf6mhkQiiOi2KKPpG8iuqp7PlhGEoWXXP+Ge0c+ifviOa73AvZqbtBm50AdyXGdIAbqM jei7m8mduEdBZkJsqojGSvJ5gz3RW8MIpUYypE+sisaZYTPmDY04He5PdBuEg29os3nO lDkHvTN4PBAPXNEF616rGWyOWsQrqkS02M++J4tcatMTr/l5Jp+speKarhPC97YeVE15 wy+Hy+raVE2KfTkFUJFA8zRcUIBzMnLDPMY44aeUNflTJGIxDXPpY0zu3iSO9Tgb5bbo WeQw== X-Gm-Message-State: AMCzsaUdkhCCkEPmLTel0mhj/55MaLEnW+tecNnm4uUqPiGqNrsqKmnT m4Ha9lgJ0meh3zoD25jEY+uL6w== X-Google-Smtp-Source: AOwi7QAr90bn4a4WuvjE8GTL4r9ckdmBIQ0UwWsL+JW2v4LzSISWVr3lQkg71ifMqSUuAF+PJxvOsw== X-Received: by 10.223.142.248 with SMTP id q111mr244003wrb.40.1507741017009; Wed, 11 Oct 2017 09:56:57 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o7sm21248631wrf.31.2017.10.11.09.56.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Oct 2017 09:56:56 -0700 (PDT) Date: Wed, 11 Oct 2017 17:56:54 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171011165654.ysru5fbik6p3gxae@bivouac.eciton.net> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> <1507736449-6073-4-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1507736449-6073-4-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 3/8] Marvell/Armada: Remove custom reset library residues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Oct 2017 16:53:29 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 11, 2017 at 05:40:44PM +0200, Marcin Wojtas wrote: > When switching to generic PSCI reset library, obsolete parts > of previous custom reset library (PCDs, documentation) remained. > Remove them. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Yes, please. Reviewed-by: Leif Lindholm > --- > Platform/Marvell/Armada/Armada70x0.dsc | 4 ---- > Platform/Marvell/Marvell.dec | 4 ---- > Silicon/Marvell/Documentation/PortingGuide.txt | 9 --------- > 3 files changed, 17 deletions(-) > > diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc > index 430803c..946c93e 100644 > --- a/Platform/Marvell/Armada/Armada70x0.dsc > +++ b/Platform/Marvell/Armada/Armada70x0.dsc > @@ -138,9 +138,5 @@ > gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } > gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } > > - #ResetLib > - gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 > - gMarvellTokenSpaceGuid.PcdResetRegMask|0x1 > - > #RTC > gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } > diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec > index 78f5e53..434d6cb 100644 > --- a/Platform/Marvell/Marvell.dec > +++ b/Platform/Marvell/Marvell.dec > @@ -188,10 +188,6 @@ > gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 > gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 > > -#ResetLib > - gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 > - gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 > - > #RTC > gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 > > diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt > index 66ec918..cbe3bed 100644 > --- a/Silicon/Marvell/Documentation/PortingGuide.txt > +++ b/Silicon/Marvell/Documentation/PortingGuide.txt > @@ -383,15 +383,6 @@ Set pin 6 and 7 to 0xa function: > gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } > > > -MarvellResetSystemLib configuration > -=================================== > -This simple library allows to mask given bits in given reg at UEFI 'reset' > -command call. These variables are configurable through PCDs: > - > - - gMarvellTokenSpaceGuid.PcdResetRegAddress > - - gMarvellTokenSpaceGuid.PcdResetRegMask > - > - > Ramdisk configuration > ===================== > There is one PCD available for Ramdisk configuration > -- > 2.7.4 >