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From: Ruiyu Ni <ruiyu.ni@intel.com>
To: edk2-devel@lists.01.org
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
	Eric Dong <eric.dong@intel.com>
Subject: [PATCH 1/4] UefiCpuPkg/MtrrLib: refine MtrrLibProgramFixedMtrr()
Date: Thu, 12 Oct 2017 16:48:07 +0800	[thread overview]
Message-ID: <20171012084810.148196-2-ruiyu.ni@intel.com> (raw)
In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com>

The patch replaces some if-checks with assertions because
they are impossible to happen.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
---
 UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 66 +++++++++++++++++-------------------
 1 file changed, 31 insertions(+), 35 deletions(-)

diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index cf1af29936..5b21fe11f1 100644
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -466,10 +466,10 @@ MtrrGetVariableMtrr (
   @param[in]      Type             The memory type to set.
   @param[in, out] Base             The base address of memory range.
   @param[in, out] Length           The length of memory range.
-  @param[in, out] LastMsrNum       On input, the last index of the fixed MTRR MSR to program.
+  @param[in, out] LastMsrIndex     On input, the last index of the fixed MTRR MSR to program.
                                    On return, the current index of the fixed MTRR MSR to program.
-  @param[out]     ReturnClearMask  The bits to clear in the fixed MTRR MSR.
-  @param[out]     ReturnOrMask     The bits to set in the fixed MTRR MSR.
+  @param[out]     ClearMask        The bits to clear in the fixed MTRR MSR.
+  @param[out]     OrMask           The bits to set in the fixed MTRR MSR.
 
   @retval RETURN_SUCCESS      The cache type was updated successfully
   @retval RETURN_UNSUPPORTED  The requested range or cache type was invalid
@@ -481,27 +481,25 @@ MtrrLibProgramFixedMtrr (
   IN     MTRR_MEMORY_CACHE_TYPE  Type,
   IN OUT UINT64                  *Base,
   IN OUT UINT64                  *Length,
-  IN OUT UINT32                  *LastMsrNum,
-  OUT    UINT64                  *ReturnClearMask,
-  OUT    UINT64                  *ReturnOrMask
+  IN OUT UINT32                  *LastMsrIndex,
+  OUT    UINT64                  *ClearMask,
+  OUT    UINT64                  *OrMask
   )
 {
-  UINT32  MsrNum;
+  UINT32  MsrIndex;
   UINT32  LeftByteShift;
   UINT32  RightByteShift;
-  UINT64  OrMask;
-  UINT64  ClearMask;
   UINT64  SubLength;
 
   //
   // Find the fixed MTRR index to be programmed
   //
-  for (MsrNum = *LastMsrNum + 1; MsrNum < MTRR_NUMBER_OF_FIXED_MTRR; MsrNum++) {
-    if ((*Base >= mMtrrLibFixedMtrrTable[MsrNum].BaseAddress) &&
+  for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
+    if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&
         (*Base <
             (
-              mMtrrLibFixedMtrrTable[MsrNum].BaseAddress +
-              (8 * mMtrrLibFixedMtrrTable[MsrNum].Length)
+              mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +
+              (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)
             )
           )
         ) {
@@ -509,65 +507,63 @@ MtrrLibProgramFixedMtrr (
     }
   }
 
-  if (MsrNum == MTRR_NUMBER_OF_FIXED_MTRR) {
-    return RETURN_UNSUPPORTED;
-  }
+  ASSERT (MsrIndex != ARRAY_SIZE (mMtrrLibFixedMtrrTable));
 
   //
   // Find the begin offset in fixed MTRR and calculate byte offset of left shift
   //
-  LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrNum].BaseAddress)
-               / mMtrrLibFixedMtrrTable[MsrNum].Length;
-
-  if (LeftByteShift >= 8) {
+  if ((((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {
+    //
+    // Base address should be aligned to the begin of a certain Fixed MTRR range.
+    //
     return RETURN_UNSUPPORTED;
   }
+  LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
+  ASSERT (LeftByteShift < 8);
 
   //
   // Find the end offset in fixed MTRR and calculate byte offset of right shift
   //
-  SubLength = mMtrrLibFixedMtrrTable[MsrNum].Length * (8 - LeftByteShift);
+  SubLength = mMtrrLibFixedMtrrTable[MsrIndex].Length * (8 - LeftByteShift);
   if (*Length >= SubLength) {
     RightByteShift = 0;
   } else {
-    RightByteShift = 8 - LeftByteShift -
-                (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrNum].Length;
-    if ((LeftByteShift >= 8) ||
-        (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrNum].Length) != 0)
-        ) {
+    if (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {
+      //
+      // Length should be aligned to the end of a certain Fixed MTRR range.
+      //
       return RETURN_UNSUPPORTED;
     }
+    RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
     //
     // Update SubLength by actual length
     //
     SubLength = *Length;
   }
 
-  ClearMask = CLEAR_SEED;
-  OrMask    = MultU64x32 (OR_SEED, (UINT32) Type);
+  *ClearMask = CLEAR_SEED;
+  *OrMask    = MultU64x32 (OR_SEED, (UINT32) Type);
 
   if (LeftByteShift != 0) {
     //
     // Clear the low bits by LeftByteShift
     //
-    ClearMask &= LShiftU64 (ClearMask, LeftByteShift * 8);
-    OrMask    &= LShiftU64 (OrMask, LeftByteShift * 8);
+    *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);
+    *OrMask    &= LShiftU64 (*OrMask,    LeftByteShift * 8);
   }
 
   if (RightByteShift != 0) {
     //
     // Clear the high bits by RightByteShift
     //
-    ClearMask &= RShiftU64 (ClearMask, RightByteShift * 8);
-    OrMask    &= RShiftU64 (OrMask, RightByteShift * 8);
+    *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);
+    *OrMask    &= RShiftU64 (*OrMask,    RightByteShift * 8);
   }
 
   *Length -= SubLength;
   *Base   += SubLength;
 
-  *LastMsrNum      = MsrNum;
-  *ReturnClearMask = ClearMask;
-  *ReturnOrMask    = OrMask;
+  *LastMsrIndex    = MsrIndex;
 
   return RETURN_SUCCESS;
 }
-- 
2.12.2.windows.2



  reply	other threads:[~2017-10-12  8:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-12  8:48 [PATCH 0/4] Update MTRR algorithm to calculate optimal settings Ruiyu Ni
2017-10-12  8:48 ` Ruiyu Ni [this message]
2017-10-12  8:48 ` [PATCH 2/4] UefiCpuPkg/MtrrLib: Optimize MtrrLibLeastAlignment() Ruiyu Ni
2017-10-12  8:48 ` [PATCH 3/4] UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings Ruiyu Ni
2017-11-09  1:36   ` Laszlo Ersek
2017-11-09  1:53     ` Jordan Justen
2017-11-09  3:04       ` Ni, Ruiyu
2017-11-09  3:19         ` 答复: " Fan Jeff
2017-11-09  6:55         ` Jordan Justen
2017-11-09  7:11           ` Ni, Ruiyu
2017-11-09 13:15             ` Laszlo Ersek
2017-11-10  0:52               ` Ni, Ruiyu
2017-11-10 14:45                 ` Laszlo Ersek
2017-10-12  8:48 ` [PATCH 4/4] UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid Ruiyu Ni
2017-10-16  3:02 ` [PATCH 0/4] Update MTRR algorithm to calculate optimal settings Yao, Jiewen
2017-10-16  3:25   ` Ni, Ruiyu

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