From: Ruiyu Ni <ruiyu.ni@intel.com>
To: edk2-devel@lists.01.org
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH 4/4] UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid
Date: Thu, 12 Oct 2017 16:48:10 +0800 [thread overview]
Message-ID: <20171012084810.148196-5-ruiyu.ni@intel.com> (raw)
In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com>
The patch optimized the MTRR access code to skip the Base MSR
access when the Mask MSR indicates the pair is invalid.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 ++++++++++++++++-------------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index a7adbafae3..2fd1d0153e 100644
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -449,10 +449,13 @@ MtrrGetVariableMtrrWorker (
for (Index = 0; Index < VariableMtrrCount; Index++) {
if (MtrrSetting == NULL) {
- VariableSettings->Mtrr[Index].Base =
- AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));
- VariableSettings->Mtrr[Index].Mask =
- AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));
+ VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));
+ //
+ // Skip to read the Base MSR when the Mask.V is not set.
+ //
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
+ VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));
+ }
} else {
VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base;
VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask;
@@ -2540,14 +2543,14 @@ MtrrSetVariableMtrrWorker (
ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));
for (Index = 0; Index < VariableMtrrCount; Index++) {
- AsmWriteMsr64 (
- MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),
- VariableSettings->Mtrr[Index].Base
- );
- AsmWriteMsr64 (
- MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),
- VariableSettings->Mtrr[Index].Mask
- );
+ //
+ // Mask MSR is always updated since caller might need to invalidate the MSR pair.
+ // Base MSR is skipped when Mask.V is not set.
+ //
+ AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask);
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
+ AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base);
+ }
}
}
@@ -2800,7 +2803,7 @@ MtrrDebugPrintAllMtrrsWorker (
}
for (Index = 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++) {
- if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) {
//
// If mask is not valid, then do not display range
//
--
2.12.2.windows.2
next prev parent reply other threads:[~2017-10-12 8:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-12 8:48 [PATCH 0/4] Update MTRR algorithm to calculate optimal settings Ruiyu Ni
2017-10-12 8:48 ` [PATCH 1/4] UefiCpuPkg/MtrrLib: refine MtrrLibProgramFixedMtrr() Ruiyu Ni
2017-10-12 8:48 ` [PATCH 2/4] UefiCpuPkg/MtrrLib: Optimize MtrrLibLeastAlignment() Ruiyu Ni
2017-10-12 8:48 ` [PATCH 3/4] UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings Ruiyu Ni
2017-11-09 1:36 ` Laszlo Ersek
2017-11-09 1:53 ` Jordan Justen
2017-11-09 3:04 ` Ni, Ruiyu
2017-11-09 3:19 ` 答复: " Fan Jeff
2017-11-09 6:55 ` Jordan Justen
2017-11-09 7:11 ` Ni, Ruiyu
2017-11-09 13:15 ` Laszlo Ersek
2017-11-10 0:52 ` Ni, Ruiyu
2017-11-10 14:45 ` Laszlo Ersek
2017-10-12 8:48 ` Ruiyu Ni [this message]
2017-10-16 3:02 ` [PATCH 0/4] Update MTRR " Yao, Jiewen
2017-10-16 3:25 ` Ni, Ruiyu
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