From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 023B921F38820 for ; Thu, 12 Oct 2017 01:44:47 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 12 Oct 2017 01:48:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,365,1503385200"; d="scan'208";a="909212144" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 01:48:17 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Michael D Kinney Date: Thu, 12 Oct 2017 16:48:10 +0800 Message-Id: <20171012084810.148196-5-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com> References: <20171012084810.148196-1-ruiyu.ni@intel.com> Subject: [PATCH 4/4] UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Oct 2017 08:44:48 -0000 The patch optimized the MTRR access code to skip the Base MSR access when the Mask MSR indicates the pair is invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index a7adbafae3..2fd1d0153e 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -449,10 +449,13 @@ MtrrGetVariableMtrrWorker ( for (Index = 0; Index < VariableMtrrCount; Index++) { if (MtrrSetting == NULL) { - VariableSettings->Mtrr[Index].Base = - AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); - VariableSettings->Mtrr[Index].Mask = - AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); + VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); + // + // Skip to read the Base MSR when the Mask.V is not set. + // + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); + } } else { VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base; VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask; @@ -2540,14 +2543,14 @@ MtrrSetVariableMtrrWorker ( ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr)); for (Index = 0; Index < VariableMtrrCount; Index++) { - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), - VariableSettings->Mtrr[Index].Base - ); - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), - VariableSettings->Mtrr[Index].Mask - ); + // + // Mask MSR is always updated since caller might need to invalidate the MSR pair. + // Base MSR is skipped when Mask.V is not set. + // + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask); + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base); + } } } @@ -2800,7 +2803,7 @@ MtrrDebugPrintAllMtrrsWorker ( } for (Index = 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++) { - if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) { // // If mask is not valid, then do not display range // -- 2.12.2.windows.2