[PATCH 2/5] Silicon/AMD/Styx: update SMMU id to MMU-401

[Ard Biesheuvel <ard.biesheuvel@linaro.org>]

The IORT spec has been updated to include more specific defines for the
MMU-401, which supports more page sizes than the generic SMMU v1. Note
that this requires an OS that understands these new definitions.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/AMD/Styx/AcpiTables/Iort.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c
index 80872773ba7d..370e71e13610 100644
--- a/Silicon/AMD/Styx/AcpiTables/Iort.c
+++ b/Silicon/AMD/Styx/AcpiTables/Iort.c
@@ -84,7 +84,7 @@ typedef struct {
     },                                                      \
     Base,                                                   \
     Size,                                                   \
-    EFI_ACPI_IORT_SMMUv1v2_MODEL_v1,                        \
+    EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401,                    \
     EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK,                   \
     FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE,       \
                  SMMU_NSgIrpt),                             \
-- 
2.11.0