From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::232; helo=mail-wm0-x232.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5DAEB202E60F0 for ; Sun, 15 Oct 2017 02:51:41 -0700 (PDT) Received: by mail-wm0-x232.google.com with SMTP id u138so28792003wmu.4 for ; Sun, 15 Oct 2017 02:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zLG+h+ypgsFGtG3/j1YuiXtrIGgpBaTN/BWY3qBgiBE=; b=cDEKBF6hSWT98aHOyraSaG5IcrykdpD6g9Uy9xtCCx0ZCPRsE8hB7oRlESMMWKxETH UKKhI2fVBYHYzQ+6uNRH+SAZJbicQbR+exoPk4U0c7VaBxxSKZCs3ihjBc3Dawv+vwBL Vmz0TF2sroGk+gy8SvMVgnfAGcR5F2ajMTZ7g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zLG+h+ypgsFGtG3/j1YuiXtrIGgpBaTN/BWY3qBgiBE=; b=h9ssoRh+qPOJJqEqt1VN4TWkImZqIUH0Wh2nz33e27L5MIKRvmqiFlQMrnoNjqVhEd r7tZ9eqgg52ty3lGrzBf7Ywn1wYb1DpOpYlGuwfY+NTlBZ4LFfhsytI1sVofGqzwHOVU 06HCUGtdQ9+Wft4Zb6oVMFBV3u7ziznDwjWUSV7xjUoLdAKvE2IS28yY2nPchhTu4P97 xwFYgt/vdbodQj47gyhKkWAoUpS2+W3Efa2wO7b5iwFX/ryTro2SDm58wriUdakLf24Y 51gSYpJ1iDsy/oM1Lk46ZX35y+rlwp0s3TRv7c3cex8Zb48fJfWQEbMjVS+K9Z9ZDL/g 1XuQ== X-Gm-Message-State: AMCzsaWOQwl4EniCfGr+DJeAbPUjAhb81+7QfnjXFBe6bkOhNFEf4e0T q/MQuI7zFBfePw9jTomy/rlo+4zTBUQ= X-Google-Smtp-Source: ABhQp+Rpr59PeWB9ZfljrBnlC/43r4+fFgB3TqerpiAtMNo+ae0mWgKt80mOf1/3Q1+eW2ROZzcGag== X-Received: by 10.28.153.85 with SMTP id b82mr4483942wme.121.1508061313592; Sun, 15 Oct 2017 02:55:13 -0700 (PDT) Received: from localhost.localdomain ([154.146.29.151]) by smtp.gmail.com with ESMTPSA id 25sm3938943wrv.8.2017.10.15.02.55.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 15 Oct 2017 02:55:12 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, alan@softiron.co.uk, naresh.bhat@linaro.org, Ard Biesheuvel Date: Sun, 15 Oct 2017 10:54:50 +0100 Message-Id: <20171015095453.4420-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171015095453.4420-1-ard.biesheuvel@linaro.org> References: <20171015095453.4420-1-ard.biesheuvel@linaro.org> Subject: [PATCH 2/5] Silicon/AMD/Styx: update SMMU id to MMU-401 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Oct 2017 09:51:41 -0000 The IORT spec has been updated to include more specific defines for the MMU-401, which supports more page sizes than the generic SMMU v1. Note that this requires an OS that understands these new definitions. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AcpiTables/Iort.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/AMD/Styx/AcpiTables/Iort.c b/Silicon/AMD/Styx/AcpiTables/Iort.c index 80872773ba7d..370e71e13610 100644 --- a/Silicon/AMD/Styx/AcpiTables/Iort.c +++ b/Silicon/AMD/Styx/AcpiTables/Iort.c @@ -84,7 +84,7 @@ typedef struct { }, \ Base, \ Size, \ - EFI_ACPI_IORT_SMMUv1v2_MODEL_v1, \ + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401, \ EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, \ FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, \ SMMU_NSgIrpt), \ -- 2.11.0