From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9786D2034715B for ; Fri, 20 Oct 2017 02:52:32 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 20 Oct 2017 02:56:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,405,1503385200"; d="scan'208";a="325553976" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by fmsmga004.fm.intel.com with ESMTP; 20 Oct 2017 02:56:10 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Eric Dong Date: Fri, 20 Oct 2017 17:56:08 +0800 Message-Id: <20171020095608.161848-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 Subject: [PATCH] MdeModulePkg/PciBus: Fix bug that PCI BUS claims too much resource X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Oct 2017 09:52:32 -0000 The bug was caused by 728d74973c9262b6c7b7ef4be213223d55affec3 "MdeModulePkg/PciBus: Count multiple hotplug resource paddings". The patch firstly updated the Bridge->Alignment to the maximum alignment of all devices under the bridge, then aligned the Bridge->Length to Bridge->Alignment. It caused too much resources were claimed. The new patch firstly aligns Bridge->Length to Bridge->Alignment, then updates the Bridge->Alignment to the maximum alignment of all devices under the bridge. Because the step to update the Bridge->Alignment is to make sure the resource allocated to the bus under the Bridge meets all devices alignment. But the Bridge->Length doesn't have to align to the maximum alignment. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Eric Dong --- .../Bus/Pci/PciBusDxe/PciResourceSupport.c | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 8dbe9a0038..2f713fcee9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -389,18 +389,7 @@ CalculateResourceAperture ( } // - // Adjust the bridge's alignment to the MAX (first) alignment of all children. - // - CurrentLink = Bridge->ChildList.ForwardLink; - if (CurrentLink != &Bridge->ChildList) { - Node = RESOURCE_NODE_FROM_LINK (CurrentLink); - if (Node->Alignment > Bridge->Alignment) { - Bridge->Alignment = Node->Alignment; - } - } - - // - // At last, adjust the aperture with the bridge's alignment + // Adjust the aperture with the bridge's alignment // Aperture[PciResUsageTypical] = ALIGN_VALUE (Aperture[PciResUsageTypical], Bridge->Alignment + 1); Aperture[PciResUsagePadding] = ALIGN_VALUE (Aperture[PciResUsagePadding], Bridge->Alignment + 1); @@ -410,6 +399,17 @@ CalculateResourceAperture ( // Use the larger one between the padding resource and actual occupied resource. // Bridge->Length = MAX (Aperture[PciResUsageTypical], Aperture[PciResUsagePadding]); + + // + // Adjust the bridge's alignment to the MAX (first) alignment of all children. + // + CurrentLink = Bridge->ChildList.ForwardLink; + if (CurrentLink != &Bridge->ChildList) { + Node = RESOURCE_NODE_FROM_LINK (CurrentLink); + if (Node->Alignment > Bridge->Alignment) { + Bridge->Alignment = Node->Alignment; + } + } } /** -- 2.12.2.windows.2