From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E108E21CEB15C for ; Wed, 25 Oct 2017 03:50:00 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id q124so1066437wmb.0 for ; Wed, 25 Oct 2017 03:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0kTM6lho3Xo8aOyabXBZ+SjlXhK9bRmVu8W1PAiNtyI=; b=EuI6CpUb00B15ibRt9qxMNpYcbjn3elJTkFDle6nsscGI8EGq5NlVepMbTpYvxs8W0 8eApRRLcfiJJ+98fYwLlXhrNJO75k3j/zbS9ytZ0i68/n0pILbjXnishvejhuJHz0q2t C83KebFAogxQTzeiUkXE3JsHo/+vpAR3nBT5s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0kTM6lho3Xo8aOyabXBZ+SjlXhK9bRmVu8W1PAiNtyI=; b=UjzmQYube+Y6hrvBnZKO3jVQxOwzL0355J/m689y0fvzb403sMRiDIWzgvRuNiyifj Rkonk1YwmyvGI+VgMEN7IjseAmtJyokPO7pM6GTEcUsLetoBohTxw1HZZ3+CXtl04u5a 6Ws5FopZQVVR56/t7XnHB+0iwoqzQxz3FO/HTQgQ27XDAlEkjkFM6CHWS9Tnm9RftCQm KIx/mjzLH1+wWusL+aTyV9KbV7MDiGsPZ7p32N3sGQkvyOGCSHuYEWAhaUrmBHEhdecy 18fuakJYr9kV7VZgMun81GXLceBS8iJb2oq3t0jNg6zSfHIppgRiqfcVMfYDKBQXBf4V cRYQ== X-Gm-Message-State: AMCzsaVnMzgM0We93fUlJ5NPCA93AjB6J8JQo02XmmBSd1bgw8dOQC3F qYyXu+VG7LomZ9RVhJgP+BquCw== X-Google-Smtp-Source: ABhQp+QH8ZBExibnCkWyPduGP0rXQT8A1AC1mAKKh9+Qh+tcajyn+PEucoJi5V7ZKFoSAWlPhQSXVQ== X-Received: by 10.28.93.200 with SMTP id r191mr1451596wmb.19.1508928824010; Wed, 25 Oct 2017 03:53:44 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f84sm1832429wme.44.2017.10.25.03.53.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2017 03:53:43 -0700 (PDT) Date: Wed, 25 Oct 2017 11:53:41 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171025105341.qkyftjvwxtkpk4db@bivouac.eciton.net> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> <1508913930-30886-5-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1508913930-30886-5-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 10:50:01 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject line still wrong. from -> for On Wed, Oct 25, 2017 at 08:45:26AM +0200, Marcin Wojtas wrote: > The Armada 70x0/80x0 DRAM controller allows a single window of DRAM > to be remapped to another location in the physical address space. Since DRAM starts at address 0, and normally exceeds 4GB on these systems, this ... content below is fine. / Leif > This > allows us to free up some memory in the 32-bit addressable region for > peripheral MMIO and PCI MMIO32 and CONFIG spaces. > > This patch adjusts memory blocks to the configuration done in ARM-TF. > The remap parameters are otained directly from the registers. Moreover, > the configuration space base address is now configurable via PCD, so > that to satisfy a case, when remap is not enabled in the early firmware > and ensure, that PcdSystemMemorySize is not overlapping it. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > Signed-off-by: Ard Biesheuvel > --- > Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 + > Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 90 +++++++++++++++----- > Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 48 +++++++++++ > Platform/Marvell/Marvell.dec | 3 + > 4 files changed, 124 insertions(+), 19 deletions(-) > > diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > index 2e198c3..2236d9f 100644 > --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf > @@ -67,5 +67,7 @@ > gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > gArmTokenSpaceGuid.PcdArmPrimaryCore > > + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress > + > [Ppis] > gArmMpCoreInfoPpiGuid > diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c > index 74c9956..978e4d3 100644 > --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c > +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c > @@ -35,8 +35,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #include > #include > #include > +#include > +#include > #include > > +#include "Armada70x0LibMem.h" > + > // The total number of descriptors, including the final "end-of-table" descriptor. > #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 > > @@ -44,6 +48,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK > #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED > > +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS]; > + > /** > Return the Virtual Memory Map of your platform > > @@ -59,35 +65,81 @@ ArmPlatformGetVirtualMemoryMap ( > IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap > ) > { > - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > UINTN Index = 0; > + UINT64 MemSize; > + UINT64 MemLowSize; > + UINT64 MemHighStart; > + UINT64 MemHighSize; > + UINT64 ConfigSpaceBaseAddr; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > > ASSERT (VirtualMemoryMap != NULL); > > - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); > - if (VirtualMemoryTable == NULL) { > - return; > + ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress); > + > + MemSize = FixedPcdGet64 (PcdSystemMemorySize); > + > + if (DRAM_REMAP_ENABLED) { > + MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize); > + MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE; > + MemHighSize = MemSize - MemLowSize; > + } else { > + MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize); > } > > - // DDR > - VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); > - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); > - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); > - VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; > + ResourceAttributes = ( > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED > + ); > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdSystemMemoryBase), > + MemLowSize > + ); > > - // Configuration space 0xF000_0000 - 0xFFFF_FFFF > - VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000; > - VirtualMemoryTable[Index].VirtualBase = 0xF0000000; > - VirtualMemoryTable[Index].Length = 0x10000000; > - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + // DDR > + mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase); > + mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase); > + mVirtualMemoryTable[Index].Length = MemLowSize; > + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; > + > + // Configuration space > + mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr; > + mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr; > + mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr; > + mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + if (MemSize > MemLowSize) { > + // > + // If we have more than MemLowSize worth of DRAM, the remainder will be > + // mapped at the top of the remapped window. > + // > + mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart; > + mVirtualMemoryTable[Index].VirtualBase = MemHighStart; > + mVirtualMemoryTable[Index].Length = MemHighSize; > + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + MemHighStart, > + MemHighSize > + ); > + } > > // End of Table > - VirtualMemoryTable[++Index].PhysicalBase = 0; > - VirtualMemoryTable[Index].VirtualBase = 0; > - VirtualMemoryTable[Index].Length = 0; > - VirtualMemoryTable[Index].Attributes = 0; > + mVirtualMemoryTable[++Index].PhysicalBase = 0; > + mVirtualMemoryTable[Index].VirtualBase = 0; > + mVirtualMemoryTable[Index].Length = 0; > + mVirtualMemoryTable[Index].Attributes = 0; > > ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); > > - *VirtualMemoryMap = VirtualMemoryTable; > + *VirtualMemoryMap = mVirtualMemoryTable; > } > diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h > new file mode 100644 > index 0000000..8101cf3 > --- /dev/null > +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h > @@ -0,0 +1,48 @@ > +/******************************************************************************* > +Copyright (C) 2017 Marvell International Ltd. > + > +Marvell BSD License Option > + > +If you received this File from Marvell, you may opt to use, redistribute and/or > +modify this File under the following licensing terms. > +Redistribution and use in source and binary forms, with or without modification, > +are permitted provided that the following conditions are met: > + > +* Redistributions of source code must retain the above copyright notice, > + this list of conditions and the following disclaimer. > + > +* Redistributions in binary form must reproduce the above copyright > + notice, this list of conditions and the following disclaimer in the > + documentation and/or other materials provided with the distribution. > + > +* Neither the name of Marvell nor the names of its contributors may be > + used to endorse or promote products derived from this software without > + specific prior written permission. > + > +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND > +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR > +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; > +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + > +*******************************************************************************/ > + > +#define CCU_MC_RCR_REG 0xf0001700 > +#define REMAP_EN_MASK 0x1 > +#define REMAP_SIZE_OFFS 20 > +#define REMAP_SIZE_MASK (0xfff << REMAP_SIZE_OFFS) > +#define CCU_MC_RTBR_REG 0xf0001708 > +#define TARGET_BASE_OFFS 10 > +#define TARGET_BASE_MASK (0xfffff << TARGET_BASE_OFFS) > + > +#define DRAM_REMAP_ENABLED \ > + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_EN_MASK) > +#define DRAM_REMAP_SIZE \ > + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB > +#define DRAM_REMAP_TARGET \ > + (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) > diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec > index 434d6cb..36a9d59 100644 > --- a/Platform/Marvell/Marvell.dec > +++ b/Platform/Marvell/Marvell.dec > @@ -194,6 +194,9 @@ > #TRNG > gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 > > +#Configuration space > + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054 > + > [Protocols] > gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} > gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} > -- > 2.7.4 >