From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B535620352613 for ; Wed, 25 Oct 2017 10:56:57 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id p75so3456941wmg.3 for ; Wed, 25 Oct 2017 11:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jsf5dzgOG/KJ9rDk2dkZHIXzl/EaXtdHkxQJSRjn9Pc=; b=WaoOw7Tw5jZrrdXvPHRC4tN6uY1cG0PtOQXHtJNKo3kFxS3iDisu3GypqtJf7dRWqb W4jEbSisR8sugh+9pHdgDUERjFRvAvwnrl1BlADcyKp1lkMrBRRX18VkiGKpA0rZZz9S uwPFSGHMok36LcvC0qW3ilLqJe5g3mmVx4wn4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jsf5dzgOG/KJ9rDk2dkZHIXzl/EaXtdHkxQJSRjn9Pc=; b=I18Dp7AcqkrTfA64huKfg47jkxK/eZ41H26GbCN8i7R9SIq66deXPutgSo0LZ36ewF HljwbjNpr0zm3oltDoatFkM60yZR/aU5Jv7sRzVT0jvZj07h1+GWiWeLHs0dQHDY+JR3 MwzJz3/8LA0buDWPPOQ2CFVO7wPXZeJPiwtTGzLdeRr2EN2w1B6wb7QYEOg1ruDYemeq 43sLhbBkqzh4CAaOqYucyF0VcHDcVpEDM/L1lrw14YGqGTyGT1W7dB3wOb5NcN3KWZrR rRYzbkD6GA5+hUQBy7c7QA9FQEEJ2sW/OE7X3chXFlD2Wuvn3EH25br0hGXrUT9bIT+A DwzA== X-Gm-Message-State: AMCzsaWeil6OsvG1ysQfZp8Lt6UwLVH3QgTaYXCe7FJlmdNjfxEdWcAS bhET2YDrScvt2DrS0/lvJVoNvXq68Mc= X-Google-Smtp-Source: ABhQp+SC8NvGVtOgvdUW/QOdcOm13k960tG9uGrITJxjf1PvXFMFi0xpRZIyypfvijsbNUF9mjvEdQ== X-Received: by 10.28.13.135 with SMTP id 129mr2697520wmn.24.1508954441474; Wed, 25 Oct 2017 11:00:41 -0700 (PDT) Received: from localhost.localdomain ([160.161.173.60]) by smtp.gmail.com with ESMTPSA id y29sm3255305wrd.3.2017.10.25.11.00.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Oct 2017 11:00:40 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Date: Wed, 25 Oct 2017 18:59:45 +0100 Message-Id: <20171025175947.22798-22-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171025175947.22798-1-ard.biesheuvel@linaro.org> References: <20171025175947.22798-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v2 21/23] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 17:56:58 -0000 Implement workaround suggested by Socionext to get legacy endpoints with 32-bit BARs working. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3c6eff602f74..dd6c9bf90223 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -31,10 +31,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 @@ -296,8 +299,9 @@ PciInitController ( RootBridge->Mem.Base, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); // Region 1: Type 0 config space ConfigureWindow (DbiBase, 1, -- 2.11.0