Re: [platforms: PATCH 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting

[Leif Lindholm <leif.lindholm@linaro.org>]

On Thu, Oct 26, 2017 at 03:19:35AM +0200, Marcin Wojtas wrote:
> This patch fixes incorrect settings for UHS mode in
> SD_MMC_HC_HOST_CTRL2 register. This field should be set to
> 
> 0x4 for DDR52
> 0x2 for SDR50
> 0x1 for SDR25
> 0x0 for others.
> 
> This way EmmcSwitchToHighSpeed function is on par with Linux
> set_uhs_signaling routine in the Xenon driver.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> index 3f73194..4d4833f 100755
> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c
> @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed (
>    if (IsDdr) {
>      HostCtrl2 = BIT2;
>    } else if (ClockFreq == 52) {
> +    HostCtrl2 = BIT1;
> +  } else if (ClockFreq == 26) {

This patch adds previously missing handling of SDR25 (I guess).
Please reflect this in commit message.

/
    Leif

>      HostCtrl2 = BIT0;
>    } else {
>      HostCtrl2 = 0;
> -- 
> 2.7.4
>