From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2957C203525FD for ; Thu, 26 Oct 2017 06:37:24 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id r196so8095997wmf.2 for ; Thu, 26 Oct 2017 06:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=squUJWjKuYnj3Gmm7z8y33J+lqFwT5k9FXbIldY1Pu4=; b=Zb8ZkdrFBJHiyNv/sBZbVCBvO5r6wSat9OFGNfdQJPLw6bJLINvDQlaOvEROAQvEyf EXymb9AyHto9+6nVdAgY+guFNdNngJqvYMXYcOTaaRWllPVXoPH65o20ii9kSHg57Vus C/gKe1E97eKBN3CIpOZwSk9AsY2xygLSA6q7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=squUJWjKuYnj3Gmm7z8y33J+lqFwT5k9FXbIldY1Pu4=; b=TgCDvNnluqvhtUt8wrj3/i5CLM6PlDAXI1hL5/RXqe55oPQ60oLxMFBn6ektNM0jDp 3UizOE7tK3yBMA4443Qre4uIS6DU3Gbr9gpibjVTSg4++4WMKj4EaxFw+ZDvf0DPj7da mzUkY/xC3oc6SxFrdM00miYPb2i5aA4Dg+0TOWZVC3hhGMXcVaEaJZLti6CwoSAYtN2q y9nCXu+N92DjDxPF99wjdz1gRhsM62B3igjeEMwVheTEJN5+VTmvW9X02cZsHqGduuLR 63RmotgYs+77zeCcb5A4uDafUdtPTr2fBz2msWeRl1H6qp97ZqNz++gntuLHY9hpGiEr DKkw== X-Gm-Message-State: AMCzsaWALr8DSk8PIEehiU6xlDx1TZtqjzdmiKG9cjVKBmIPd3gJgZt0 XQissUeaJdv1z0uktMYr/gd/T2razbs= X-Google-Smtp-Source: ABhQp+QoNkEga6LtbOYHBmaPu5FmDfOg1ETi1QEnGtoWUVJNDdc4nFmXVl8/NvveWzNJ/fVHFXop8w== X-Received: by 10.28.143.130 with SMTP id r124mr1725195wmd.122.1509025269050; Thu, 26 Oct 2017 06:41:09 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y29sm4585508wrd.3.2017.10.26.06.41.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 06:41:07 -0700 (PDT) Date: Thu, 26 Oct 2017 14:41:06 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171026134106.tdr27ighebhlzrdp@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-9-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1508980777-29006-9-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:37:24 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 26, 2017 at 03:19:35AM +0200, Marcin Wojtas wrote: > This patch fixes incorrect settings for UHS mode in > SD_MMC_HC_HOST_CTRL2 register. This field should be set to > > 0x4 for DDR52 > 0x2 for SDR50 > 0x1 for SDR25 > 0x0 for others. > > This way EmmcSwitchToHighSpeed function is on par with Linux > set_uhs_signaling routine in the Xenon driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > index 3f73194..4d4833f 100755 > --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c > @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( > if (IsDdr) { > HostCtrl2 = BIT2; > } else if (ClockFreq == 52) { > + HostCtrl2 = BIT1; > + } else if (ClockFreq == 26) { This patch adds previously missing handling of SDR25 (I guess). Please reflect this in commit message. / Leif > HostCtrl2 = BIT0; > } else { > HostCtrl2 = 0; > -- > 2.7.4 >