From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BD17A203525FD for ; Thu, 26 Oct 2017 06:42:30 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id g90so3218915wrd.6 for ; Thu, 26 Oct 2017 06:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ErEnLDWx08Jx7mRnKLSrEtD8WOWzihlJ5u5ozY7wO90=; b=AKNGESe5fX1+cN7cUIhTLHzy5EAr5tOyFAoMrDoLV3B+6CTWQV217GQJ4sDdthCYBe l34VU6SAUKSq6lD4oOfm1Xeqfo4/X+1pmVxLRf5Pmu5NF4JsuxYuI1o+z8bN8NxzTu9/ IR/0OX6n8i7nolWRyi/uBKIqMFdqUYSw0U5VE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ErEnLDWx08Jx7mRnKLSrEtD8WOWzihlJ5u5ozY7wO90=; b=r6k4ve16qSCGqLLsXhSnoeVsyxsBjDJI6MOnk/IW1unfnmX40Wo1KnVfyhhOEcM1rc ZZUdtR9vYfhIXCzHsYYEzTmv9O33rS9PpIna98HRlpqc+dhQJ6LDQf4lkK7veeO3ZuDT 7oKMcfSotjU0MdTQfK8v46kxTeOzZSHVJp9PPG9l3Mq3rttd04NCmDXx6Jq5knFdOBlR lpn6lisX4UE6dFqN36XS7QtZn9ytR9Fq+1TGJo8dd7dpwa14gWXPsx8jcE7sQC+AFCGO 6r2Eln8XccYKxFAEYywdElArZB1UgnU32IvrSKozHA8NndCU4auexu+rl78WSN0IXAsL FeYQ== X-Gm-Message-State: AMCzsaUYbLJuwSVY4lBIwLtaOdmIjLh7woKs+oYEuTOVUQ5xjbKZm4CS LplkzMHNIiEwX1ZQDPbKBMLLYg== X-Google-Smtp-Source: ABhQp+TTuwIl9sYFZTpqRP7JNjIKB8oU596Yb37rwAtgCI2BJ0xqqXpV9tcoSzVnaIcEIGHIAnJTMg== X-Received: by 10.223.193.70 with SMTP id w6mr5670159wre.158.1509025575497; Thu, 26 Oct 2017 06:46:15 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id x49sm4503773wrb.25.2017.10.26.06.46.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 06:46:14 -0700 (PDT) Date: Thu, 26 Oct 2017 14:46:12 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1508980777-29006-10-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:42:31 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: > Incorrectly the clock divisor was calculated relatively > to 255MHz instead of actual 400MHz. This describes the specific symptom, not the problem with the existing code. > Fix this. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c > index ccbf355..0b9328b 100644 > --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c > +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c > @@ -16,6 +16,7 @@ > **/ > > #include "SdMmcPciHcDxe.h" > +#include "XenonSdhci.h" > > /** > Dump the content of SD/MMC host controller's Capability Register. > @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( > // > // Calculate a divisor for SD clock frequency > // > - ASSERT (Capability.BaseClkFreq != 0); > > - BaseClkFreq = Capability.BaseClkFreq; Why is Capability.BaseClkFreq the wrong frequency to use? / Leif > + BaseClkFreq = XENON_MMC_MAX_CLK / 1000 / 1000; > if (ClockFreq == 0) { > return EFI_INVALID_PARAMETER; > } > -- > 2.7.4 >