From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 68F21203525FD for ; Thu, 26 Oct 2017 06:43:26 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id z3so8434421wme.5 for ; Thu, 26 Oct 2017 06:47:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SRkqD8VxLxa8WevSJUI1kZV3tskZCZrsYtn1TDHPw8M=; b=i36pAYKzXEGalWa8fhY/OJfYgDnMkVoM+QaHKviI3JCII6Qj5gleOIzc3hcXJicLTU xZgG5gNCMuMH4Ug0SC0nvFfKGR2kJG9NhrqyLkce9IDlMuXoWltIc8K3ylPX5qsQ2UGV KtfIkVlMxdGFpnSgF6fHcDGLrxri/ENiHoudI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=SRkqD8VxLxa8WevSJUI1kZV3tskZCZrsYtn1TDHPw8M=; b=iWdbzNMUadEtYLJlsdZ4SWepGzPHPxKkYUGaKzpm3n6RK8+6BoTRdgrAzUYn/KMKcV SGg9zgd4sbFLjPbxqCgsGPNeirEsIseTuPSsbgfz71bM+dZTHGHB/KPegMexI9ziJ2j6 IR8YeBIICURmT1v2jq40IZEBNwRGGTu4T/gaGmi5Rgo/7SvCitZlTlvDBbPUCPpW48l1 X5GUQcXgV+xqWQ4UD72qDC5jbGo5OU8XQtsI2kVAsJin13/ucDAoSssTpgMDsL1FeoYP GG4FoQfdlSHCCxToEHYzuAjcfCSPIQ5McePkHFVnxDWgiAH61b8BaIhLTbPVaY8FkVnS igBA== X-Gm-Message-State: AMCzsaU13vpYnBaWvPx4AW53Vvfg5TPT0ycVfv0n/0clSMJo1DO8yCvv dmQCHWGLW0/X44M4hp4iRY5u8w== X-Google-Smtp-Source: ABhQp+RPl1oSU5zkSXQrbDVH7R/M53oTIXpqrJGz7OKI+v6yjBbj6RcyXK9LbwxpLhJZJlJlL9JAbw== X-Received: by 10.28.138.202 with SMTP id m193mr1827167wmd.63.1509025631286; Thu, 26 Oct 2017 06:47:11 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id x70sm838924wmf.0.2017.10.26.06.47.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 06:47:10 -0700 (PDT) Date: Thu, 26 Oct 2017 14:47:08 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, jsd@semihalf.com Message-ID: <20171026134708.evw5jhio2bjpkzpy@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-11-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1508980777-29006-11-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:43:26 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 26, 2017 at 03:19:37AM +0200, Marcin Wojtas wrote: > Changing controller's FIFO default values is not necessary and > possibly can cause instabilities, when using some devices. > Disable the modification and rely on initial settings. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > index 31f207e..6bbe5bc 100755 > --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > @@ -44,20 +44,6 @@ XenonReadVersion ( > SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_SIZE_2B, ControllerVersion); > } > > -STATIC > -VOID > -XenonSetFifo ( > - IN EFI_PCI_IO_PROTOCOL *PciIo > - ) > -{ > - UINTN Data; > - > - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC > - Data = SDHC_SLOT_FIFO_DEFAULT_CONFIG; > - > - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG_SIZE_4B, &Data); > -} > - > // Auto Clock Gating > STATIC > VOID > @@ -634,8 +620,6 @@ XenonInit ( > // Read XENON version > XenonReadVersion (PciIo, &Private->ControllerVersion); > > - XenonSetFifo (PciIo); > - > // Disable auto clock generator > XenonSetAcg (PciIo, FALSE); > > -- > 2.7.4 >