From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4498D203525F5 for ; Thu, 26 Oct 2017 07:36:16 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id g90so3399344wrd.6 for ; Thu, 26 Oct 2017 07:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=VNk5rjQFYtuBYVaBsWrbxghVwgbAemjk73BB6hwN7DM=; b=kYKy1lfl5PtVf57R9VEO2ZfVgkashNTsfd3EPUwSkDdLOMc/9KuV1tePXzHxcg/5Rf nsWbXgm0pEnts1/Wgp6LFb6zXCwo6JdLWiJFFJ5kzF/wVCW3QxqdjjzMK2TkFAPp9oYL PrVRYE/xn9A3QnKkC14KC9LOE2dgtW/U5zqOA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VNk5rjQFYtuBYVaBsWrbxghVwgbAemjk73BB6hwN7DM=; b=aAfsUqS3ha5pEMTdPibN7L8lUXu/vwTeU0dtWaOA67M8/DuRHFbrYsSNs4bkZ400Gh KM0Dh6JIfAIx9u2OwefWF1XDFSzSchKnPraHqilPHn9YAcDdtDjRe+Wb5uBiunF99iFg b/mWzMmafuVxa0XsmIvfhJVXb9wD++MdkCnEWmbKXKClEnljHCgL56kclhUbTYkbfp8z pqRwX3QqpQOlI6+GoGXI9k1xvGq466t4gW5cvd601yrFWnoBjjRIV400vu7LB+u3d155 BrisiWwxmbbwvpMeliWKYiehuVQeu3tVOFYAuSgkjWvQFT4pHaLzdgJRLz/RRUYqcSpQ g/Rw== X-Gm-Message-State: AMCzsaWv+Wcfj/bhLa4pznk9nVDGhOmLAkTvVQntaUGRwGQf/Keyx4n2 H3Hej/rzlXKkWf8cO5K782c/sQ== X-Google-Smtp-Source: ABhQp+Ra2FzJC9CHGSh4aAIOpSZqMQ7O63lAw+Q01QVYwjVTXzA3BWRG9v+XU9eqqNajzEqxlYujow== X-Received: by 10.223.160.132 with SMTP id m4mr5423834wrm.45.1509028800805; Thu, 26 Oct 2017 07:40:00 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m198sm2899254wmg.20.2017.10.26.07.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 07:39:59 -0700 (PDT) Date: Thu, 26 Oct 2017 15:39:58 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org Message-ID: <20171026143958.q4t3kay4boq7xuk6@bivouac.eciton.net> References: <20171025175947.22798-1-ard.biesheuvel@linaro.org> <20171025175947.22798-2-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20171025175947.22798-2-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 01/23] Silicon/SynQuacer: add package with platform headers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 14:36:16 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 25, 2017 at 06:59:25PM +0100, Ard Biesheuvel wrote: > Add a package .DEC description for SynQuacer with an [Includes] > section, and add header files containing descriptions of the > platform's memory map and PCIe configuration. No code yet. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Special thanks for the tedious name case-change. > --- > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 69 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 ++++++++++++++++++ > Silicon/Socionext/SynQuacer/SynQuacer.dec | 20 ++++++ > 3 files changed, 152 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > new file mode 100644 > index 000000000000..a53b9088c3af > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > @@ -0,0 +1,69 @@ > +/** @file > + Physical memory map for SynQuacer > + > + Copyright (c) 2017, Linaro Ltd. All rights reserved.
> + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_ > +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_ > + > +// Memory mapped SPI NOR > +#define SYNQUACER_SPI_NOR_BASE 0x08000000 > +#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB > + > +// On-Chip non-secure ROM > +#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000 > +#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB > + > +// On-Chip Peripherals > +#define SYNQUACER_PERIPHERALS_BASE 0x20000000 > +#define SYNQUACER_PERIPHERALS_SZ 0x0E000000 > + > +// On-Chip non-secure SRAM > +#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000 > +#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_64KB > + > +// GIC-500 > +#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase) > +#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB > +#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase) > +#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB > + > +// GPIO block > +#define SYNQUACER_GPIO_BASE 0x51000000 > +#define SYNQUACER_GPIO_SIZE SIZE_4KB > + > +// eMMC(SDH30) > +#define SYNQUACER_EMMC_BASE 0x52300000 > +#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB > + > +#define SYNQUACER_EEPROM_BASE 0x10000000 > +#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB > + > +// NETSEC > +#define SYNQUACER_NETSEC_BASE 0x522D0000 > +#define SYNQUACER_NETSEC_BASE_SZ SIZE_64KB > + > +#define SYNQUACER_SYSTEM_MEMORY_1_BASE 0x80000000 > +#define SYNQUACER_SYSTEM_MEMORY_1_SZ (SIZE_2GB - SIZE_16MB) > + > +#define SYNQUACER_SYSTEM_MEMORY_2_BASE 0x0880000000ULL > +#define SYNQUACER_SYSTEM_MEMORY_2_SZ (SIZE_32GB - SIZE_2GB) > + > +#define SYNQUACER_SYSTEM_MEMORY_3_BASE 0x8800000000ULL > +#define SYNQUACER_SYSTEM_MEMORY_3_SZ SIZE_32GB > + > +// PCI > +#define SYNQUACER_PCIE_BASE 0x58200000 > +#define SYNQUACER_PCIE_SIZE 0x00200000 > + > +#endif > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > new file mode 100644 > index 000000000000..d2a3f9acbf49 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > @@ -0,0 +1,63 @@ > +/** @file > + PCI memory configuration for SynQuacer > + > + Copyright (c) 2017, Linaro Ltd. All rights reserved.
> + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _SYNQUACER_PLATFORM_PCI_H_ > +#define _SYNQUACER_PLATFORM_PCI_H_ > + > +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000 > +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000 > +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000 > +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000 > + > +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 > +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e > + > +#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 > +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff > +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 > +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 > +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE > + > +#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 > +#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff > +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 > + > +#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 > +#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff > +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000 > + > +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000 > +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000 > +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000 > +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000 > + > +#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 > +#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e > + > +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 > +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff > +#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 > +#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 > +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE > + > +#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 > +#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff > +#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 > + > +#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 > +#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff > +#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000 > + > +#endif > diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec > new file mode 100644 > index 000000000000..c3adf85d3562 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec > @@ -0,0 +1,20 @@ > +# > +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x0001001A > + PACKAGE_NAME = SynQuacer > + PACKAGE_GUID = 9c782fd2-7db1-438d-b51c-2155cee2c5cc > + PACKAGE_VERSION = 0.1 > + > +[Includes] > + Include > -- > 2.11.0 >