From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::236; helo=mail-wr0-x236.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x236.google.com (mail-wr0-x236.google.com [IPv6:2a00:1450:400c:c0c::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 97FF821CEB138 for ; Thu, 26 Oct 2017 07:49:00 -0700 (PDT) Received: by mail-wr0-x236.google.com with SMTP id j15so3438302wre.8 for ; Thu, 26 Oct 2017 07:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=eKB0hLdU5rFOWNVLNZuewjLQGKQbEWgCSwsFrkMp9ys=; b=dxds9OE20AmIMbXlPckCpfKXeYHb+GhhvqMKk1W4CDrEYadUUdVuM6xzGV4AbBAAbF Lv6jAXjosM+M0iOo8LynwkZRQQaMFHn6430uoHBuGmodKU1kWd4rR+nR2D2ff4ukJ5Wp Hfq1lyExPxZjJLPobzNmFBSaQGqVWESu+Id9I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=eKB0hLdU5rFOWNVLNZuewjLQGKQbEWgCSwsFrkMp9ys=; b=p9sTmZX2Gu6QcAT6LkSZ7aAhx927OWDPwNqd9IVZL1ErWNe0FidylTXkNshe+Yw5bR l5KLAT79999N0t6VCfsyleX71tiTikhTbGhmCxldlMF6xqmLCHEPZ3zKXUXBY6ZiZPiC otpOY3KmiZAk6CYSslzWVqnGg4l2lcRhR6SrSkaq1IHe1AANBDLjvsGH2z5Hvz+FTGLZ 05Ouzik/lgAT0sVi09GeWfnFJ0f1Y+j9wDyiQaBohbyRx8wSgbnMsUwDyDnDI/6HED/C /uu0gaGWmKZfZ463EOjlweKFcAt2SeT0JDWf8enz5zTQUgiP/rSwRNjDR04Y1cLVidgL h66A== X-Gm-Message-State: AMCzsaU7R0y2b8MgjGyyBhaFyzKSmJz97B0xJCPIDJcgJeYou+UDwsjo p+dEELhwAX22yGzZAvnJgMjolw== X-Google-Smtp-Source: ABhQp+Qpm4gdZ5X4Y+K7UcP4LdRHuR5YDWDKCUlUpgKjvwJGB8PPv6zZkq1YEd1Hyih6RcAZ8yDcmQ== X-Received: by 10.223.176.176 with SMTP id i45mr5915817wra.240.1509029565373; Thu, 26 Oct 2017 07:52:45 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 68sm1307583wmh.2.2017.10.26.07.52.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Oct 2017 07:52:44 -0700 (PDT) Date: Thu, 26 Oct 2017 15:52:42 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel-01 , Ard Biesheuvel , nadavh@marvell.com, Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , semihalf-dabros-jan Message-ID: <20171026145242.zyzx7tysxq653sex@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> <20171026140200.v33dpi54ri2e3fuu@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 14:49:00 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 26, 2017 at 04:29:39PM +0200, Marcin Wojtas wrote: > 2017-10-26 16:02 GMT+02:00 Leif Lindholm : > >> > Why is Capability.BaseClkFreq the wrong frequency to use? > >> > >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. > >> An alternative would be change this generic type to UINT16 and update > >> field properly during initialization - do you prefer that? > > > > No, I'm still dreaming we might be able to reintegrate this into the > > MdeModulePkg driver in some glorious future. > > Yes, that would be great. I imagine some SDMMC_HOST_PROTOCOL exposing > callbacks to set UHS, custom clock handling, etc (like it's done in > the Linux). Yes, *waves hands*, something like that. > > So what you are basically saying is that this controller is running at > > a higher frequency than is permitted (or even describable) by the > > specification? If so, _that_ needs to be in the commit message (and > > really, a comment by the code as well). > > Yes, this clock value is Xenon controller's quirk. I will mention it > in commit log/comment, but please let know if you wish me to: > a. extend BaseClkFreq to UINT16 and configure it properly during init > b. leave as is with better description only > I lean towards a., it's a very low-cost quirk to be applied. I would actually lean towards b. That way it stands out and is less likely to actually _confuse_ someone in the future. / Leif